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Updated the Configuration for Tomahawk in RM only DEV_EDMA3_LLD_02_10_04_01
authorSundaram Raju <sundaram@ti.com>
Thu, 14 Oct 2010 06:14:37 +0000 (11:44 +0530)
committerSundaram Raju <sundaram@ti.com>
Thu, 14 Oct 2010 06:14:37 +0000 (11:44 +0530)
Signed-off-by: Sundaram Raju <sundaram@ti.com>
packages/ti/sdo/edma3/rm/src/configs/edma3_c6472_cfg.c patch | blob | history
packages/ti/sdo/edma3/rm/src/configs/edma3_tci6486_cfg.c patch | blob | history

diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_c6472_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_c6472_cfg.c
index 27d44db1dcc843c5ee59c47eb333962934335056..7fd8f4e314700f41d262440eb45439d8d2daa4c1 100644 (file)
--- a/packages/ti/sdo/edma3/rm/src/configs/edma3_c6472_cfg.c
+++ b/packages/ti/sdo/edma3/rm/src/configs/edma3_c6472_cfg.c
@@ -199,14 +199,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
                  * on the mapped channel.
                  */
                {
-        0u, 1u, 2u, 3u,
-        4u, 5u, 6u, 7u,
-        8u, 9u, 10u, 11u,
-        12u, 13u, 14u, 15u,
-        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+        16u, 17u, 18u, 19u,
+        20u, 21u, 22u, 23u,
+        24u, 25u, 26u, 27u,
+        28u, 29u, 30u, 31u,
         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
@@ -223,7 +223,7 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
                 * All channels need not be mapped, some can be free also.
                 */
                {
-               0x0000FFFFu,
+               0xFFFF0000u,
                0x00000000u
                }
                }
@@ -236,7 +236,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* Resources owned by Region 0 */
                 /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0xFFFF0000u, 0x00FFFFFFu, 0x00000000u, 0x00000000u,
+               {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -246,7 +246,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00FF0000u, 0x00000000u},
+               {0x000000FFu, 0x00000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -254,12 +254,12 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00FF0000u, 0x00000000u},
+               {0x000000FFu, 0x00000000u},
 
                /* Resources reserved by Region 0 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -269,7 +269,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0x0000FFFFu, 0x00000000u},
+        {0xFFFF0000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -277,14 +277,14 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0x0000FFFFu, 0x00000000u},
+        {0xFFFF0000u, 0x00000000u},
          },
 
          {
                /* Resources owned by Region 1 */
                /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0xFF000000u, 0xFFFFFFFFu, 0x00000000u,
+               {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -294,7 +294,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0xFF000000u, 0x00000000u},
+               {0x0000FF00u, 0x00000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -302,12 +302,12 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0xFF000000u, 0x00000000u},
+               {0x0000FF00u, 0x00000000u},
 
                /* Resources reserved by Region 1 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -317,7 +317,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0x0000FFFFu, 0x00000000u},
+        {0xFFFF0000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -325,16 +325,16 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0x0000FFFFu, 0x00000000u},
+        {0xFFFF0000u, 0x00000000u},
          },
 
          {
                /* Resources owned by Region 2 */
                 /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x000000FFu, 0x00000000u, 0x00000000u, 0x00000000u,
+                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -355,7 +355,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* Resources reserved by Region 2 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -365,7 +365,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0x0000FFFFu, 0x00000000u},
+        {0xFFFF0000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -373,7 +373,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0x0000FFFFu, 0x00000000u},
+        {0xFFFF0000u, 0x00000000u},
          },
 
          {
@@ -382,7 +382,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0xFFFFFF00u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -403,7 +403,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* Resources reserved by Region 3 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -413,7 +413,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdDmaChannels */
                /* 31     0     63    32 */
-               {0x0000FFFFu, 0x00000000u},
+               {0xFFFF0000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -421,7 +421,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdTccs */
                /* 31     0     63    32 */
-               {0x0000FFFFu, 0x00000000u},
+               {0xFFFF0000u, 0x00000000u},
          },
 
          {
@@ -430,7 +430,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0xFFFF0000u, 0x00FFFFFFu, 0x00000000u,
+                0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -451,7 +451,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* Resources reserved by Region 4 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -461,7 +461,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdDmaChannels */
                /* 31     0     63    32 */
-               {0x0000FFFFu, 0x00000000u},
+               {0xFFFF0000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -469,7 +469,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdTccs */
                /* 31     0     63    32 */
-               {0x0000FFFFu, 0x00000000u},
+               {0xFFFF0000u, 0x00000000u},
          },
 
          {
@@ -478,7 +478,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -499,7 +499,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* Resources reserved by Region 5 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -509,7 +509,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdDmaChannels */
                /* 31     0     63    32 */
-               {0x0000FFFFu, 0x00000000u},
+               {0xFFFF0000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -517,7 +517,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdTccs */
                /* 31     0     63    32 */
-               {0x0000FFFFu, 0x00000000u},
+               {0xFFFF0000u, 0x00000000u},
          },
 
       {
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_tci6486_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_tci6486_cfg.c
index fd459ab27bf5585eada8e60c3789618274258da7..382752d7710d2e7c581a505c199d76d0ae855eb9 100644 (file)
--- a/packages/ti/sdo/edma3/rm/src/configs/edma3_tci6486_cfg.c
+++ b/packages/ti/sdo/edma3/rm/src/configs/edma3_tci6486_cfg.c
@@ -199,14 +199,14 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
                  * on the mapped channel.
                  */
                {
-        0u, 1u, 2u, 3u,
-        4u, 5u, 6u, 7u,
-        8u, 9u, 10u, 11u,
-        12u, 13u, 14u, 15u,
-        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+        EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+        16u, 17u, 18u, 19u,\r
+        20u, 21u, 22u, 23u,\r
+        24u, 25u, 26u, 27u,\r
+        28u, 29u, 30u, 31u,\r
         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
         EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
@@ -223,7 +223,7 @@ EDMA3_RM_GblConfigParams edma3GblCfgParams [NUM_EDMA3_INSTANCES] =
                 * All channels need not be mapped, some can be free also.
                 */
                {
-               0x0000FFFFu,
+               0xFFFF0000u,
                0x00000000u
                }
                }
@@ -236,7 +236,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* Resources owned by Region 0 */
                 /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0xFFFF0000u, 0x00FFFFFFu, 0x00000000u, 0x00000000u,
+               {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -246,7 +246,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0x00FF0000u, 0x00000000u},
+               {0x000000FFu, 0x00000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -254,12 +254,12 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0x00FF0000u, 0x00000000u},
+               {0x000000FFu, 0x00000000u},
 
                /* Resources reserved by Region 0 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -269,7 +269,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0x0000FFFFu, 0x00000000u},
+        {0xFFFF0000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -277,14 +277,14 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0x0000FFFFu, 0x00000000u},
+        {0xFFFF0000u, 0x00000000u},
          },
 
          {
                /* Resources owned by Region 1 */
                /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0xFF000000u, 0xFFFFFFFFu, 0x00000000u,
+               {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -294,7 +294,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* ownDmaChannels */
                /* 31     0     63    32 */
-               {0xFF000000u, 0x00000000u},
+               {0x0000FF00u, 0x00000000u},
 
                /* ownQdmaChannels */
                /* 31     0 */
@@ -302,12 +302,12 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* ownTccs */
                /* 31     0     63    32 */
-               {0xFF000000u, 0x00000000u},
+               {0x0000FF00u, 0x00000000u},
 
                /* Resources reserved by Region 1 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -317,7 +317,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0x0000FFFFu, 0x00000000u},
+        {0xFFFF0000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -325,16 +325,16 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0x0000FFFFu, 0x00000000u},
+        {0xFFFF0000u, 0x00000000u},
          },
 
          {
                /* Resources owned by Region 2 */
                 /* ownPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
+               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x000000FFu, 0x00000000u, 0x00000000u, 0x00000000u,
+                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -355,7 +355,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* Resources reserved by Region 2 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -365,7 +365,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdDmaChannels */
         /* 31    0    63     32 */
-        {0x0000FFFFu, 0x00000000u},
+        {0xFFFF0000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -373,7 +373,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdTccs */
         /* 31    0    63     32 */
-        {0x0000FFFFu, 0x00000000u},
+        {0xFFFF0000u, 0x00000000u},
          },
 
          {
@@ -382,7 +382,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0xFFFFFF00u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+                0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -403,7 +403,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* Resources reserved by Region 3 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -413,7 +413,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdDmaChannels */
                /* 31     0     63    32 */
-               {0x0000FFFFu, 0x00000000u},
+               {0xFFFF0000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -421,7 +421,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdTccs */
                /* 31     0     63    32 */
-               {0x0000FFFFu, 0x00000000u},
+               {0xFFFF0000u, 0x00000000u},
          },
 
          {
@@ -430,7 +430,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0xFFFF0000u, 0x00FFFFFFu, 0x00000000u,
+                0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -451,7 +451,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* Resources reserved by Region 4 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -461,7 +461,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdDmaChannels */
                /* 31     0     63    32 */
-               {0x0000FFFFu, 0x00000000u},
+               {0xFFFF0000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -469,7 +469,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdTccs */
                /* 31     0     63    32 */
-               {0x0000FFFFu, 0x00000000u},
+               {0xFFFF0000u, 0x00000000u},
          },
 
          {
@@ -478,7 +478,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* 31     0     63    32     95    64     127   96 */
                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
-                0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
                /* 287  256     319  288     351  320     383  352 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 415  384     447  416     479  448     511  480 */
@@ -499,7 +499,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
                /* Resources reserved by Region 5 */
                /* resvdPaRAMSets */
                /* 31     0     63    32     95    64     127   96 */
-               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                /* 159  128     191  160     223  192     255  224 */
                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                /* 287  256     319  288     351  320     383  352 */
@@ -509,7 +509,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdDmaChannels */
                /* 31     0     63    32 */
-               {0x0000FFFFu, 0x00000000u},
+               {0xFFFF0000u, 0x00000000u},
 
                /* resvdQdmaChannels */
                /* 31     0 */
@@ -517,7 +517,7 @@ EDMA3_RM_InstanceInitConfig defInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_MAX_RE
 
                /* resvdTccs */
                /* 31     0     63    32 */
-               {0x0000FFFFu, 0x00000000u},
+               {0xFFFF0000u, 0x00000000u},
          },
 
       {
Project to include GIT repos for RTOS components including user mode CSL & NetCP LLDs (CPPI/QMSS/PA/RM), PDK components (NWAL/PKTLIB) and Transport Net Lib components (NetAPI/HPLIB) - Project to host low level driver for EDMA3 peripheral used in several C6000, CI and OMAP devices.