Updating/cleaning comments for doxygen
authorAnuj Aggarwal <anuj.aggarwal@ti.com>
Mon, 14 Sep 2009 06:07:08 +0000 (11:37 +0530)
committerAnuj Aggarwal <anuj.aggarwal@ti.com>
Mon, 14 Sep 2009 06:07:08 +0000 (11:37 +0530)
16 files changed:
packages/ti/sdo/edma3/drv/edma3_drv.h
packages/ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h [changed mode: 0644->0755]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_da830_cfg.c [changed mode: 0644->0755]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_da830_int_reg.c [changed mode: 0644->0755]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6498_cfg.c [changed mode: 0644->0755]
packages/ti/sdo/edma3/drv/sample/src/sample_cs.c [changed mode: 0644->0755]
packages/ti/sdo/edma3/drv/src/edma3.h [changed mode: 0644->0755]
packages/ti/sdo/edma3/drv/src/edma3_drv_adv.c [changed mode: 0644->0755]
packages/ti/sdo/edma3/drv/src/edma3_drv_basic.c
packages/ti/sdo/edma3/drv/src/edma3_drv_init.c [changed mode: 0644->0755]
packages/ti/sdo/edma3/rm/edma3_common.h
packages/ti/sdo/edma3/rm/edma3_rm.h
packages/ti/sdo/edma3/rm/src/edma3_log.h [changed mode: 0644->0755]
packages/ti/sdo/edma3/rm/src/edma3_rm_gbl_data.c [changed mode: 0644->0755]
packages/ti/sdo/edma3/rm/src/edma3resmgr.c
packages/ti/sdo/edma3/rm/src/edma3resmgr.h [changed mode: 0644->0755]

index 6343122f461ef3653ec3de3c5d51ee14c746413d..3e595cb24f8d04a8b2f6254a30cd3db33584a78f 100755 (executable)
  *
 */
 
+/** @defgroup EDMA3_LLD_DRV_API EDMA3 Driver
+ *
+ * @section Introduction
+ *
+ * @subsection xxx Overview
+ *  EDMA3 Driver is a functional library providing APIs for programming,
+ *  scheduling and synchronizing with EDMA transfers and many more.
+ */
+
 #ifndef _EDMA3_DRV_H_
 #define _EDMA3_DRV_H_
 
@@ -50,371 +59,44 @@ extern "C" {
 #endif
 
 /**
- * \defgroup Edma3DrvMain EDMA3 Driver Interface Definition
- *
- * Top-level Encapsulation of all documentation for EDMA3 Driver
- *
- * @{
- */
-
-
-/*---------------------------------------------------------------------------*/
-/*------------------Usage Guidelines Start-----------------------------------*/
-/*---------------------------------------------------------------------------*/
-
+@defgroup EDMA3_LLD_DRV_SYMBOL  EDMA3 Driver Symbols
+@ingroup EDMA3_LLD_DRV_API
+*/
 /**
- * \defgroup Edma3DrvUsage EDMA3 Driver Usage Guidelines
- *
- * Guidelines for typical usage of EDMA3 Driver.
- *
- * @{
- */
-
-
-/**
-  \brief Usage of EDMA3 Driver.
-
-    -# Create EDMA3 Driver Object (one for each EDMA3 hardware instance)
-        - EDMA3_DRV_Result result = EDMA3_DRV_SOK;
-        - unsigned int edma3HwInstanceId = 0;
-        - EDMA3_DRV_GblConfigParams *gblCfgParams = NULL;
-        - Init-time Configuration structure for EDMA3 controller, to provide
-            Global SoC specific Information. This could be NULL also. In that
-            case, static configuration will be taken.
-        - result = EDMA3_DRV_create (edma3HwInstanceId, gblCfgParams, NULL);
-
-    -# Open EDMA3 driver Instance
-        - Steps
-            - EDMA3_DRV_InitConfig initCfg;
-            - EDMA3_DRV_Handle hEdma = NULL;
-            - EDMA3_OS_SemAttrs semAttrs = {EDMA3_OS_SEMTYPE_FIFO, NULL};
-            - EDMA3_DRV_Result edmaResult;
-                -To get the error code while opening driver instance
-
-            -# initCfg.regionId = One of the possible regions available
-               for eg, (EDMA3_RM_RegionId)0 or (EDMA3_RM_RegionId)1 etc, for
-               different masters.
-
-            -# initCfg.isMaster =  TRUE/FALSE (Whether this EDMA3
-               DRV instance is Master or not. The EDMA3 Shadow Region tied to
-               the Master DRV Instance will ONLY receive the EDMA3 interrupts
-               (error or completion), if enabled).
-
-            -# initCfg.drvSemHandle =
-               EDMA3 DRV Instance specific semaphore handle. It should
-               be provided by the user for proper sharing of resources.
-               - edma3Result = edma3OsSemCreate(1, &semAttrs,
-                                                &initCfg.drvSemHandle);
-
-            -# initCfg.drvInstInitConfig =
-               Init-time Region Specific Configuration Structure. It can be
-               provided by the user at run-time. If not provided by the user,
-               this info would be taken from the platform specific config file,
-               if it exists.
-
-            -# initCfg.drvInstInitConfig->ownDmaChannels[] =
-               The bitmap(s) which indicate the DMA channels owned by this
-               instance of the EDMA3 Driver\n
-               E.g. A '1' at bit position 24 indicates that this instance of
-               the EDMA3 Driver owns DMA Channel Id 24\n
-               Later when a request is made based on a particular Channel Id,
-               the EDMA3 Driver will check first if it owns that channel.
-               If it doesnot own it, EDMA3 Driver returns error.
-            -# initCfg.drvInstInitConfig->ownQdmaChannels[] =
-               The bitmap(s) which indicate the QDMA channels owned by this
-               instance of the EDMA3 Driver \n
-            -# initCfg.drvInstInitConfig->ownPaRAMSets[] =
-               The bitmap(s) which indicate the PaRAM Sets owned by this
-               instance of the EDMA3 Driver \n
-            -# initCfg.drvInstInitConfig->ownTccs[] =
-               The bitmap(s) which indicate the TCCs owned by this
-               instance of the EDMA3 Driver \n
-
-            -# initCfg.drvInstInitConfig->resvdDmaChannels[] =
-               The bitmap(s) which indicate the DMA channels reserved by this
-               instance of the EDMA3 Driver \n
-               E.g. A '1' at bit position 24 indicates that this instance of
-               the EDMA3 Driver reserves Channel Id 24\n
-               These channels are reserved and may be mapped to HW events,
-               these are not given to 'EDMA3_DRV_DMA_CHANNEL_ANY' requests.\n
-            -# initCfg.drvInstInitConfig->resvdQdmaChannels[] =
-               The bitmap(s) which indicate the QDMA channels reserved by this
-               instance of the EDMA3 Driver \n
-               E.g. A '1' at bit position 1 indicates that this instance of
-               the EDMA3 Driver reserves QDMA Channel Id 1\n
-               These channels are reserved for some specific purpose,
-               these are not given to 'EDMA3_DRV_QDMA_CHANNEL_ANY' request\n
-            -# initCfg.drvInstInitConfig->resvdPaRAMSets[] =
-               PaRAM Sets which are reserved by this Region;
-            -# initCfg.drvInstInitConfig->resvdTccs[] =
-               TCCs which are reserved by this Region;
-
-
-            -# initCfg.gblerrCb =
-               Instance wide callback function to catch non-channel specific
-               errors;
-            -# initCfg.gblerrData =
-               Application data to be passed back to the callback function;
-
-            -# hEdma = EDMA3_DRV_open(edma3HwInstanceId, &initCfg, &edmaResult);
-
-    -# EDMA3 driver APIs
-        - EDMA3_RM_ResDesc      resObj;
-        - EDMA3_DRV_Result      result;
-        - unsigned int          ch1Id = 0;
-        - unsigned int          ch2Id = 0;
-        - unsigned int          tcc1 = 0;
-        - unsigned int          tcc2 = 0;
-        - unsigned int          qCh1Id = 0;
-        - unsigned int          qTcc1 = 0;
-        - unsigned int          qCh2Id = 0;
-        - unsigned int          qTcc2 = 0;
-        - unsigned int          paRAMId;
-        - int                   srcbidx = 0;
-        - int                   desbidx = 0;
-        - int                   srccidx = 0;
-        - int                   descidx = 0;
-        - unsigned int          acnt = 0;
-        - unsigned int          bcnt = 0;
-        - unsigned int          ccnt = 0;
-        - unsigned int          bcntreload = 0;
-        - EDMA3_DRV_SyncType    synctype;
-        - EDMA3_RM_TccCallback  tccCb;
-        - void *cbData;
-        -
-        - Use Case 1: Memory to memory transfer on any available
-        -             DMA Channel\n\n
-            - tcc1   = EDMA3_DRV_TCC_ANY;
-            - ch1Id  = EDMA3_DRV_DMA_CHANNEL_ANY;
-            - result = EDMA3_DRV_requestChannel (hEdma, &ch1Id, &tcc1,
-                               (EDMA3_RM_EventQueue)0, &callback1, NULL);
-
-            - result = EDMA3_DRV_setSrcParams (hEdma, ch1Id,
-                                                (unsigned int)(srcBuff1),
-                                                EDMA3_DRV_ADDR_MODE_INCR,
-                                                EDMA3_DRV_W8BIT);
-            - result = EDMA3_DRV_setDestParams (hEdma, ch1Id,
-                                                (unsigned int)(dstBuff1),
-                                                EDMA3_DRV_ADDR_MODE_INCR,
-                                                EDMA3_DRV_W8BIT);
-
-            - Set EDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload,
-                                            SyncType)
-              acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;
-              synctype = EDMA3_DRV_SYNC_A;
-            - result = EDMA3_DRV_setTransferParams (hEdma, ch1Id, acnt, bcnt,
-                                                    ccnt, bcntreload, synctype);
-
-            - Set srcbidx and srccidx to the appropriate values
-            - srcbidx = acnt; srccidx = acnt;
-            - result = EDMA3_DRV_setSrcIndex  (hEdma, ch1Id, srcbidx, srccidx);
-
-            - Set desbidx and descidx to the appropriate values
-            - desbidx = acnt; descidx = acnt;
-            - result = EDMA3_DRV_setDestIndex (hEdma, ch1Id, desbidx, descidx);
-
-            - Enable the final completion interrupt.
-            - result = EDMA3_DRV_setOptField (hEdma, ch1Id,
-                               EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
-
-            - Enable the transfer
-            - result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
-                                        EDMA3_DRV_TRIG_MODE_MANUAL);
-
-        - Use Case 2: Linked memory to memory transfer on any available
-        -             DMA Channel\n\n
-            - Perform steps as for Use Case 1 for the Master logical channel
-                ch1Id for configuration. DONOT enable the transfer for ch1Id.
-            - Configure link channel, ch2Id.
-            - tcc2   = EDMA3_DRV_TCC_ANY;
-            - ch2Id  = EDMA3_DRV_LINK_CHANNEL;
-            - result = EDMA3_DRV_requestChannel (hEdma, &ch2Id, &tcc2,
-                               (EDMA3_RM_EventQueue)0, &callback2, NULL);
-
-            - result = EDMA3_DRV_setSrcParams (hEdma, ch2Id,
-                                            (unsigned int)(srcBuff2),
-                                            EDMA3_DRV_ADDR_MODE_INCR,
-                                            EDMA3_DRV_W8BIT);
-            - result = EDMA3_DRV_setDestParams (hEdma, ch2Id,(
-                                            unsigned int)(dstBuff2),
-                                            EDMA3_DRV_ADDR_MODE_INCR,
-                                            EDMA3_DRV_W8BIT);
-
-            - result = EDMA3_DRV_setSrcIndex  (hEdma, ch2Id, srcbidx, srccidx);
-            - result = EDMA3_DRV_setDestIndex (hEdma, ch2Id, desbidx, descidx);
-
-            - result = EDMA3_DRV_setTransferParams (hEdma, ch2Id, acnt, bcnt,
-                                ccnt, bcntreload, synctype);
-
-            - Link both the channels
-            - result = EDMA3_DRV_linkChannel (hEdma, ch1Id, ch2Id);
-
-            - Enable the final completion interrupts on both the channels
-            - result = EDMA3_DRV_setOptField (hEdma, ch1Id,
-                               EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
-            - result = EDMA3_DRV_setOptField (hEdma, ch2Id,
-                               EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
-
-            - Enable the transfer on channel 1.
-            - result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
-                                        EDMA3_DRV_TRIG_MODE_MANUAL);
-            - Wait for the completion interrupt on Ch1 and then enable the
-              transfer again for the LINK channel, to provide the required
-              sync event.
-            - result = EDMA3_DRV_enableTransfer (hEdma, ch1Id,
-                                        EDMA3_DRV_TRIG_MODE_MANUAL);
-
-            - Note: Enabling of transfers on channel 1 (for master and link
-              channel) is required as many number of times as the sync events
-              are required. For ASync mode, number of sync events=(bcnt * ccnt)
-              and for ABSync mode, number of sync events = ccnt.
-
-        - Use Case 3: Memory to memory transfer on any available
-        -             QDMA Channel\n\n
-            - qTcc1  = EDMA3_DRV_TCC_ANY;
-            - qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;
-
-            - result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,
-                               (EDMA3_RM_EventQueue)0, &callback1, NULL);
-
-            - Set the QDMA trigger word.
-            - result =  EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,
-                                                    EDMA3_RM_QDMA_TRIG_DST);
-            - Note: DONOT write the destination address (trigger word) before
-                    completing the configuration as it will trigger the
-                    transfer. Also, DONOT use EDMA3_DRV_setDestParams() to set
-                    the destination address as it also sets other parameters.
-                    Use EDMA3_DRV_setPaRAMEntry() to set the destination address
-
-            - result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,
-                                                (unsigned int)(srcBuff1),
-                                                EDMA3_DRV_ADDR_MODE_INCR,
-                                                EDMA3_DRV_W8BIT);
-
-            - Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload,
-                                            SyncType)
-              acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;
-              synctype = EDMA3_DRV_SYNC_A;
-            - result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,
-                                                    ccnt, bcntreload, synctype);
-
-            - srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
-            - result = EDMA3_DRV_setSrcIndex  (hEdma, qCh1Id, srcbidx, srccidx);
-            - result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);
-
-            - Enable the final completion interrupt.
-            - result = EDMA3_DRV_setOptField  (hEdma, qCh1Id,
-                               EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
-
-            - Set the Destination Addressing Mode as Increment
-            - result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
-                                            EDMA3_DRV_OPT_FIELD_DAM,
-                                            EDMA3_DRV_ADDR_MODE_INCR);
-
-            - Trigger the QDMA channel by writing the destination address
-            - result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id,
-                                                EDMA3_DRV_PARAM_ENTRY_DST,
-                                                (unsigned int)(dstBuff1));
-
-        -
-        - Use Case 4: Linked memory to memory transfer on any available
-        -             QDMA Channel\n\n
-            - Setup for any QDMA Channel
-            - qTcc1  = EDMA3_DRV_TCC_ANY;
-            - qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;
-            - result = EDMA3_DRV_requestChannel (hEdma, &qCh1Id, &qTcc1,
-                               (EDMA3_RM_EventQueue)0, &callback1, NULL);
-
-            - Setup for Channel 2
-            - qCh2Id = EDMA3_DRV_LINK_CHANNEL;
-            - qTcc2  = EDMA3_DRV_TCC_ANY;
-            - result = EDMA3_DRV_requestChannel (hEdma, &qCh2Id, &qTcc2,
-                                                (EDMA3_RM_EventQueue)0,
-                                                &callback2, NULL);
-
-            - result = EDMA3_DRV_setSrcParams (hEdma, qCh2Id,
-                                                (unsigned int)(srcBuff2),
-                                                EDMA3_DRV_ADDR_MODE_INCR,
-                                                EDMA3_DRV_W8BIT);
-            - result = EDMA3_DRV_setDestParams(hEdma, qCh2Id,
-                                                (unsigned int)(dstBuff2),
-                                                EDMA3_DRV_ADDR_MODE_INCR,
-                                                EDMA3_DRV_W8BIT);
-
-            - acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;
-              synctype = EDMA3_DRV_SYNC_A;
-            - result = EDMA3_DRV_setTransferParams (hEdma, qCh2Id, acnt, bcnt,
-                                                    ccnt, BRCnt,
-                                                    EDMA3_DRV_SYNC_A);
-
-            - srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
-            - result = EDMA3_DRV_setSrcIndex  (hEdma, qCh2Id, srcbidx, srccidx);
-            - result = EDMA3_DRV_setDestIndex (hEdma, qCh2Id, desbidx, descidx);
-
-            - result = EDMA3_DRV_setOptField (hEdma, qCh2Id,
-                               EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
-
-            - Make the PaRAM Set associated with qCh2Id as Static
-            - result = EDMA3_DRV_setOptField (hEdma, qCh2Id,
-                                            EDMA3_DRV_OPT_FIELD_STATIC, 1u);
-
-            - Link both the channels
-            - result = EDMA3_DRV_linkChannel (hEdma,qCh1Id,qCh2Id);
-
-            - Set the QDMA trigger word.
-            - result = EDMA3_DRV_setQdmaTrigWord (hEdma, qCh1Id,
-                               EDMA3_DRV_QDMA_TRIG_DST);
-            - Note: DONOT write the destination address (trigger word) before
-                    completing the configuration as it'll trigger the transfer.
-                    Also, DONOT use EDMA3_DRV_setDestParams () function to set
-                    the destination address as it also sets other parameters.
-                    Use EDMA3_DRV_setPaRAMEntry() to set the dest address.
-
-            - result = EDMA3_DRV_setSrcParams (hEdma, qCh1Id,
-                                                (unsigned int)(srcBuff1),
-                                                EDMA3_DRV_ADDR_MODE_INCR,
-                                                EDMA3_DRV_W8BIT);
-
-            - Set QDMA transfer parameters (aCnt, bCnt, cCnt, bCntReload,
-                                            SyncType)
-              acnt = 256; bcnt = 1; ccnt = 1, bcntreload = 0;
-              synctype = EDMA3_DRV_SYNC_A;
-            - result = EDMA3_DRV_setTransferParams (hEdma, qCh1Id, acnt, bcnt,
-                                                ccnt, bcntreload, synctype);
-
-            - srcbidx = acnt; srccidx = acnt; desbidx = acnt; descidx = acnt;
-            - result = EDMA3_DRV_setSrcIndex  (hEdma, qCh1Id, srcbidx, srccidx);
-            - result = EDMA3_DRV_setDestIndex (hEdma, qCh1Id, desbidx, descidx);
-
-            - result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
-                               EDMA3_DRV_OPT_FIELD_TCINTEN, 1);
-
-            - Set the Destination Addressing Mode as Increment
-            - result = EDMA3_DRV_setOptField (hEdma, qCh1Id,
-                                            EDMA3_DRV_OPT_FIELD_DAM,
-                                            EDMA3_DRV_ADDR_MODE_INCR);
-
-            - Trigger the QDMA channel by writing the destination address
-            - result = EDMA3_DRV_setPaRAMEntry (hEdma, qCh1Id,
-                                                EDMA3_DRV_PARAM_ENTRY_DST,
-                                                (unsigned int)(dstBuff1));
+@defgroup EDMA3_LLD_DRV_DATASTRUCT  EDMA3 Driver Data Structures
+@ingroup EDMA3_LLD_DRV_API
+*/
+/**
+@defgroup EDMA3_LLD_DRV_FUNCTION  EDMA3 Driver APIs
+@ingroup EDMA3_LLD_DRV_API
+*/
 
+/**
+@defgroup EDMA3_LLD_DRV_SYMBOL_DEFINE  EDMA3 Driver Defines
+@ingroup EDMA3_LLD_DRV_SYMBOL
+*/
+/**
+@defgroup EDMA3_LLD_DRV_SYMBOL_ENUM  EDMA3 Driver Enums
+@ingroup EDMA3_LLD_DRV_SYMBOL
 */
-/* @} Edma3DrvUsage */
 
-/*---------------------------------------------------------------------------*/
-/*------------------Usage Guidelines End-------------------------------------*/
-/*---------------------------------------------------------------------------*/
+/**
+@defgroup EDMA3_LLD_DRV_FUNCTION_INIT  EDMA3 Driver Initialization APIs
+@ingroup EDMA3_LLD_DRV_FUNCTION
+*/
+/**
+@defgroup EDMA3_LLD_DRV_FUNCTION_BASIC  EDMA3 Driver Basic APIs
+@ingroup EDMA3_LLD_DRV_FUNCTION
+*/
+/**
+@defgroup EDMA3_LLD_DRV_FUNCTION_ADVANCED  EDMA3 Driver Advanced APIs
+@ingroup EDMA3_LLD_DRV_FUNCTION
+*/
 
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_DEFINE
+ @{ */
 
-/**
- * \defgroup Edma3DrvErrorCode EDMA3 Driver Error Codes
- *
- * Error Codes returned by the EDMA3 Driver
- *
- * @{
- */
-/** EDMA3 Driver Error Codes Base define */
+/** @brief EDMA3 Driver Error Codes Base define */
 #define EDMA3_DRV_E_BASE                        (-128)
 
 /**
@@ -483,9 +165,6 @@ extern "C" {
 /** EDMA3 Driver Instance does not exist, it is not opened yet */
 #define EDMA3_DRV_E_INST_NOT_OPENED         (EDMA3_DRV_E_BASE-16)
 
-/* @} Edma3DrvErrorCode */
-
-
 /**
  * This define is used to specify that a DMA channel is NOT tied to any PaRAM
  * Set and hence any available PaRAM Set could be used for that DMA channel.
@@ -508,7 +187,12 @@ extern "C" {
  */
 #define EDMA3_DRV_CH_NO_TCC_MAP             EDMA3_RM_CH_NO_TCC_MAP
 
+/**
+@}
+*/
 
+/** @addtogroup EDMA3_LLD_DRV_DATASTRUCT
+ @{ */
 
 /**\struct  EDMA3_DRV_GblConfigParams
  * \brief   Init-time Configuration structure for EDMA3
@@ -660,8 +344,6 @@ typedef struct  {
     unsigned int        dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS];
     } EDMA3_DRV_GblConfigParams;
 
-
-
 /**\struct  EDMA3_DRV_InstanceInitConfig
  * \brief   Init-time Region Specific Configuration structure for
  * EDMA3 Driver, to provide region specific Information.
@@ -776,8 +458,6 @@ typedef struct
     unsigned int        resvdTccs[EDMA3_MAX_TCC_DWRDS];
 }EDMA3_DRV_InstanceInitConfig;
 
-
-
 /**\struct      EDMA3_DRV_InitConfig
  * \brief       Used to Initialize the EDMA3 Driver Instance
  *
@@ -827,8 +507,6 @@ typedef struct
     void                    *gblerrData;
 } EDMA3_DRV_InitConfig;
 
-
-
 /**\struct      EDMA3_DRV_MiscParam
  * \brief       Used to specify the miscellaneous options during EDMA3 Driver
  * Initialization.
@@ -850,6 +528,12 @@ typedef struct {
     unsigned short          param;
 }EDMA3_DRV_MiscParam;
 
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_INIT
+ @{ */
 
 /**
  * \brief   Create EDMA3 Driver Object
@@ -886,8 +570,6 @@ typedef struct {
 EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId,
                                 const EDMA3_DRV_GblConfigParams *gblCfgParams,
                                 const void *miscParam);
-
-
 /**
  * \brief Delete EDMA3 Driver Object
  *
@@ -911,8 +593,6 @@ EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId,
 EDMA3_DRV_Result EDMA3_DRV_delete (unsigned int phyCtrllerInstId,
                                     const void *param);
 
-
-
 /**
  * \brief   Open EDMA3 Driver Instance
  *
@@ -953,7 +633,6 @@ EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int phyCtrllerInstId,
                         const EDMA3_DRV_InitConfig *initCfg,
                         EDMA3_DRV_Result *errorCode);
 
-
 /**
  * \brief Close the EDMA3 Driver Instance.
  *
@@ -973,15 +652,12 @@ EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int phyCtrllerInstId,
 EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
                                 const void *param);
 
-
-
 /**
- * \defgroup Edma3DrvChannelSetup EDMA3 Driver Channel Setup
- *
- * Channel related Interface of the EDMA3 Driver
- *
- * @{
- */
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_DEFINE
+ @{ */
 
 /* Defines for Logical Channel Values */
 /*---------------------------------------------------------------------------*/
@@ -1019,24 +695,31 @@ EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
 #define EDMA3_DRV_LINK_CHANNEL                      1005u
 
 /**
- * Used to specify any available PaRAM Set while requesting
- * one. Used in the API EDMA3_DRV_requestChannel(), for Link channels.
+ * Used to specify any available PaRAM Set while requesting one. Used in the
+ * API EDMA3_DRV_requestChannel(), for Link channels.
+ * TCC code should also be specified and it will be used to populate the LINK
+ * field of the PaRAM Set. Without TCC code, the call will fail.
  * PaRAM Set from the pool of (owned && non_reserved && available_right_now)
  * PaRAM Sets will be chosen and returned.
  */
 #define EDMA3_DRV_LINK_CHANNEL_WITH_TCC                                1006u
-/*---------------------------------------------------------------------------*/
 
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
 
 /**
  * \brief DMA Channels assigned to different Hardware Events.
+ *
  * They should be used while requesting a specific DMA channel.
  * One possible usage is to maintain a SoC specific file, which will
  * contain the mapping of these hardware events to the respective
  * peripherals for better understanding and lesser probability of
  * errors. Also, if any event associated with a particular peripheral
  * gets changed, only that SoC specific file needs to be changed.
- *
  * for eg, the sample SoC specific file "soc.h" can have these defines:
  *
  * #define EDMA3_DRV_HW_CHANNEL_MCBSP_TX        EDMA3_DRV_HW_CHANNEL_EVENT_2
@@ -1178,10 +861,21 @@ typedef enum
     EDMA3_DRV_HW_CHANNEL_EVENT_63
 } EDMA3_DRV_HW_CHANNEL_EVENT;
 
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_DEFINE
+ @{ */
 
 /**
  * \brief QDMA Channel defines
- * They should be used while requesting a specific QDMA channel.
+ *
+ * They should be used while requesting a specific QDMA channel in API
+ * EDMA3_DRV_requestChannel() as the argument (*pLch). Please note that
+ * these defines should ONLY be used in the API EDMA3_DRV_requestChannel() and
+ * not in any other API to perform further operations. They are only provided
+ * to allow user allocate specific QDMA channels.
  */
 /** QDMA Channel 0 */
 #define EDMA3_DRV_QDMA_CHANNEL_0    (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
@@ -1200,7 +894,12 @@ typedef enum
 /** QDMA Channel 7 */
 #define EDMA3_DRV_QDMA_CHANNEL_7    (EDMA3_DRV_QDMA_CHANNEL_0+7u)
 
+/**
+@}
+*/
 
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_BASIC
+ @{ */
 
 /**
  *  \brief Request a DMA/QDMA/Link channel.
@@ -1210,15 +909,25 @@ typedef enum
  *
  * This API is used to allocate a logical channel (DMA/QDMA/Link) along with
  * the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are
- * also allocated along with the requested channel. For Link channel, ONLY a
- * PaRAM Set is allocated.
+ * also allocated along with the requested channel. User can also specify a
+ * specific TCC which needs to be allocated with the DMA/QDMA channel or else
+ * can request any available TCC.
+ *
+ * For Link channels, ONLY a PaRAM Set is allocated and the allocated PaRAM Set
+ * number is returned as the logical channel no. A TCC code can also be
+ * specified while making the request. This TCC code will be copied to the
+ * LINK field of the allocated PaRAM Set and will be associated with the Link
+ * channel.
  *
- * User can request a specific logical channel by passing the channel id in
- * 'pLCh'. Note that the channel id is the same as the actual resource id in
- * case of DMA channels. To allocate specific QDMA channels, user SHOULD use the
- * defines EDMA3_DRV_QDMA_CHANNEL_X mentioned above.
+ * User can request a specific logical channel - DMA, QDMA and Link, by passing
+ * the channel id in 'pLCh'. Note that the channel id is the same as the actual
+ * resource id in case of DMA channels and Link channels. For DMA channels,
+ * channel id lies between 0 and (max dma channels - 1). For Link channels,
+ * channel id lies between (max dma channels) and (max param sets - 1). To
+ * allocate specific QDMA channels, user SHOULD use the defines
+ * EDMA3_DRV_QDMA_CHANNEL_X mentioned above.
  *
- * User can also request ANY available logical channel also by specifying the
+ * User can also request ANY available logical channel by specifying the
  * below mentioned values in '*pLCh':
  *  a)  EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels
  *  b)  EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and
@@ -1226,12 +935,18 @@ typedef enum
  *      value to request link channels (PaRAM Sets used for linking purpose
  *      only), unless he wants to use some specific link channels (PaRAM Sets)
  *      which is also allowed.
+ *  d)  EDMA3_DRV_LINK_CHANNEL_WITH_TCC: For Link channels. User should
+ *      use this value to request link channels with TCC code.
  *
  * This API internally uses EDMA3_RM_allocResource () to allocate the desired
  * resources (DMA/QDMA channel, PaRAM Set and TCC).
  *
- * This API also registers a specific callback function against the allocated
- * TCC.
+ * This API also registers a specific callback function, in case the same is
+ * provided, against the allocated TCC. To do this, this API calls
+ * EDMA3_RM_registerTccCb(), which is a part of the Resource Manager. Please
+ * note that the interrupts are enabled for the specific TCC only if callback
+ * function is provided. In the absence of this, the API assumes that the
+ * requested logical channel is going to be used in Poll mode environment.
  *
  * For DMA/QDMA channels, after allocating all the EDMA3 resources, this API
  * sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets
@@ -1266,6 +981,11 @@ typedef enum
  *                                      - to be linked to some other Master
  *                                      - channel.
  *
+ *                                      - EDMA3_DRV_LINK_CHANNEL_WITH_TCC
+ *                                      - For requesting a DMA Slave Channel,
+ *                                      - to be linked to some other Master
+ *                                      - channel, with a TCC associated with it.
+ *
  *                                      In case user passes a specific channel
  *                                      Id, pLCh value is left unchanged. In
  *                                      case user requests ANY available
@@ -1275,12 +995,10 @@ typedef enum
  *  \note   To request  a PaRAM Set for the purpose of
  *          linking to another channel,  call the function with
  *
- *          *pLCh = EDMA3_DRV_LINK_CHANNEL;
+ *          *pLCh = EDMA3_DRV_LINK_CHANNEL or EDMA3_DRV_LINK_CHANNEL_WITH_TCC
  *
  *          This function will update *pLCh with the allocated Link channel
- *          handle. This handle could be DIFFERENT from the actual PaRAM Set
- *          allocated by the Resource Manager internally. So user SHOULD NOT
- *          assume the handle as the PaRAM Set Id.
+ *          handle.
  *
  *  \param  pTcc             [IN/OUT]   The channel number on which the
  *                                      completion/error interrupt is generated.
@@ -1328,7 +1046,6 @@ EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
                                     EDMA3_RM_TccCallback tccCb,
                                     void *cbData);
 
-
 /**
  * \brief Free the specified channel (DMA/QDMA/Link) and its associated
  * resources (PaRAM Set, TCC etc) and removes various mappings.
@@ -1360,8 +1077,6 @@ EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
 EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
                                                 unsigned int channelId);
 
-
-
 /**
  *  \brief  Disables the DMA Channel by clearing the Event Enable Register and
  *     clears Error Register & Secondary Event Register for a specific DMA channel.
@@ -1381,6 +1096,12 @@ EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
 EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
                                                     unsigned int channelId);
 
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
 
 /**
  * \brief  Link two logical channels.
@@ -1392,11 +1113,10 @@ EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
  * channel (lCh1) to point it to the PaRAM set associated with second logical
  * channel (lCh2).
  *
- * It also sets the TCC field of PaRAM set associated with second logical
- * channel to the same as that of the first logical channel.
- *
- * After linking the channels, user should not update any PaRAM Set of the
- * channel.
+ * It also sets the TCC field of PaRAM set of second logical channel to the
+ * same as that of the first logical channel, only if the TCC field doesnot
+ * contain a valid TCC code. In case the second logical channel has its own TCC,
+ * the TCC field remains unchanged.
  *
  * \param   hEdma           [IN]    Handle to the EDMA Driver Instance.
  * \param   lCh1            [IN]    Logical Channel to which particular channel
@@ -1420,8 +1140,6 @@ EDMA3_DRV_Result EDMA3_DRV_linkChannel ( EDMA3_DRV_Handle hEdma,
                                                 unsigned int lCh1,
                                                 unsigned int lCh2);
 
-
-
 /**
  * \brief  Unlink the channel from the earlier linked logical channel.
  *
@@ -1440,17 +1158,12 @@ EDMA3_DRV_Result EDMA3_DRV_linkChannel ( EDMA3_DRV_Handle hEdma,
 EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma,
                                                     unsigned int lCh);
 
-/* @} Edma3DrvChannelSetup */
-
-
-
 /**
- * \defgroup Edma3DrvTransferSetupType EDMA3 Driver Typical EDMA Transfer Setup
- *
- * The typical EDMA transfer related Interface of the EDMA3 Driver
- *
- * @{
- */
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
 
 /**
  * \brief OPT Field Offset.
@@ -1534,7 +1247,6 @@ typedef enum
 
 } EDMA3_DRV_OptField;
 
-
 /**
  * \brief EDMA Addressing modes
  *
@@ -1562,8 +1274,6 @@ typedef enum
 
 } EDMA3_DRV_AddrMode;
 
-
-
 /**
  * \brief EDMA Transfer Synchronization type.
  *
@@ -1606,8 +1316,6 @@ typedef enum
 
 } EDMA3_DRV_SyncType;
 
-
-
 /**
  * \brief True/False: PaRAM set is Static or not. A Static PaRAM set
  * is updated or linked after TR is submitted.
@@ -1631,7 +1339,6 @@ typedef enum
     EDMA3_DRV_STATIC_EN       = 1
 } EDMA3_DRV_StaticMode;
 
-
 /**
  * \brief EDMA3 FIFO width.
  *
@@ -1662,9 +1369,6 @@ typedef enum
 
 } EDMA3_DRV_FifoWidth;
 
-
-
-
 /**
  * \brief Transfer complete code mode.
  * Indicates the point at which a transfer is considered completed for
@@ -1683,7 +1387,6 @@ typedef enum
     EDMA3_DRV_TCCMODE_EARLY       = 1
 } EDMA3_DRV_TccMode;
 
-
 /**
  * \brief Transfer complete interrupt enable.
  */
@@ -1703,7 +1406,6 @@ typedef enum
     EDMA3_DRV_TCINTEN_EN       = 1
 } EDMA3_DRV_TcintEn;
 
-
 /**
  * \brief Intermediate Transfer complete interrupt enable.
  */
@@ -1724,7 +1426,6 @@ typedef enum
     EDMA3_DRV_ITCINTEN_EN       = 1
 } EDMA3_DRV_ItcintEn;
 
-
 /**
  * \brief Transfer complete chaining enable.
  */
@@ -1743,7 +1444,6 @@ typedef enum
     EDMA3_DRV_TCCHEN_EN       = 1
 } EDMA3_DRV_TcchEn;
 
-
 /**
  * \brief Intermediate Transfer complete chaining enable.
  */
@@ -1762,6 +1462,12 @@ typedef enum
     EDMA3_DRV_ITCCHEN_EN       = 1
 } EDMA3_DRV_ItcchEn;
 
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_DATASTRUCT
+ @{ */
 
 /**
  * \brief Structure to be used to configure interrupt generation
@@ -1782,7 +1488,12 @@ typedef struct
     EDMA3_DRV_ItcintEn  itcintEn;
 } EDMA3_DRV_ChainOptions;
 
+/**
+@}
+*/
 
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_BASIC
+ @{ */
 
 /**
  * \brief   Set a particular OPT field in the PaRAM set associated with the
@@ -1809,7 +1520,6 @@ EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,
                     EDMA3_DRV_OptField optField,
                     unsigned int newOptFieldVal);
 
-
 /**
  * \brief   Get a particular OPT field in the PaRAM set associated with the
  *          logical channel 'lCh'.
@@ -1834,7 +1544,6 @@ EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,
                     EDMA3_DRV_OptField optField,
                     unsigned int *optFieldVal);
 
-
 /**
  * \brief  DMA source parameters setup
  *
@@ -1867,8 +1576,6 @@ EDMA3_DRV_Result EDMA3_DRV_setSrcParams ( EDMA3_DRV_Handle hEdma,
                     EDMA3_DRV_AddrMode addrMode,
                     EDMA3_DRV_FifoWidth fifoWidth);
 
-
-
 /**
  * \brief  DMA Destination parameters setup
  *
@@ -1901,8 +1608,6 @@ EDMA3_DRV_Result EDMA3_DRV_setDestParams ( EDMA3_DRV_Handle hEdma,
                     EDMA3_DRV_AddrMode addrMode,
                     EDMA3_DRV_FifoWidth fifoWidth );
 
-
-
 /**
  * \brief   DMA source index setup
  *
@@ -1940,8 +1645,6 @@ EDMA3_DRV_Result EDMA3_DRV_setSrcIndex ( EDMA3_DRV_Handle hEdma,
                     int srcBIdx,
                     int srcCIdx );
 
-
-
 /**
  * \brief   DMA destination index setup
  *
@@ -1979,7 +1682,6 @@ EDMA3_DRV_Result  EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma,
                     int destBIdx,
                     int destCIdx);
 
-
 /**
  * \brief       DMA transfer parameters setup
  *
@@ -2049,7 +1751,12 @@ EDMA3_DRV_Result EDMA3_DRV_setTransferParams (
                         unsigned int bCntReload,
                         EDMA3_DRV_SyncType syncType);
 
+/**
+@}
+*/
 
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
 
 /**
  * \brief   Chain the two specified channels.
@@ -2084,7 +1791,6 @@ EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
                                     unsigned int lCh2,
                                     const EDMA3_DRV_ChainOptions *chainOptions);
 
-
 /**
  * \brief   Unchain the two channels.
  *
@@ -2100,6 +1806,12 @@ EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
 EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma,
                         unsigned int lCh);
 
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
 
 /**
  * \brief EDMA Trigger Mode Selection
@@ -2137,6 +1849,12 @@ typedef enum
         EDMA3_DRV_TRIG_MODE_NONE = 3
 } EDMA3_DRV_TrigMode;
 
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_BASIC
+ @{ */
 
 /**
  * \brief       Start EDMA transfer on the specified channel.
@@ -2146,8 +1864,8 @@ typedef enum
  * Manual or QDMA.
  *
  * In event triggered, a peripheral or an externally generated event triggers
- * the transfer. This API clears the Event and Event Miss Register and then
- * enables the DMA channel by writing to the EESR.
+ * the transfer. This API clears the Secondary Event Register and Event Miss
+ * Register and then enables the DMA channel by writing to the EESR.
  *
  * In manual triggered mode, CPU manually triggers a transfer by writing a 1
  * in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to
@@ -2173,7 +1891,6 @@ EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
                         unsigned int lCh,
                         EDMA3_DRV_TrigMode trigMode);
 
-
 /**
  * \brief Disable DMA transfer on the specified channel
  *
@@ -2189,8 +1906,8 @@ EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
  * API clears the QDMA Event Enable Register, for the specific QDMA channel.
  *
  * To disable a channel which was previously triggered in event mode, this API
- * clears the Event Enable Register, Event Register, Secondary Event Register
- * and Event Miss Register, if set, for the specific DMA channel.
+ * clears the Event Enable Register. It also clears Event Register, Secondary
+ * Event Register and Event Miss Register, if set, for the specific DMA channel.
  *
  * \param   hEdma       [IN]    Handle to the EDMA Driver Instance
  * \param   lCh         [IN]    Channel on which transfer has to be stopped
@@ -2225,23 +1942,17 @@ EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
  * \note    This function is re-entrant for unique lCh values. It is non-
  *          re-entrant for same lCh value.
  */
-EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
+EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (
+                                               EDMA3_DRV_Handle hEdma,
                         unsigned int lCh,
                         EDMA3_DRV_TrigMode trigMode);
 
-
-/* @} Edma3DrvTransferSetupType */
-
-
-
 /**
- * \defgroup Edma3DrvTransferSetupOpt EDMA3 Driver Optional Setup for EDMA
- * Transfer.
- *
- * The Optional EDMA transfer related Interface of the EDMA3 Driver
- *
- * @{
- */
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
 
 /**
  * \brief PaRAM Set Entry type
@@ -2293,8 +2004,6 @@ typedef enum
 
 } EDMA3_DRV_PaRAMEntry;
 
-
-
 /**
  * \brief PaRAM Set Field type
  *
@@ -2373,7 +2082,12 @@ typedef enum
 
 } EDMA3_DRV_PaRAMField;
 
+/**
+@}
+*/
 
+/** @addtogroup EDMA3_LLD_DRV_DATASTRUCT
+ @{ */
 
 /**
  * \brief EDMA3 PaRAM Set
@@ -2441,8 +2155,6 @@ typedef struct  {
 
 } EDMA3_DRV_ParamentryRegs;
 
-
-
 /**
  * \brief EDMA3 Parameter RAM Set in User Configurable format
  *
@@ -2622,7 +2334,12 @@ typedef struct
     unsigned int evtQPri[EDMA3_MAX_EVT_QUE];
 }EDMA3_DRV_EvtQuePriority;
 
+/**
+@}
+*/
 
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
 
 /**
  * \brief  Assign a Trigger Word to the specified QDMA channel
@@ -2647,7 +2364,6 @@ EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma,
                     unsigned int lCh,
                     EDMA3_RM_QdmaTrigWord trigWord);
 
-
 /**
  * \brief   Copy the user specified PaRAM Set onto the PaRAM Set
  *          associated with the logical channel (DMA/QDMA/Link).
@@ -2673,7 +2389,6 @@ EDMA3_DRV_Result EDMA3_DRV_setPaRAM ( EDMA3_DRV_Handle hEdma,
                         unsigned int lCh,
                         const EDMA3_DRV_PaRAMRegs *newPaRAM);
 
-
 /**
  * \brief   Retrieve existing PaRAM set associated with specified logical
  *          channel (DMA/QDMA/Link).
@@ -2691,8 +2406,6 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma,
                     unsigned int lCh,
                     EDMA3_DRV_PaRAMRegs *currPaRAM);
 
-
-
 /**
  * \brief   Set a particular PaRAM set entry of the specified PaRAM set
  *
@@ -2720,7 +2433,6 @@ EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma,
                     EDMA3_DRV_PaRAMEntry paRAMEntry,
                     unsigned int newPaRAMEntryVal);
 
-
 /**
  * \brief   Get a particular PaRAM set entry of the specified PaRAM set
  *
@@ -2741,7 +2453,6 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma,
                     EDMA3_DRV_PaRAMEntry paRAMEntry,
                     unsigned int *paRAMEntryVal);
 
-
 /**
  * \brief   Set a particular PaRAM set field of the specified PaRAM set
  *
@@ -2770,7 +2481,6 @@ EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma,
                     EDMA3_DRV_PaRAMField paRAMField,
                     unsigned int newPaRAMFieldVal);
 
-
 /**
  * \brief   Get a particular PaRAM set field of the specified PaRAM set
  *
@@ -2791,7 +2501,6 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma,
                     EDMA3_DRV_PaRAMField paRAMField,
                     unsigned int *currPaRAMFieldVal);
 
-
 /**
  * \brief   Sets EDMA TC priority
  *
@@ -2811,7 +2520,6 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma,
 EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma,
                     const EDMA3_DRV_EvtQuePriority *evtQPriObj);
 
-
 /**
  * \brief   Associate Channel to Event Queue
  *
@@ -2834,7 +2542,6 @@ EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle hEdma,
                     unsigned int channelId,
                     EDMA3_RM_EventQueue eventQ);
 
-
 /**
  * \brief   Get the Event Queue mapped to the specified DMA/QDMA channel.
  *
@@ -2852,8 +2559,6 @@ EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma,
                     unsigned int channelId,
                     unsigned int *mappedEvtQ);
 
-
-
 /**
  * \brief   Set the Channel Controller (CC) Register value
  *
@@ -2876,7 +2581,6 @@ EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,
                     unsigned int regOffset,
                     unsigned int newRegValue);
 
-
 /**
  * \brief   Get the Channel Controller (CC) Register value
  *
@@ -2892,8 +2596,6 @@ EDMA3_DRV_Result EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma,
                     unsigned int regOffset,
                     unsigned int *regValue);
 
-
-
 /**
  * \brief   Wait for a transfer completion interrupt to occur and clear it.
  *
@@ -2915,9 +2617,6 @@ EDMA3_DRV_Result EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma,
 EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
                     unsigned int tccNo);
 
-
-
-
 /**
  * \brief   Returns the status of a previously initiated transfer.
  *
@@ -2943,8 +2642,6 @@ EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma,
                     unsigned int tccNo,
                     unsigned short *tccStatus);
 
-
-
 /**
  * \brief   Get the PaRAM Set Physical Address associated with a logical channel
  *
@@ -2972,6 +2669,12 @@ EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr(EDMA3_DRV_Handle hEdma,
                     unsigned int lCh,
                     unsigned int *paramPhyAddr);
 
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
 
 /**\enum    EDMA3_DRV_IoctlCmd
  * \brief   EDMA3 Driver IOCTL commands
@@ -3010,7 +2713,6 @@ typedef enum
      * during allocation.
      * If the value read is '0', it means that PaRAM Sets are NOT getting cleared
      * during allocation.
-     *
      * For e.g.,
      * unsigned short isParamClearingDone;
      * cmdArg = &paramClearingRequired;
@@ -3021,6 +2723,12 @@ typedef enum
     EDMA3_DRV_IOCTL_MAX_IOCTL
 } EDMA3_DRV_IoctlCmd;
 
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
 
 /**
  *  \brief EDMA3 Driver IOCTL
@@ -3045,7 +2753,6 @@ EDMA3_DRV_Result EDMA3_DRV_Ioctl(
                       void                  *param
                      );
 
-
 /**
  * \brief      Return the previously opened EDMA3 Driver Instance handle
  *
@@ -3087,16 +2794,17 @@ EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(unsigned int phyCtrllerInstId,
                                                                EDMA3_RM_RegionId regionId,
                                                                EDMA3_DRV_Result *errorCode);
 
-
 /**
  * \brief   Registers a transfer completion handler for a specific DMA/QDMA
  *                     channel
  *
  * This function registers a non-NULL callback function for a specific DMA or QDMA
  * channel and enables the completion interrupt for the TCC associated with
- * the underlying channel in the IER/IERH register. If user enables the transfer
- * completion interrupts (intermediate or final) in the associated PaRAM Set,
- * the registered callback function will be called by the EDMA3 driver.
+ * the underlying channel in the IER/IERH register. It also sets the DRAE/DRAEH
+ * register for the TCC associated with the specified DMA/QDMA channel. If user
+ * enables the transfer completion interrupts (intermediate or final) in the OPT
+ * field of the associated PaRAM Set, the registered callback function will be
+ * called by the EDMA3 Resource Manager.
  *
  * If a call-back function is already registered for the channel, the API fails
  * with the error code EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED.
@@ -3122,16 +2830,19 @@ EDMA3_DRV_Result EDMA3_DRV_registerTccCb(EDMA3_DRV_Handle hEdma,
  * \brief   Un-register the previously registered callback function against a
  *          DMA/QDMA channel.
  *
- * This function unregisters the previously registered callback function against
- * a DMA/QDMA channel by removing any stored callback function. Moreover, it
- * clears the interrupt enable register (IER/IERH) by writing to the IECR/
- * IECRH register, for the TCC associated with that particular channel.
+ * This function un-registers the previously registered callback function for
+ * the DMA/QDMA channel by removing any stored callback function. Moreover, it
+ * clears the:
+ *             Interrupt Enable Register (IER/IERH) by writing to the IECR/IECRH
+ *                     register, for the TCC associated with that particular channel,
+ *             DRA/DRAEH register for the TCC associated with the specified DMA/QDMA
+ *                     channel
  *
  * \param  hEdma               [IN]    Handle to the EDMA Driver Instance.
  * \param  channelId           [IN]    DMA/QDMA channel for which the callback
  *                                                                             function needs to be un-registered.
  *
- * \return  EDMA3_RM_SOK or EDMA3_RM Error Code.
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
  *
  * \note    This function is re-entrant for unique channelId. It is
  *                     non-re-entrant for same channelId.
@@ -3139,12 +2850,18 @@ EDMA3_DRV_Result EDMA3_DRV_registerTccCb(EDMA3_DRV_Handle hEdma,
 EDMA3_DRV_Result EDMA3_DRV_unregisterTccCb(EDMA3_DRV_Handle hEdma,
                     const unsigned int channelId);
 
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
 
 /**\enum    EDMA3_DRV_Tc_Err
  * \brief   TC Error Enablers
  *
  * Use this enum to enable/disable the specific EDMA3 Transfer Controller
- * Interrupt.
+ * Interrupts.
  */
 typedef enum
 {
@@ -3189,52 +2906,85 @@ typedef enum
        EDMA3_DRV_TC_ERR_EN
 } EDMA3_DRV_Tc_Err;
 
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
 
 /**
- * \brief   Un-register the previously registered callback function against a
- *          DMA/QDMA channel.
+ * \brief   Enable/disable specific EDMA3 Transfer Controller Interrupts
  *
- * This function unregisters the previously registered callback function against
- * a DMA/QDMA channel by removing any stored callback function. Moreover, it
- * clears the interrupt enable register (IER/IERH) by writing to the IECR/
- * IECRH register, for the TCC associated with that particular channel.
+ * This function allows one to enable/disable specific EDMA3 Transfer Controller
+ * Interrupts. Since these interrupts don't get enabled by default, this API can
+ * be used to achieve the same.
  *
- * \param  hEdma               [IN]    Handle to the EDMA Driver Instance.
- * \param  channelId           [IN]    DMA/QDMA channel for which the callback
- *                                                                             function needs to be un-registered.
+ * \param phyCtrllerInstId  [IN]    EDMA3 Controller Instance Id
+ *                                 (Hardware instance id, starting from 0).
+ * \param tcId                         [IN]    Transfer Controller Id. It starts from 0
+ *                                                                     for each EDMA3 hardware and can go upto
+ *                                                                     (TCs available on EDMA3 Hardware - 1).
+ * \param tcErr                        [IN]    TC Error Interrupts which need to be
+ *                                                                     enabled/disabled.
  *
- * \return  EDMA3_RM_SOK or EDMA3_RM Error Code.
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error code
  *
- * \note    This function is re-entrant for unique channelId. It is
- *                     non-re-entrant for same channelId.
+ * \note    This function is re-entrant for unique combination of EDMA3 hw and
+ *                     TC. It is non-re-entrant for same combination.
  */
 EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt(unsigned int phyCtrllerInstId,
                                        unsigned int tcId,
                                        EDMA3_DRV_Tc_Err tcErr);
 
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_DEFINE
+ @{ */
 
+/**
+ * \brief Channel status defines
+ * These defines suggest the current state of the DMA / QDMA channel. They
+ * are used while returning the channel status from EDMA3_DRV_getChannelStatus().
+ */
+/** Channel is clean; no pending event, completion interrupt and event miss interrupt */
 #define EDMA3_DRV_CHANNEL_CLEAN                                0x0000u
+/** Pending event is detected on the DMA channel */
 #define EDMA3_DRV_CHANNEL_EVENT_PENDING                0x0001u
+/** Transfer completion interrupt is detected on the DMA/QDMA channel */
 #define EDMA3_DRV_CHANNEL_XFER_COMPLETE                0x0002u
+/** Event miss error interrupt is detected on the DMA/QDMA channel */
 #define EDMA3_DRV_CHANNEL_ERR                          0x0004u
 
 /**
- * \brief   Un-register the previously registered callback function against a
- *          DMA/QDMA channel.
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
+
+/**
+ * \brief   Get the current status of the DMA/QDMA channel
  *
- * This function unregisters the previously registered callback function against
- * a DMA/QDMA channel by removing any stored callback function. Moreover, it
- * clears the interrupt enable register (IER/IERH) by writing to the IECR/
- * IECRH register, for the TCC associated with that particular channel.
+ * This function returns the current status of the specific DMA/QDMA channel.
+ * For a DMA channel, it checks whether an event is pending in ER, transfer
+ * completion interrupt is pending in IPR and event miss error interrupt is
+ * pending in EMR or not. For a QDMA channel, it checks whether a transfer
+ * completion interrupt is pending in IPR and event miss error interrupt is
+ * pending in QEMR or not.
  *
  * \param  hEdma               [IN]    Handle to the EDMA Driver Instance.
- * \param  channelId           [IN]    DMA/QDMA channel for which the callback
- *                                                                             function needs to be un-registered.
+ * \param  lCh                         [IN]    DMA/QDMA channel for which the current
+ *                                                                             status is required.
+ * \param  lchStatus           [IN/OUT]Status of the channel. Defines mentioned
+ *                                                                             above are used (and may be combined) to
+ *                                                                             return the actual status.
  *
- * \return  EDMA3_RM_SOK or EDMA3_RM Error Code.
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
  *
- * \note    This function is re-entrant for unique channelId. It is
- *                     non-re-entrant for same channelId.
+ * \note    This function is re-entrant.
  */
 EDMA3_DRV_Result EDMA3_DRV_getChannelStatus(EDMA3_DRV_Handle hEdma,
                         unsigned int lCh, unsigned int *lchStatus);
@@ -3244,31 +2994,29 @@ EDMA3_DRV_Result EDMA3_DRV_getChannelStatus(EDMA3_DRV_Handle hEdma,
  * \brief  Associates a link channel and a TCC
  *
  * This API is used to map a TCC to a LINK channel. It should be used with LINK
- * channels ONLY else it will fail.
+ * channels ONLY else it will fail. It will copy the TCC code in the OPT field
+ * of the param set associated with the link channel.
  *
  * \param   hEdma           [IN]    Handle to the EDMA Driver Instance.
  * \param   linkCh          [IN]    Link Channel to which a particular TCC
  *                                  needs to be mapped.
- * \param   tcc             [IN]    TCC which needs to be mapped
+ * \param   tcc             [IN]    TCC which needs to be mapped.
  *
  * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
  *
  * \note    This function is re-entrant for unique linkCh values. It is
  *          non-re-entrant for same linkCh values.
  */
-EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh ( EDMA3_DRV_Handle hEdma,
+EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh (EDMA3_DRV_Handle hEdma,
                                                 unsigned int linkCh,
                                                 unsigned int tcc);
 
-
-/* @} Edma3DrvTransferSetupOpt */
-
-
-/* @} Edma3DrvMain */
+/**
+@}
+*/
 
 #ifdef __cplusplus
 }
 #endif /* extern "C" */
 
 #endif         /* _EDMA3_DRV_H_ */
-
old mode 100644 (file)
new mode 100755 (executable)
index b6b233f..9834288
-/*
- * bios6_edma3_drv_sample.h
- *
- * Header file for the sample application for the EDMA3 Driver.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#ifndef _BIOS6_EDMA3_DRV_SAMPLE_H_
-#define _BIOS6_EDMA3_DRV_SAMPLE_H_
-
-#include <stdio.h>
-#include <ti/sysbios/ipc/Semaphore.h>
-
-/* Include EDMA3 Driver */
-#include <ti/sdo/edma3/drv/edma3_drv.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Cache line size on the underlying SoC. It needs to be modified
- * for different cache line sizes, if the Cache is Enabled.
- */
-#define EDMA3_CACHE_LINE_SIZE_IN_BYTES      (128u)
-
-/* Error returned in case of buffers are not aligned on the cache boundary */
-#define EDMA3_NON_ALIGNED_BUFFERS_ERROR     (-1)
-
-/* Error returned in case of data mismatch */
-#define EDMA3_DATA_MISMATCH_ERROR           (-2)
-
-/**
- * \brief   EDMA3 Initialization
- *
- * This function initializes the EDMA3 Driver and registers the
- * interrupt handlers.
- *
-  * \return  EDMA3_DRV_SOK if success, else error code
- */
-EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode);
-
-/**
- * \brief   EDMA3 De-initialization
- *
- * This function removes the EDMA3 RM Instance and un-registers the
- * interrupt handlers. It also deletes the RM  Object.
- *
-  * \return  EDMA3_DRV_SOK if success, else error code
- */
-EDMA3_DRV_Result edma3deinit (unsigned int edma3Id, EDMA3_DRV_Handle hEdma);
-
-
-/**
- *  \brief   EDMA3 Cache Invalidate
- *
- *  This function invalidates the D cache.
- *
- *  \param  mem_start_ptr [IN]      Starting address of memory.
- *                                  Please note that this should be
- *                                  aligned according to the cache line size.
- *  \param  num_bytes [IN]          length of buffer
- *  \return  EDMA3_DRV_SOK if success, else error code in case of error
- *          or non-alignment of buffers.
- *
- * Note: This function is required if the buffer is in DDR.
- * For other cases, where buffer is NOT in DDR, user
- * may or may not require the below implementation and
- * should modify it according to her need.
- */
-EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr,
-                           unsigned int num_bytes);
-
-
-
-/**
- * \brief   EDMA3 Cache Flush
- *
- *  This function flushes (cleans) the Cache
- *
- *  \param  mem_start_ptr [IN]      Starting address of memory.
- *                                  Please note that this should be
- *                                  aligned according to the cache line size.
- *  \param  num_bytes [IN]          length of buffer
- *  \return  EDMA3_DRV_SOK if success, else error code in case of error
- *          or non-alignment of buffers.
- *
- * Note: This function is required if the buffer is in DDR.
- * For other cases, where buffer is NOT in DDR, user
- * may or may not require the below implementation and
- * should modify it according to her need.
- */
-EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr,
-                      unsigned int num_bytes);
-
-
-
-/**
-  * Counting Semaphore related functions (OS dependent) should be
-  * called/implemented by the application. A handle to the semaphore
-  * is required while opening the driver/resource manager instance.
-  */
-
-/**
- * \brief   EDMA3 OS Semaphore Create
- *
- *      This function creates a counting semaphore with specified
- *      attributes and initial value. It should be used to create a semaphore
- *      with initial value as '1'. The semaphore is then passed by the user
- *      to the EDMA3 driver/RM for proper sharing of resources.
- * \param   initVal [IN] is initial value for semaphore
- * \param   semParams [IN] is the semaphore attributes.
- * \param   hSem [OUT] is location to receive the handle to just created
- *      semaphore.
- * \return  EDMA3_DRV_SOK if successful, else a suitable error code.
- */
-EDMA3_DRV_Result edma3OsSemCreate(int initVal,
-                                                       const Semaphore_Params *semParams,
-                                                       EDMA3_OS_Sem_Handle *hSem);
-
-
-
-/**
- * \brief   EDMA3 OS Semaphore Delete
- *
- *      This function deletes or removes the specified semaphore
- *      from the system. Associated dynamically allocated memory
- *      if any is also freed up.
- * \param   hSem [IN] handle to the semaphore to be deleted
- * \return  EDMA3_DRV_SOK if successful else a suitable error code
- */
-EDMA3_DRV_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem);
-
-#ifdef __cplusplus
-}
-#endif /* extern "C" */
-
-#endif  /* _BIOS6_EDMA3_DRV_SAMPLE_H_ */
-
+/*\r
+ * bios6_edma3_drv_sample.h\r
+ *\r
+ * Header file for the sample application for the EDMA3 Driver.\r
+ *\r
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ *  Redistribution and use in source and binary forms, with or without\r
+ *  modification, are permitted provided that the following conditions\r
+ *  are met:\r
+ *\r
+ *    Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ *    Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the\r
+ *    distribution.\r
+ *\r
+ *    Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#ifndef _BIOS6_EDMA3_DRV_SAMPLE_H_\r
+#define _BIOS6_EDMA3_DRV_SAMPLE_H_\r
+\r
+#include <stdio.h>\r
+#include <ti/sysbios/ipc/Semaphore.h>\r
+\r
+/* Include EDMA3 Driver */\r
+#include <ti/sdo/edma3/drv/edma3_drv.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**\r
+ * Cache line size on the underlying SoC. It needs to be modified\r
+ * for different cache line sizes, if the Cache is Enabled.\r
+ */\r
+#define EDMA3_CACHE_LINE_SIZE_IN_BYTES      (128u)\r
+\r
+/* Error returned in case of buffers are not aligned on the cache boundary */\r
+#define EDMA3_NON_ALIGNED_BUFFERS_ERROR     (-1)\r
+\r
+/* Error returned in case of data mismatch */\r
+#define EDMA3_DATA_MISMATCH_ERROR           (-2)\r
+\r
+/**\r
+ * \brief   EDMA3 Initialization\r
+ *\r
+ * This function initializes the EDMA3 Driver for the given EDMA3 controller\r
+ * and opens a EDMA3 driver instance. It internally calls EDMA3_DRV_create() and\r
+ * EDMA3_DRV_open(), in that order.\r
+ *\r
+ * It also registers interrupt handlers for various EDMA3 interrupts like \r
+ * transfer completion or error interrupts.\r
+ *\r
+ *  \param  edma3Id    [IN]            EDMA3 Controller Instance Id (Hardware\r
+ *                                                                     instance id, starting from 0)\r
+ *  \param  errorCode  [IN/OUT]        Error code while opening DRV instance\r
+ *  \return EDMA3_DRV_Handle: If successfully opened, the API will return the\r
+ *                            associated driver's instance handle.\r
+ */\r
+EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode);\r
+\r
+/**\r
+ * \brief   EDMA3 De-initialization\r
+ *\r
+ * This function de-initializes the EDMA3 Driver for the given EDMA3 controller\r
+ * and closes the previously opened EDMA3 driver instance. It internally calls \r
+ * EDMA3_DRV_close and EDMA3_DRV_delete(), in that order.\r
+ *\r
+ * It also un-registers the previously registered interrupt handlers for various \r
+ * EDMA3 interrupts.\r
+ *\r
+ *  \param  edma3Id    [IN]            EDMA3 Controller Instance Id (Hardware\r
+ *                                                                     instance id, starting from 0)\r
+ *  \param  hEdma              [IN]            EDMA3 Driver handle, returned while using\r
+ *                                                                     edma3init().\r
+ *  \return  EDMA3_DRV_SOK if success, else error code\r
+ */\r
+EDMA3_DRV_Result edma3deinit (unsigned int edma3Id, EDMA3_DRV_Handle hEdma);\r
+\r
+\r
+/**\r
+ *  \brief   EDMA3 Cache Invalidate\r
+ *\r
+ *  This function invalidates the D cache.\r
+ *\r
+ *  \param  mem_start_ptr [IN]      Starting address of memory.\r
+ *                                  Please note that this should be\r
+ *                                  aligned according to the cache line size.\r
+ *  \param  num_bytes [IN]          length of buffer\r
+ *  \return  EDMA3_DRV_SOK if success, else error code in case of error\r
+ *          or non-alignment of buffers.\r
+ *\r
+ * Note: This function is required if the buffer is in DDR.\r
+ * For other cases, where buffer is NOT in DDR, user\r
+ * may or may not require the below implementation and\r
+ * should modify it according to her need.\r
+ */\r
+EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr,\r
+                           unsigned int num_bytes);\r
+\r
+\r
+\r
+/**\r
+ * \brief   EDMA3 Cache Flush\r
+ *\r
+ *  This function flushes (cleans) the Cache\r
+ *\r
+ *  \param  mem_start_ptr [IN]      Starting address of memory.\r
+ *                                  Please note that this should be\r
+ *                                  aligned according to the cache line size.\r
+ *  \param  num_bytes [IN]          length of buffer\r
+ *  \return  EDMA3_DRV_SOK if success, else error code in case of error\r
+ *          or non-alignment of buffers.\r
+ *\r
+ * Note: This function is required if the buffer is in DDR.\r
+ * For other cases, where buffer is NOT in DDR, user\r
+ * may or may not require the below implementation and\r
+ * should modify it according to her need.\r
+ */\r
+EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr,\r
+                      unsigned int num_bytes);\r
+\r
+\r
+\r
+/**\r
+  * Counting Semaphore related functions (OS dependent) should be\r
+  * called/implemented by the application. A handle to the semaphore\r
+  * is required while opening the driver/resource manager instance.\r
+  */\r
+\r
+/**\r
+ * \brief   EDMA3 OS Semaphore Create\r
+ *\r
+ *      This function creates a counting semaphore with specified\r
+ *      attributes and initial value. It should be used to create a semaphore\r
+ *      with initial value as '1'. The semaphore is then passed by the user\r
+ *      to the EDMA3 driver/RM for proper sharing of resources.\r
+ * \param   initVal [IN] is initial value for semaphore\r
+ * \param   semParams [IN] is the semaphore attributes.\r
+ * \param   hSem [OUT] is location to receive the handle to just created\r
+ *      semaphore.\r
+ * \return  EDMA3_DRV_SOK if successful, else a suitable error code.\r
+ */\r
+EDMA3_DRV_Result edma3OsSemCreate(int initVal,\r
+                                                       const Semaphore_Params *semParams,\r
+                                                       EDMA3_OS_Sem_Handle *hSem);\r
+\r
+\r
+\r
+/**\r
+ * \brief   EDMA3 OS Semaphore Delete\r
+ *\r
+ *      This function deletes or removes the specified semaphore\r
+ *      from the system. Associated dynamically allocated memory\r
+ *      if any is also freed up.\r
+ * \param   hSem [IN] handle to the semaphore to be deleted\r
+ * \return  EDMA3_DRV_SOK if successful else a suitable error code\r
+ */\r
+EDMA3_DRV_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* extern "C" */\r
+\r
+#endif  /* _BIOS6_EDMA3_DRV_SAMPLE_H_ */\r
+\r
old mode 100644 (file)
new mode 100755 (executable)
index 067e80b..deb0ad6
@@ -1,7 +1,7 @@
 /*
  * sample_da830_cfg.c
  *
- * SoC specific EDMA3 hardware related information like number of transfer
+ * Platform specific EDMA3 hardware related information like number of transfer
  * controllers, various interrupt ids etc. It is used while interrupts
  * enabling / disabling. It needs to be ported for different SoCs.
  *
@@ -51,7 +51,7 @@ const unsigned int numDsps = NUM_DSPS;
 /* Determine the processor id by reading DNUM register. */
 unsigned short determineProcId()
        {
-#if 0  
+#if 0
        volatile unsigned int *addr;
        unsigned int core_no;
 
@@ -67,7 +67,7 @@ unsigned short determineProcId()
 unsigned short isGblConfigRequired(unsigned int dspNum)
        {
        (void) dspNum;
-       
+
        return 1;
        }
 
@@ -425,7 +425,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                                /* 31     0     63    32 */
                                {0x00000000u, 0x00000000u},
                        },
-                   
+
                /* Resources owned/reserved by region 1 */
                    {
                        /* ownPaRAMSets */
@@ -760,7 +760,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX
                        },
            },
        };
-                   
+
 
 
 /* End of File */
old mode 100644 (file)
new mode 100755 (executable)
index 731c093..51fee14
@@ -1,5 +1,7 @@
 /*
- * bios6_int_register_tci_6498.c
+ * sample_da830_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
  *
  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  *
old mode 100644 (file)
new mode 100755 (executable)
index a7a00ab..3e487c4
-/*
- * sample_tci6498_cfg.c
- *
- * SoC specific EDMA3 hardware related information like number of transfer
- * controllers, various interrupt ids etc. It is used while interrupts
- * enabling / disabling. It needs to be ported for different SoCs.
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <ti/sdo/edma3/drv/edma3_drv.h>
-
-/* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES                    3u
-const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
-
-/* Number of DSPs present in the system */
-#define NUM_DSPS                                       4u
-//const unsigned int numDsps = NUM_DSPS;
-
-#define CGEM_REG_START                  (0x01800000)
-
-/* Determine the processor id by reading DNUM register. */
-unsigned short determineProcId()
-       {
-       volatile unsigned int *addr;
-       unsigned int core_no;
-
-    /* Identify the core number */
-    addr = (unsigned int *)(CGEM_REG_START+0x40000);
-    core_no = ((*addr) & 0x000F0000)>>16;
-
-       return core_no;
-       }
-
-/** Whether global configuration required for EDMA3 or not.
- * This configuration should be done only once for the EDMA3 hardware by
- * any one of the masters (i.e. DSPs).
- * It can be changed depending on the use-case.
- */
-unsigned int gblCfgReqdArray [NUM_DSPS] = {
-                                                                       0,      /* DSP#0 is Master, will do the global init */
-                                                                       1,      /* DSP#1 is Slave, will not do the global init  */
-                                                                       1,      /* DSP#2 is Slave, will not do the global init  */
-                                                                       1,      /* DSP#3 is Slave, will not do the global init  */
-                                                                       };
-
-unsigned short isGblConfigRequired(unsigned int dspNum)
-       {
-       return gblCfgReqdArray[dspNum];
-       }
-
-/* Semaphore handles */
-EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
-
-
-/* Variable which will be used internally for referring number of Event Queues. */
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
-
-/* Variable which will be used internally for referring number of TCs. */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
-
-/**
- * Variable which will be used internally for referring transfer completion
- * interrupt. Completion interrupts for all the shadow regions and all the
- * EDMA3 controllers are captured since it is a multi-DSP platform.
- */
-unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
-                                                                                                       {
-                                                                                                       38u, 39u, 40u, 41u,
-                                                                                                       42u, 43u, 44u, 45u,
-                                                                                                       },
-                                                                                                       {
-                                                                                                       8u, 9u, 10u, 11u,
-                                                                                                       12u, 13u, 14u, 15u,
-                                                                                                       },
-                                                                                                       {
-                                                                                                       24u, 25u, 26u, 27u,
-                                                                                                       28u, 29u, 30u, 31u,
-                                                                                                       },
-                                                                                               };
-
-
-/**
- * Variable which will be used internally for referring channel controller's
- * error interrupt.
- */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
-
-/**
- * Variable which will be used internally for referring transfer controllers'
- * error interrupts.
- */
-unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] =    {
-                                                                                                       {
-                                                                                                       34u, 35u, 0u, 0u,
-                                                                                                       0u, 0u, 0u, 0u,
-                                                                                                       },
-                                                                                                       {
-                                                                                                       2u, 3u, 4u, 5u,
-                                                                                                       0u, 0u, 0u, 0u,
-                                                                                                       },
-                                                                                                       {
-                                                                                                       18u, 19u, 20u, 21u,
-                                                                                                       0u, 0u, 0u, 0u,
-                                                                                                       },
-                                                                                               };
-
-/* Driver Object Initialization Configuration */
-EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
-       {
-               {
-               /* EDMA3 INSTANCE# 0 */
-               /** Total number of DMA Channels supported by the EDMA3 Controller */
-               16u,
-               /** Total number of QDMA Channels supported by the EDMA3 Controller */
-               8u,
-               /** Total number of TCCs supported by the EDMA3 Controller */
-               16u,
-               /** Total number of PaRAM Sets supported by the EDMA3 Controller */
-               128u,
-               /** Total number of Event Queues in the EDMA3 Controller */
-               2u,
-               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
-               2u,
-               /** Number of Regions on this EDMA3 controller */
-               8u,
-
-               /**
-                * \brief Channel mapping existence
-                * A value of 0 (No channel mapping) implies that there is fixed association
-                * for a channel number to a parameter entry number or, in other words,
-                * PaRAM entry n corresponds to channel n.
-                */
-               1u,
-
-               /** Existence of memory protection feature */
-               1u,
-
-               /** Global Register Region of CC Registers */
-               (void *)0x02700000u,
-               /** Transfer Controller (TC) Registers */
-               {
-               (void *)0x02760000u,
-               (void *)0x02768000u,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL
-               },
-               /** Interrupt no. for Transfer Completion */
-               38u,
-               /** Interrupt no. for CC Error */
-               32u,
-               /** Interrupt no. for TCs Error */
-               {
-               34u,
-               35u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u,
-               },
-
-               /**
-                * \brief EDMA3 TC priority setting
-                *
-                * User can program the priority of the Event Queues
-                * at a system-wide level.  This means that the user can set the
-                * priority of an IO initiated by either of the TCs (Transfer Controllers)
-                * relative to IO initiated by the other bus masters on the
-                * device (ARM, DSP, USB, etc)
-                */
-               {
-               0u,
-               1u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-               /**
-                * \brief To Configure the Threshold level of number of events
-                * that can be queued up in the Event queues. EDMA3CC error register
-                * (CCERR) will indicate whether or not at any instant of time the
-                * number of events queued up in any of the event queues exceeds
-                * or equals the threshold/watermark value that is set
-                * in the queue watermark threshold register (QWMTHRA).
-                */
-               {
-               16u,
-               16u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-
-               /**
-                * \brief To Configure the Default Burst Size (DBS) of TCs.
-                * An optimally-sized command is defined by the transfer controller
-                * default burst size (DBS). Different TCs can have different
-                * DBS values. It is defined in Bytes.
-                */
-               {
-               16u,
-               16u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-
-               /**
-                * \brief Mapping from each DMA channel to a Parameter RAM set,
-                * if it exists, otherwise of no use.
-                */
-               {
-               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-               /* DMA channels 16-63 DOES NOT exist */
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
-               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
-               },
-
-                /**
-                 * \brief Mapping from each DMA channel to a TCC. This specific
-                 * TCC code will be returned when the transfer is completed
-                 * on the mapped channel.
-                 */
-               {
-               0u, 1u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-               4u, 5u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-               8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-               12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-               /* DMA channels 16-63 DOES NOT exist */
-               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
-               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
-               },
-
-               /**
-                * \brief Mapping of DMA channels to Hardware Events from
-                * various peripherals, which use EDMA for data transfer.
-                * All channels need not be mapped, some can be free also.
-                */
-               {
-               0x00003333u,
-               0x00000000u
-               }
-               },
-
-               {
-               /* EDMA3 INSTANCE# 1 */
-               /** Total number of DMA Channels supported by the EDMA3 Controller */
-               64u,
-               /** Total number of QDMA Channels supported by the EDMA3 Controller */
-               8u,
-               /** Total number of TCCs supported by the EDMA3 Controller */
-               64u,
-               /** Total number of PaRAM Sets supported by the EDMA3 Controller */
-               512u,
-               /** Total number of Event Queues in the EDMA3 Controller */
-               4u,
-               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
-               4u,
-               /** Number of Regions on this EDMA3 controller */
-               8u,
-
-               /**
-                * \brief Channel mapping existence
-                * A value of 0 (No channel mapping) implies that there is fixed association
-                * for a channel number to a parameter entry number or, in other words,
-                * PaRAM entry n corresponds to channel n.
-                */
-               1u,
-
-               /** Existence of memory protection feature */
-               1u,
-
-               /** Global Register Region of CC Registers */
-               (void *)0x02720000u,
-               /** Transfer Controller (TC) Registers */
-               {
-               (void *)0x02770000u,
-               (void *)0x02778000u,
-               (void *)0x02780000u,
-               (void *)0x02788000u,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL
-               },
-               /** Interrupt no. for Transfer Completion */
-               8u,
-               /** Interrupt no. for CC Error */
-               0u,
-               /** Interrupt no. for TCs Error */
-               {
-               2u,
-               3u,
-               4u,
-               5u,
-               0u,
-               0u,
-               0u,
-               0u,
-               },
-
-               /**
-                * \brief EDMA3 TC priority setting
-                *
-                * User can program the priority of the Event Queues
-                * at a system-wide level.  This means that the user can set the
-                * priority of an IO initiated by either of the TCs (Transfer Controllers)
-                * relative to IO initiated by the other bus masters on the
-                * device (ARM, DSP, USB, etc)
-                */
-               {
-               0u,
-               1u,
-               2u,
-               3u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-               /**
-                * \brief To Configure the Threshold level of number of events
-                * that can be queued up in the Event queues. EDMA3CC error register
-                * (CCERR) will indicate whether or not at any instant of time the
-                * number of events queued up in any of the event queues exceeds
-                * or equals the threshold/watermark value that is set
-                * in the queue watermark threshold register (QWMTHRA).
-                */
-               {
-               16u,
-               16u,
-               16u,
-               16u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-
-               /**
-                * \brief To Configure the Default Burst Size (DBS) of TCs.
-                * An optimally-sized command is defined by the transfer controller
-                * default burst size (DBS). Different TCs can have different
-                * DBS values. It is defined in Bytes.
-                */
-               {
-               8u,
-               8u,
-               8u,
-               8u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-
-               /**
-                * \brief Mapping from each DMA channel to a Parameter RAM set,
-                * if it exists, otherwise of no use.
-                */
-               {
-               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-               32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
-               40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-               48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-               56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
-               },
-
-                /**
-                 * \brief Mapping from each DMA channel to a TCC. This specific
-                 * TCC code will be returned when the transfer is completed
-                 * on the mapped channel.
-                 */
-               {
-               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-               8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-               24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-               32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
-               40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-               48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-               56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
-               },
-
-               /**
-                * \brief Mapping of DMA channels to Hardware Events from
-                * various peripherals, which use EDMA for data transfer.
-                * All channels need not be mapped, some can be free also.
-                */
-               {
-               0x3FFF3FFFu,
-               0x3FFF3FFFu
-               }
-               },
-
-               {
-               /* EDMA3 INSTANCE# 2 */
-               /** Total number of DMA Channels supported by the EDMA3 Controller */
-               64u,
-               /** Total number of QDMA Channels supported by the EDMA3 Controller */
-               8u,
-               /** Total number of TCCs supported by the EDMA3 Controller */
-               64u,
-               /** Total number of PaRAM Sets supported by the EDMA3 Controller */
-               512u,
-               /** Total number of Event Queues in the EDMA3 Controller */
-               4u,
-               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
-               4u,
-               /** Number of Regions on this EDMA3 controller */
-               8u,
-
-               /**
-                * \brief Channel mapping existence
-                * A value of 0 (No channel mapping) implies that there is fixed association
-                * for a channel number to a parameter entry number or, in other words,
-                * PaRAM entry n corresponds to channel n.
-                */
-               1u,
-
-               /** Existence of memory protection feature */
-               1u,
-
-               /** Global Register Region of CC Registers */
-               (void *)0x02740000u,
-               /** Transfer Controller (TC) Registers */
-               {
-               (void *)0x02790000u,
-               (void *)0x02798000u,
-               (void *)0x027A0000u,
-               (void *)0x027A8000u,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL
-               },
-               /** Interrupt no. for Transfer Completion */
-               24u,
-               /** Interrupt no. for CC Error */
-               16u,
-               /** Interrupt no. for TCs Error */
-               {
-               18u,
-               19u,
-               20u,
-               21u,
-               0u,
-               0u,
-               0u,
-               0u,
-               },
-
-               /**
-                * \brief EDMA3 TC priority setting
-                *
-                * User can program the priority of the Event Queues
-                * at a system-wide level.  This means that the user can set the
-                * priority of an IO initiated by either of the TCs (Transfer Controllers)
-                * relative to IO initiated by the other bus masters on the
-                * device (ARM, DSP, USB, etc)
-                */
-               {
-               0u,
-               1u,
-               2u,
-               3u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-               /**
-                * \brief To Configure the Threshold level of number of events
-                * that can be queued up in the Event queues. EDMA3CC error register
-                * (CCERR) will indicate whether or not at any instant of time the
-                * number of events queued up in any of the event queues exceeds
-                * or equals the threshold/watermark value that is set
-                * in the queue watermark threshold register (QWMTHRA).
-                */
-               {
-               16u,
-               16u,
-               16u,
-               16u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-
-               /**
-                * \brief To Configure the Default Burst Size (DBS) of TCs.
-                * An optimally-sized command is defined by the transfer controller
-                * default burst size (DBS). Different TCs can have different
-                * DBS values. It is defined in Bytes.
-                */
-               {
-               8u,
-               8u,
-               8u,
-               8u,
-               0u,
-               0u,
-               0u,
-               0u
-               },
-
-               /**
-                * \brief Mapping from each DMA channel to a Parameter RAM set,
-                * if it exists, otherwise of no use.
-                */
-               {
-               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-               32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
-               40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-               48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-               56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
-               },
-
-                /**
-                 * \brief Mapping from each DMA channel to a TCC. This specific
-                 * TCC code will be returned when the transfer is completed
-                 * on the mapped channel.
-                 */
-               {
-               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-               8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-               24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-               32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
-               40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-               48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-               56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
-               },
-
-               /**
-                * \brief Mapping of DMA channels to Hardware Events from
-                * various peripherals, which use EDMA for data transfer.
-                * All channels need not be mapped, some can be free also.
-                */
-               {
-               0x3FFF3FFFu,
-               0x3FFF3FFFu
-               }
-               },
-       };
-
-EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
-       {
-               /* EDMA3 INSTANCE# 0 */
-               {
-                       /* Resources owned/reserved by region 0 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x0000000Fu, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000003u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x0000000Fu, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* resvdDmaChannels */
-                               /* 31           0 */
-                               {0x00000003u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31           0 */
-                               {0x00000003u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 1 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x000000F0u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x0000000Cu},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x000000F0u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000030u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000030u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 2 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x0000000Fu,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000F00u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000030u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000F00u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000300u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000300u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 3 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFFFF0u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x0000F000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x000000C0u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x0000F000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00003000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00003000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 4 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 5 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 6 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 7 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-           },
-
-               /* EDMA3 INSTANCE# 1 */
-           {
-               /* Resources owned/reserved by region 0 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x0000FFFFu, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000003u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x0000FFFFu, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00003FFFu, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00003FFFu, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 1 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0xFFFF0000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x0000000Cu},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0xFFFF0000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x3FFF0000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x3FFF0000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 2 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x0000FFFFu},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000030u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x0000FFFFu},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00003FFFu},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00003FFFu},
-                       },
-
-               /* Resources owned/reserved by region 3 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0xFFFF0000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x000000C0u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0xFFFF0000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x3FFF0000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x3FFF0000u},
-                       },
-
-               /* Resources owned/reserved by region 4 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 5 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 6 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 7 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-           },
-
-               /* EDMA3 INSTANCE# 2 */
-               {
-               /* Resources owned/reserved by region 0 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x0000FFFFu, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000003u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x0000FFFFu, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00003FFFu, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00003FFFu, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 1 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0xFFFF0000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x0000000Cu},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0xFFFF0000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x3FFF0000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x3FFF0000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 2 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x0000FFFFu},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000030u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x0000FFFFu},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00003FFFu},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00003FFFu},
-                       },
-
-               /* Resources owned/reserved by region 3 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0xFFFF0000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x000000C0u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0xFFFF0000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x3FFF0000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x3FFF0000u},
-                       },
-
-               /* Resources owned/reserved by region 4 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 5 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 6 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 7 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-           },
-       };
-
-/* End of File */
+/*\r
+ * sample_tci6498_cfg.c\r
+ *\r
+ * Platform specific EDMA3 hardware related information like number of transfer\r
+ * controllers, various interrupt ids etc. It is used while interrupts\r
+ * enabling / disabling. It needs to be ported for different SoCs.\r
+ *\r
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ *  Redistribution and use in source and binary forms, with or without\r
+ *  modification, are permitted provided that the following conditions\r
+ *  are met:\r
+ *\r
+ *    Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ *    Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the\r
+ *    distribution.\r
+ *\r
+ *    Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#include <ti/sdo/edma3/drv/edma3_drv.h>\r
+\r
+/* Number of EDMA3 controllers present in the system */\r
+#define NUM_EDMA3_INSTANCES                    3u\r
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
+\r
+/* Number of DSPs present in the system */\r
+#define NUM_DSPS                                       4u\r
+//const unsigned int numDsps = NUM_DSPS;\r
+\r
+#define CGEM_REG_START                  (0x01800000)\r
+\r
+/* Determine the processor id by reading DNUM register. */\r
+unsigned short determineProcId()\r
+       {\r
+       volatile unsigned int *addr;\r
+       unsigned int core_no;\r
+\r
+    /* Identify the core number */\r
+    addr = (unsigned int *)(CGEM_REG_START+0x40000);\r
+    core_no = ((*addr) & 0x000F0000)>>16;\r
+\r
+       return core_no;\r
+       }\r
+\r
+/** Whether global configuration required for EDMA3 or not.\r
+ * This configuration should be done only once for the EDMA3 hardware by\r
+ * any one of the masters (i.e. DSPs).\r
+ * It can be changed depending on the use-case.\r
+ */\r
+unsigned int gblCfgReqdArray [NUM_DSPS] = {\r
+                                                                       0,      /* DSP#0 is Master, will do the global init */\r
+                                                                       1,      /* DSP#1 is Slave, will not do the global init  */\r
+                                                                       1,      /* DSP#2 is Slave, will not do the global init  */\r
+                                                                       1,      /* DSP#3 is Slave, will not do the global init  */\r
+                                                                       };\r
+\r
+unsigned short isGblConfigRequired(unsigned int dspNum)\r
+       {\r
+       return gblCfgReqdArray[dspNum];\r
+       }\r
+\r
+/* Semaphore handles */\r
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};\r
+\r
+\r
+/* Variable which will be used internally for referring number of Event Queues. */\r
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};\r
+\r
+/* Variable which will be used internally for referring number of TCs. */\r
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};\r
+\r
+/**\r
+ * Variable which will be used internally for referring transfer completion\r
+ * interrupt. Completion interrupts for all the shadow regions and all the\r
+ * EDMA3 controllers are captured since it is a multi-DSP platform.\r
+ */\r
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {\r
+                                                                                                       {\r
+                                                                                                       38u, 39u, 40u, 41u,\r
+                                                                                                       42u, 43u, 44u, 45u,\r
+                                                                                                       },\r
+                                                                                                       {\r
+                                                                                                       8u, 9u, 10u, 11u,\r
+                                                                                                       12u, 13u, 14u, 15u,\r
+                                                                                                       },\r
+                                                                                                       {\r
+                                                                                                       24u, 25u, 26u, 27u,\r
+                                                                                                       28u, 29u, 30u, 31u,\r
+                                                                                                       },\r
+                                                                                               };\r
+\r
+/**\r
+ * Variable which will be used internally for referring channel controller's\r
+ * error interrupt.\r
+ */\r
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};\r
+\r
+/**\r
+ * Variable which will be used internally for referring transfer controllers'\r
+ * error interrupts.\r
+ */\r
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] =    {\r
+                                                                                                       {\r
+                                                                                                       34u, 35u, 0u, 0u,\r
+                                                                                                       0u, 0u, 0u, 0u,\r
+                                                                                                       },\r
+                                                                                                       {\r
+                                                                                                       2u, 3u, 4u, 5u,\r
+                                                                                                       0u, 0u, 0u, 0u,\r
+                                                                                                       },\r
+                                                                                                       {\r
+                                                                                                       18u, 19u, 20u, 21u,\r
+                                                                                                       0u, 0u, 0u, 0u,\r
+                                                                                                       },\r
+                                                                                               };\r
+\r
+/* Driver Object Initialization Configuration */\r
+EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
+       {\r
+               {\r
+               /* EDMA3 INSTANCE# 0 */\r
+               /** Total number of DMA Channels supported by the EDMA3 Controller */\r
+               16u,\r
+               /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
+               8u,\r
+               /** Total number of TCCs supported by the EDMA3 Controller */\r
+               16u,\r
+               /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
+               128u,\r
+               /** Total number of Event Queues in the EDMA3 Controller */\r
+               2u,\r
+               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
+               2u,\r
+               /** Number of Regions on this EDMA3 controller */\r
+               8u,\r
+\r
+               /**\r
+                * \brief Channel mapping existence\r
+                * A value of 0 (No channel mapping) implies that there is fixed association\r
+                * for a channel number to a parameter entry number or, in other words,\r
+                * PaRAM entry n corresponds to channel n.\r
+                */\r
+               1u,\r
+\r
+               /** Existence of memory protection feature */\r
+               1u,\r
+\r
+               /** Global Register Region of CC Registers */\r
+               (void *)0x02700000u,\r
+               /** Transfer Controller (TC) Registers */\r
+               {\r
+               (void *)0x02760000u,\r
+               (void *)0x02768000u,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL\r
+               },\r
+               /** Interrupt no. for Transfer Completion */\r
+               38u,\r
+               /** Interrupt no. for CC Error */\r
+               32u,\r
+               /** Interrupt no. for TCs Error */\r
+               {\r
+               34u,\r
+               35u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               },\r
+\r
+               /**\r
+                * \brief EDMA3 TC priority setting\r
+                *\r
+                * User can program the priority of the Event Queues\r
+                * at a system-wide level.  This means that the user can set the\r
+                * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
+                * relative to IO initiated by the other bus masters on the\r
+                * device (ARM, DSP, USB, etc)\r
+                */\r
+               {\r
+               0u,\r
+               1u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+               /**\r
+                * \brief To Configure the Threshold level of number of events\r
+                * that can be queued up in the Event queues. EDMA3CC error register\r
+                * (CCERR) will indicate whether or not at any instant of time the\r
+                * number of events queued up in any of the event queues exceeds\r
+                * or equals the threshold/watermark value that is set\r
+                * in the queue watermark threshold register (QWMTHRA).\r
+                */\r
+               {\r
+               16u,\r
+               16u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+\r
+               /**\r
+                * \brief To Configure the Default Burst Size (DBS) of TCs.\r
+                * An optimally-sized command is defined by the transfer controller\r
+                * default burst size (DBS). Different TCs can have different\r
+                * DBS values. It is defined in Bytes.\r
+                */\r
+               {\r
+               16u,\r
+               16u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+\r
+               /**\r
+                * \brief Mapping from each DMA channel to a Parameter RAM set,\r
+                * if it exists, otherwise of no use.\r
+                */\r
+               {\r
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
+               /* DMA channels 16-63 DOES NOT exist */\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS\r
+               },\r
+\r
+                /**\r
+                 * \brief Mapping from each DMA channel to a TCC. This specific\r
+                 * TCC code will be returned when the transfer is completed\r
+                 * on the mapped channel.\r
+                 */\r
+               {\r
+               0u, 1u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               4u, 5u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               /* DMA channels 16-63 DOES NOT exist */\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC\r
+               },\r
+\r
+               /**\r
+                * \brief Mapping of DMA channels to Hardware Events from\r
+                * various peripherals, which use EDMA for data transfer.\r
+                * All channels need not be mapped, some can be free also.\r
+                */\r
+               {\r
+               0x00003333u,\r
+               0x00000000u\r
+               }\r
+               },\r
+\r
+               {\r
+               /* EDMA3 INSTANCE# 1 */\r
+               /** Total number of DMA Channels supported by the EDMA3 Controller */\r
+               64u,\r
+               /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
+               8u,\r
+               /** Total number of TCCs supported by the EDMA3 Controller */\r
+               64u,\r
+               /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
+               512u,\r
+               /** Total number of Event Queues in the EDMA3 Controller */\r
+               4u,\r
+               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
+               4u,\r
+               /** Number of Regions on this EDMA3 controller */\r
+               8u,\r
+\r
+               /**\r
+                * \brief Channel mapping existence\r
+                * A value of 0 (No channel mapping) implies that there is fixed association\r
+                * for a channel number to a parameter entry number or, in other words,\r
+                * PaRAM entry n corresponds to channel n.\r
+                */\r
+               1u,\r
+\r
+               /** Existence of memory protection feature */\r
+               1u,\r
+\r
+               /** Global Register Region of CC Registers */\r
+               (void *)0x02720000u,\r
+               /** Transfer Controller (TC) Registers */\r
+               {\r
+               (void *)0x02770000u,\r
+               (void *)0x02778000u,\r
+               (void *)0x02780000u,\r
+               (void *)0x02788000u,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL\r
+               },\r
+               /** Interrupt no. for Transfer Completion */\r
+               8u,\r
+               /** Interrupt no. for CC Error */\r
+               0u,\r
+               /** Interrupt no. for TCs Error */\r
+               {\r
+               2u,\r
+               3u,\r
+               4u,\r
+               5u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               },\r
+\r
+               /**\r
+                * \brief EDMA3 TC priority setting\r
+                *\r
+                * User can program the priority of the Event Queues\r
+                * at a system-wide level.  This means that the user can set the\r
+                * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
+                * relative to IO initiated by the other bus masters on the\r
+                * device (ARM, DSP, USB, etc)\r
+                */\r
+               {\r
+               0u,\r
+               1u,\r
+               2u,\r
+               3u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+               /**\r
+                * \brief To Configure the Threshold level of number of events\r
+                * that can be queued up in the Event queues. EDMA3CC error register\r
+                * (CCERR) will indicate whether or not at any instant of time the\r
+                * number of events queued up in any of the event queues exceeds\r
+                * or equals the threshold/watermark value that is set\r
+                * in the queue watermark threshold register (QWMTHRA).\r
+                */\r
+               {\r
+               16u,\r
+               16u,\r
+               16u,\r
+               16u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+\r
+               /**\r
+                * \brief To Configure the Default Burst Size (DBS) of TCs.\r
+                * An optimally-sized command is defined by the transfer controller\r
+                * default burst size (DBS). Different TCs can have different\r
+                * DBS values. It is defined in Bytes.\r
+                */\r
+               {\r
+               8u,\r
+               8u,\r
+               8u,\r
+               8u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+\r
+               /**\r
+                * \brief Mapping from each DMA channel to a Parameter RAM set,\r
+                * if it exists, otherwise of no use.\r
+                */\r
+               {\r
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
+               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
+               32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
+               40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
+               48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
+               56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
+               },\r
+\r
+                /**\r
+                 * \brief Mapping from each DMA channel to a TCC. This specific\r
+                 * TCC code will be returned when the transfer is completed\r
+                 * on the mapped channel.\r
+                 */\r
+               {\r
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
+               8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
+               24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
+               40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
+               56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP\r
+               },\r
+\r
+               /**\r
+                * \brief Mapping of DMA channels to Hardware Events from\r
+                * various peripherals, which use EDMA for data transfer.\r
+                * All channels need not be mapped, some can be free also.\r
+                */\r
+               {\r
+               0x3FFF3FFFu,\r
+               0x3FFF3FFFu\r
+               }\r
+               },\r
+\r
+               {\r
+               /* EDMA3 INSTANCE# 2 */\r
+               /** Total number of DMA Channels supported by the EDMA3 Controller */\r
+               64u,\r
+               /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
+               8u,\r
+               /** Total number of TCCs supported by the EDMA3 Controller */\r
+               64u,\r
+               /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
+               512u,\r
+               /** Total number of Event Queues in the EDMA3 Controller */\r
+               4u,\r
+               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
+               4u,\r
+               /** Number of Regions on this EDMA3 controller */\r
+               8u,\r
+\r
+               /**\r
+                * \brief Channel mapping existence\r
+                * A value of 0 (No channel mapping) implies that there is fixed association\r
+                * for a channel number to a parameter entry number or, in other words,\r
+                * PaRAM entry n corresponds to channel n.\r
+                */\r
+               1u,\r
+\r
+               /** Existence of memory protection feature */\r
+               1u,\r
+\r
+               /** Global Register Region of CC Registers */\r
+               (void *)0x02740000u,\r
+               /** Transfer Controller (TC) Registers */\r
+               {\r
+               (void *)0x02790000u,\r
+               (void *)0x02798000u,\r
+               (void *)0x027A0000u,\r
+               (void *)0x027A8000u,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL\r
+               },\r
+               /** Interrupt no. for Transfer Completion */\r
+               24u,\r
+               /** Interrupt no. for CC Error */\r
+               16u,\r
+               /** Interrupt no. for TCs Error */\r
+               {\r
+               18u,\r
+               19u,\r
+               20u,\r
+               21u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               },\r
+\r
+               /**\r
+                * \brief EDMA3 TC priority setting\r
+                *\r
+                * User can program the priority of the Event Queues\r
+                * at a system-wide level.  This means that the user can set the\r
+                * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
+                * relative to IO initiated by the other bus masters on the\r
+                * device (ARM, DSP, USB, etc)\r
+                */\r
+               {\r
+               0u,\r
+               1u,\r
+               2u,\r
+               3u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+               /**\r
+                * \brief To Configure the Threshold level of number of events\r
+                * that can be queued up in the Event queues. EDMA3CC error register\r
+                * (CCERR) will indicate whether or not at any instant of time the\r
+                * number of events queued up in any of the event queues exceeds\r
+                * or equals the threshold/watermark value that is set\r
+                * in the queue watermark threshold register (QWMTHRA).\r
+                */\r
+               {\r
+               16u,\r
+               16u,\r
+               16u,\r
+               16u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+\r
+               /**\r
+                * \brief To Configure the Default Burst Size (DBS) of TCs.\r
+                * An optimally-sized command is defined by the transfer controller\r
+                * default burst size (DBS). Different TCs can have different\r
+                * DBS values. It is defined in Bytes.\r
+                */\r
+               {\r
+               8u,\r
+               8u,\r
+               8u,\r
+               8u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+\r
+               /**\r
+                * \brief Mapping from each DMA channel to a Parameter RAM set,\r
+                * if it exists, otherwise of no use.\r
+                */\r
+               {\r
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
+               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
+               32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
+               40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
+               48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
+               56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
+               },\r
+\r
+                /**\r
+                 * \brief Mapping from each DMA channel to a TCC. This specific\r
+                 * TCC code will be returned when the transfer is completed\r
+                 * on the mapped channel.\r
+                 */\r
+               {\r
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
+               8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
+               24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
+               40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
+               56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP\r
+               },\r
+\r
+               /**\r
+                * \brief Mapping of DMA channels to Hardware Events from\r
+                * various peripherals, which use EDMA for data transfer.\r
+                * All channels need not be mapped, some can be free also.\r
+                */\r
+               {\r
+               0x3FFF3FFFu,\r
+               0x3FFF3FFFu\r
+               }\r
+               },\r
+       };\r
+\r
+EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+       {\r
+               /* EDMA3 INSTANCE# 0 */\r
+               {\r
+                       /* Resources owned/reserved by region 0 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x0000000Fu, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000003u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x0000000Fu, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31           0 */\r
+                               {0x00000003u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31           0 */\r
+                               {0x00000003u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 1 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x000000F0u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x0000000Cu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x000000F0u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000030u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000030u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 2 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x0000000Fu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000F00u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000030u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000F00u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000300u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000300u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 3 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFFFF0u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x0000F000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000C0u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x0000F000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00003000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00003000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 4 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 5 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 6 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 7 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+           },\r
+\r
+               /* EDMA3 INSTANCE# 1 */\r
+           {\r
+               /* Resources owned/reserved by region 0 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x0000FFFFu, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000003u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x0000FFFFu, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00003FFFu, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00003FFFu, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 1 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFF0000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x0000000Cu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFF0000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x3FFF0000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x3FFF0000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 2 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x0000FFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000030u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x0000FFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00003FFFu},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00003FFFu},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 3 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0xFFFF0000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000C0u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0xFFFF0000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x3FFF0000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x3FFF0000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 4 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 5 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 6 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 7 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+           },\r
+\r
+               /* EDMA3 INSTANCE# 2 */\r
+               {\r
+               /* Resources owned/reserved by region 0 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x0000FFFFu, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x0000FFFFu, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000003u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x0000FFFFu, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00003FFFu, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00003FFFu, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 1 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFF0000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x0000000Cu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFF0000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x3FFF0000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x3FFF0000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 2 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x0000FFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000030u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x0000FFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00003FFFu},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00003FFFu},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 3 */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,\r