Merged from master, added a15 support for k2l, c66ak2e
authorIvan Pang <i-pang@ti.com>
Mon, 6 Jan 2014 23:18:23 +0000 (18:18 -0500)
committerIvan Pang <i-pang@ti.com>
Mon, 6 Jan 2014 23:18:23 +0000 (18:18 -0500)
141 files changed:
.gitignore [new file with mode: 0644]
COPYING.txt [new file with mode: 0644]
debian/README.Debian [new file with mode: 0644]
debian/README.source [new file with mode: 0644]
debian/changelog [new file with mode: 0644]
debian/compat [new file with mode: 0644]
debian/control [new file with mode: 0644]
debian/copyright [new file with mode: 0644]
debian/docs [new file with mode: 0644]
debian/edma3.debhelper.log [new file with mode: 0644]
debian/edma3.substvars [new file with mode: 0644]
debian/edma3/DEBIAN/control [new file with mode: 0644]
debian/edma3/DEBIAN/md5sums [new file with mode: 0644]
debian/edma3/usr/include/edma3_common.h [new file with mode: 0644]
debian/edma3/usr/include/edma3_drv.h [new file with mode: 0644]
debian/edma3/usr/include/edma3_rm.h [new file with mode: 0644]
debian/edma3/usr/share/doc/edma3/README.Debian [new file with mode: 0644]
debian/edma3/usr/share/doc/edma3/changelog.Debian.gz [new file with mode: 0644]
debian/edma3/usr/share/doc/edma3/copyright [new file with mode: 0644]
debian/files [new file with mode: 0644]
debian/install [new file with mode: 0644]
debian/rules [new file with mode: 0755]
examples/edma3_driver/evmC66AK2E/makefile [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/maketemp_configuro_cmd_c6xdsp.bat [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/rtsc_config/.ccsproject [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/rtsc_config/.cdtbuild [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/rtsc_config/.cdtproject [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/rtsc_config/.cproject [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/rtsc_config/.project [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/rtsc_config/.settings/org.eclipse.cdt.codan.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/rtsc_config/.settings/org.eclipse.cdt.debug.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/rtsc_config/.settings/org.eclipse.core.resources.prefs [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/rtsc_config/edma3_drv_bios6_c66ak2e_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/sample_app/.ccsproject [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/sample_app/.cdtbuild [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/sample_app/.cdtproject [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/sample_app/.cproject [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/sample_app/.project [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/sample_app/.settings/org.eclipse.cdt.codan.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/sample_app/.settings/org.eclipse.cdt.debug.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/sample_app/.settings/org.eclipse.core.resources.prefs [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/sample_app/linker.cmd [new file with mode: 0644]
examples/edma3_driver/evmC66AK2E/sample_app/macros.ini_initial [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/makefile [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/maketemp_configuro_cmd_c6xdsp.bat [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/rtsc_config/.ccsproject [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/rtsc_config/.cdtbuild [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/rtsc_config/.cdtproject [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/rtsc_config/.cproject [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/rtsc_config/.project [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/rtsc_config/.settings/org.eclipse.cdt.codan.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/rtsc_config/.settings/org.eclipse.cdt.debug.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/rtsc_config/.settings/org.eclipse.core.resources.prefs [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/rtsc_config/edma3_drv_bios6_c66ak2ebe_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/sample_app/.ccsproject [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/sample_app/.cdtbuild [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/sample_app/.cdtproject [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/sample_app/.cproject [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/sample_app/.project [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/sample_app/.settings/org.eclipse.cdt.codan.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/sample_app/.settings/org.eclipse.cdt.debug.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/sample_app/.settings/org.eclipse.core.resources.prefs [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/sample_app/linker.cmd [new file with mode: 0644]
examples/edma3_driver/evmC66AK2EBE/sample_app/macros.ini_initial [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/makefile [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/maketemp_configuro_cmd_c6xdsp.bat [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/rtsc_config/.ccsproject [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/rtsc_config/.cdtbuild [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/rtsc_config/.cdtproject [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/rtsc_config/.cproject [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/rtsc_config/.project [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/rtsc_config/.settings/org.eclipse.cdt.codan.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/rtsc_config/.settings/org.eclipse.cdt.debug.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/rtsc_config/.settings/org.eclipse.core.resources.prefs [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/rtsc_config/edma3_drv_bios6_tci6630k2l_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/sample_app/.ccsproject [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/sample_app/.cdtbuild [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/sample_app/.cdtproject [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/sample_app/.cproject [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/sample_app/.project [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/sample_app/.settings/org.eclipse.cdt.codan.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/sample_app/.settings/org.eclipse.cdt.debug.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/sample_app/.settings/org.eclipse.core.resources.prefs [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/sample_app/linker.cmd [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2L/sample_app/macros.ini_initial [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/makefile [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/maketemp_configuro_cmd_c6xdsp.bat [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/rtsc_config/.ccsproject [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/rtsc_config/.cdtbuild [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/rtsc_config/.cdtproject [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/rtsc_config/.cproject [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/rtsc_config/.project [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/rtsc_config/.settings/org.eclipse.cdt.codan.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/rtsc_config/.settings/org.eclipse.cdt.debug.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/rtsc_config/.settings/org.eclipse.core.resources.prefs [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/rtsc_config/edma3_drv_bios6_tci6630k2lbe_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/sample_app/.ccsproject [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/sample_app/.cdtbuild [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/sample_app/.cdtproject [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/sample_app/.cproject [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/sample_app/.project [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/sample_app/.settings/org.eclipse.cdt.codan.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/sample_app/.settings/org.eclipse.cdt.debug.core.prefs [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/sample_app/.settings/org.eclipse.core.resources.prefs [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/sample_app/linker.cmd [new file with mode: 0644]
examples/edma3_driver/evmTCI6630K2LBE/sample_app/macros.ini_initial [new file with mode: 0644]
examples/edma3_driver/evmTCI6636K2H/maketemp_configuro_cmd_c6xdsp.bat [new file with mode: 0644]
examples/edma3_user_space_driver/evmC66AK2E/evmC66AK2ESample.c [new file with mode: 0644]
examples/edma3_user_space_driver/evmC66AK2E/makefile [new file with mode: 0755]
examples/edma3_user_space_driver/evmTCI6630K2L/evmTCI6630K2LSample.c [new file with mode: 0644]
examples/edma3_user_space_driver/evmTCI6630K2L/makefile [new file with mode: 0755]
examples/edma3_user_space_driver/evmTCI6636K2H/evmTCI6636K2HSample.c [new file with mode: 0644]
examples/edma3_user_space_driver/evmTCI6636K2H/makefile [new file with mode: 0755]
examples/edma3_user_space_driver/evmTCI6638K2K/evmTCI6638K2KSample.c [new file with mode: 0644]
examples/edma3_user_space_driver/evmTCI6638K2K/makefile [new file with mode: 0755]
examples/edma3_user_space_driver/src/main.c [new file with mode: 0755]
makerules/common.mk
makerules/env.mk
makerules/platform.mk
makerules/rules_GCC_a15.mk [new file with mode: 0755]
packages/component.mk
packages/config.bld
packages/makefile
packages/makefile_c66x
packages/ti/sdo/edma3/drv/sample/makefile
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c66ak2e_cfg.c [new file with mode: 0644]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_c66ak2e_int_reg.c [new file with mode: 0644]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6630k2l_cfg.c [new file with mode: 0644]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tci6630k2l_int_reg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/makefile
packages/ti/sdo/edma3/rm/package.bld
packages/ti/sdo/edma3/rm/package.xs
packages/ti/sdo/edma3/rm/sample/makefile
packages/ti/sdo/edma3/rm/sample/package.bld
packages/ti/sdo/edma3/rm/sample/package.xs
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c66ak2e_cfg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_c66ak2e_int_reg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6630k2l_cfg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tci6630k2l_int_reg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/src/configs/edma3_c66ak2e_cfg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/src/configs/edma3_tci6630k2l_cfg.c [new file with mode: 0644]

diff --git a/.gitignore b/.gitignore
new file mode 100644 (file)
index 0000000..b38c79f
--- /dev/null
@@ -0,0 +1,5 @@
+bin/
+obj
+*.patch
+Debug/
+
diff --git a/COPYING.txt b/COPYING.txt
new file mode 100644 (file)
index 0000000..2f7d9fb
--- /dev/null
@@ -0,0 +1,32 @@
+/*  ===========================================================================
+ *  Copyright (c) Texas Instruments Incorporated 2010-2013
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
\ No newline at end of file
diff --git a/debian/README.Debian b/debian/README.Debian
new file mode 100644 (file)
index 0000000..3533f40
--- /dev/null
@@ -0,0 +1,4 @@
+EDMA3 for Debian
+--------------
+
+ -- Hao Zhang <hzhang@ti.com>  Tue, 20 Aug 2013 13:55:04 -0400
diff --git a/debian/README.source b/debian/README.source
new file mode 100644 (file)
index 0000000..601a297
--- /dev/null
@@ -0,0 +1,9 @@
+EDMA3 LLD for Debian
+--------------
+
+<this file describes information about the source package, see Debian policy
+manual section 4.14. You WILL either need to modify or delete this file>
+
+
+
+
diff --git a/debian/changelog b/debian/changelog
new file mode 100644 (file)
index 0000000..d4e3154
--- /dev/null
@@ -0,0 +1,6 @@
+edma3 (01.00.00.00-0ubuntu1~ppa2) precise; urgency=low
+
+  * Initial Release 
+
+ -- Hao Zhang <hzhang@ti.com>  Fri, 13 Sep 2013 09:44:44 -0400
+
diff --git a/debian/compat b/debian/compat
new file mode 100644 (file)
index 0000000..45a4fb7
--- /dev/null
@@ -0,0 +1 @@
+8
diff --git a/debian/control b/debian/control
new file mode 100644 (file)
index 0000000..4c598c3
--- /dev/null
@@ -0,0 +1,13 @@
+Source: edma3
+Section: admin
+Priority: extra
+Maintainer: Hao Zhang <hzhang@ti.com>
+Build-Depends: debhelper (>= 8.0.0)
+Standards-Version: 3.9.4
+Vcs-Git: git://gitorious.design.ti.com/+edma3-lld-developers/edma3/edma3_lld_development.git
+Vcs-Browser: https://gitorious.design.ti.com/+edma3-lld-developers/edma3/edma3_lld_development
+
+Package: edma3
+Architecture: any
+Depends: ${shlibs:Depends}, ${misc:Depends}
+Description: EDMA3 Low Level Driver for user space. This LLD provides API for using EDMA. 
diff --git a/debian/copyright b/debian/copyright
new file mode 100644 (file)
index 0000000..4882ede
--- /dev/null
@@ -0,0 +1,39 @@
+Format: http://www.debian.org/doc/packaging-manuals/copyright-format/1.0/
+Upstream-Name: edma3 
+Source: <https://gitorious.design.ti.com/+edma3-lld-developers/edma3/edma3_lld_development>
+
+Files: *
+(C) Copyright 2013, Texas Instruments, Inc.
+
+Redistribution and use in source and binary forms, with or without 
+modification, are permitted provided that the following conditions 
+are met:
+
+  Redistributions of source code must retain the above copyright 
+  notice, this list of conditions and the following disclaimer.
+
+  Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the 
+  documentation and/or other materials provided with the   
+  distribution.
+
+  Neither the name of Texas Instruments Incorporated nor the names of
+  its contributors may be used to endorse or promote products derived
+  from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+# Please also look if there are files or directories which have a
+# different copyright/license attached and list them here.
+# Please avoid to pick license terms that are more restrictive than the
+# packaged work, as it may make Debian's contributions unacceptable upstream.
diff --git a/debian/docs b/debian/docs
new file mode 100644 (file)
index 0000000..852f9d2
--- /dev/null
@@ -0,0 +1 @@
+#LICENSE.txt
diff --git a/debian/edma3.debhelper.log b/debian/edma3.debhelper.log
new file mode 100644 (file)
index 0000000..ce685bc
--- /dev/null
@@ -0,0 +1,48 @@
+dh_auto_configure
+dh_auto_build
+dh_auto_test
+dh_prep
+dh_installdirs
+dh_auto_install
+dh_install
+dh_installdocs
+dh_installchangelogs
+dh_installexamples
+dh_installman
+dh_installcatalogs
+dh_installcron
+dh_installdebconf
+dh_installemacsen
+dh_installifupdown
+dh_installinfo
+dh_pysupport
+dh_installinit
+dh_installmenu
+dh_installmime
+dh_installmodules
+dh_installlogcheck
+dh_installlogrotate
+dh_installpam
+dh_installppp
+dh_installudev
+dh_installwm
+dh_installxfonts
+dh_installgsettings
+dh_bugfiles
+dh_ucf
+dh_lintian
+dh_gconf
+dh_icons
+dh_perl
+dh_usrlocal
+dh_link
+dh_compress
+dh_fixperms
+dh_strip
+dh_makeshlibs
+dh_shlibdeps
+dh_installdeb
+dh_gencontrol
+dh_md5sums
+dh_builddeb
+dh_builddeb
diff --git a/debian/edma3.substvars b/debian/edma3.substvars
new file mode 100644 (file)
index 0000000..abd3ebe
--- /dev/null
@@ -0,0 +1 @@
+misc:Depends=
diff --git a/debian/edma3/DEBIAN/control b/debian/edma3/DEBIAN/control
new file mode 100644 (file)
index 0000000..e1889fb
--- /dev/null
@@ -0,0 +1,8 @@
+Package: edma3
+Version: 01.00.00.00-0ubuntu1~ppa2
+Architecture: armhf
+Maintainer: Hao Zhang <hzhang@ti.com>
+Installed-Size: 245
+Section: admin
+Priority: extra
+Description: EDMA3 Low Level Driver for user space. This LLD provides API for using EDMA.
diff --git a/debian/edma3/DEBIAN/md5sums b/debian/edma3/DEBIAN/md5sums
new file mode 100644 (file)
index 0000000..1a1baf3
--- /dev/null
@@ -0,0 +1,6 @@
+5704243f434fe80ed5ecce2038837f1d  usr/include/edma3_common.h
+12bb604e7bd21e8c7360a3103e77ecb0  usr/include/edma3_drv.h
+3fc12265e88bf197527ec8e92d87b8ac  usr/include/edma3_rm.h
+18f4333e907c7d1f1f0361cbc13b849b  usr/share/doc/edma3/README.Debian
+c39876e2586a6d957633ce8a3a523d61  usr/share/doc/edma3/changelog.Debian.gz
+5746d112311b92b6de788ee0ece6fc3a  usr/share/doc/edma3/copyright
diff --git a/debian/edma3/usr/include/edma3_common.h b/debian/edma3/usr/include/edma3_common.h
new file mode 100644 (file)
index 0000000..2025465
--- /dev/null
@@ -0,0 +1,330 @@
+/*
+ * edma3_common.h
+ *
+ * EDMA3 common header providing generic defines/typedefs and debugging info.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef _EDMA3_COMMON_H_
+#define _EDMA3_COMMON_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** define to enable/disable Resource Manager debug messages*/
+#define EDMA3_RM_DEBUG
+#undef EDMA3_RM_DEBUG
+
+/** define to enable/disable EDMA3 Driver debug messages*/
+#define EDMA3_DRV_DEBUG
+#undef EDMA3_DRV_DEBUG
+
+/** Debug mechanism used for Resource Manager */
+#ifdef EDMA3_RM_DEBUG
+#include <stdio.h>
+#define EDMA3_RM_PRINTF printf
+#endif
+
+/** Debug mechanism used for EDMA Driver */
+#ifdef EDMA3_DRV_DEBUG
+#include <stdio.h>
+#define EDMA3_DRV_PRINTF printf
+#endif
+
+/** Defines for boolean variables */
+#ifndef TRUE
+  /** TRUE */
+  #define TRUE  (1u)
+  /** FALSE */
+  #define FALSE (0u)
+#endif
+
+/** Define for NULL values*/
+#ifndef NULL
+#define NULL 0u
+#endif
+
+/** EDMA3_RM Result - return value of a function  */
+typedef int32_t             EDMA3_RM_Result;
+/** EDMA3_DRV Result - return value of a function  */
+typedef int32_t             EDMA3_DRV_Result;
+
+/** EDMA3 Resource Manager Result OK */
+#define EDMA3_RM_SOK             (0u)
+/** EDMA3 Driver Result OK */
+#define EDMA3_DRV_SOK            (0u)
+
+/**
+ * EDMA3 Resource Manager Handle.
+ * It will be returned from EDMA3_RM_open() and will be used to call
+ * other Resource Manager APIs.
+ */
+typedef void    *EDMA3_RM_Handle;
+/**
+ * EDMA3 Driver Handle.
+ * It will be returned from EDMA3_DRV_open() and will be used to call
+ * other EDMA3 Driver APIs.
+ */
+typedef void    *EDMA3_DRV_Handle;
+
+/**
+ * OS specific Semaphore Handle.
+ * Used to acquire/free the semaphore, used for sharing of resources
+ * among multiple users.
+ */
+typedef void    *EDMA3_OS_Sem_Handle;
+
+/** Blocking call without timeout */
+#define EDMA3_OSSEM_NO_TIMEOUT    (-1)
+
+/**
+ * Defines used to support the maximum resources supported
+ * by the EDMA3 controller. These are used to allocate the maximum
+ * memory for different data structures of the EDMA3 Driver and Resource
+ * Manager.
+ */
+/** Maximum EDMA3 Controllers on the SoC */
+#define EDMA3_MAX_EDMA3_INSTANCES               (5u)
+/** Maximum DMA channels supported by the EDMA3 Controller */
+#define EDMA3_MAX_DMA_CH                        (64u)
+/** Maximum QDMA channels supported by the EDMA3 Controller */
+#define EDMA3_MAX_QDMA_CH                       (8u)
+/** Maximum PaRAM Sets supported by the EDMA3 Controller */
+#define EDMA3_MAX_PARAM_SETS                    (512u)
+/** Maximum Logical channels supported by the EDMA3 Package */
+#define EDMA3_MAX_LOGICAL_CH                    (EDMA3_MAX_DMA_CH + \
+                                                 EDMA3_MAX_PARAM_SETS + \
+                                                 EDMA3_MAX_QDMA_CH)
+/** Maximum TCCs (Interrupt Channels) supported by the EDMA3 Controller */
+#define EDMA3_MAX_TCC                           (64u)
+/** Maximum Event Queues supported by the EDMA3 Controller */
+#define EDMA3_MAX_EVT_QUE                       (8u)
+/** Maximum Transfer Controllers supported by the EDMA3 Controller */
+#define EDMA3_MAX_TC                            (8u)
+/** Maximum Shadow Regions supported by the EDMA3 Controller */
+#define EDMA3_MAX_REGIONS                       (8u)
+
+/**
+ * Maximum Words (4-bytes region) required for the book-keeping information
+ * specific to the maximum possible DMA channels.
+ */
+#define EDMA3_MAX_DMA_CHAN_DWRDS                (EDMA3_MAX_DMA_CH / 32u)
+
+/**
+ * Maximum Words (4-bytes region) required for the book-keeping information
+ * specific to the maximum possible QDMA channels.
+ */
+#define EDMA3_MAX_QDMA_CHAN_DWRDS               (1u)
+
+/**
+ * Maximum Words (4-bytes region) required for the book-keeping information
+ * specific to the maximum possible PaRAM Sets.
+ */
+#define EDMA3_MAX_PARAM_DWRDS                   (EDMA3_MAX_PARAM_SETS / 32u)
+
+/**
+ * Maximum Words (4-bytes region) required for the book-keeping information
+ * specific to the maximum possible TCCs.
+ */
+#define EDMA3_MAX_TCC_DWRDS                     (EDMA3_MAX_TCC / 32u)
+
+/**
+ * EDMA3 ISRs which need to be registered with the underlying OS by the user
+ * (Not all TC error ISRs need to be registered, register only for the
+ * available Transfer Controllers).
+ */
+/**  EDMA3 Completion Handler ISR Routine */
+extern void lisrEdma3ComplHandler0 (uint32_t arg);
+
+/**  EDMA3 CC Error Interrupt Handler ISR Routine */
+extern void lisrEdma3CCErrHandler0 (uint32_t arg);
+
+/**  EDMA3 TC0 Error Interrupt Handler ISR Routine */
+extern void lisrEdma3TC0ErrHandler0(uint32_t arg);
+/**  EDMA3 TC1 Error Interrupt Handler ISR Routine */
+extern void lisrEdma3TC1ErrHandler0(uint32_t arg);
+/**  EDMA3 TC2 Error Interrupt Handler ISR Routine */
+extern void lisrEdma3TC2ErrHandler0(uint32_t arg);
+/**  EDMA3 TC3 Error Interrupt Handler ISR Routine */
+extern void lisrEdma3TC3ErrHandler0(uint32_t arg);
+/**  EDMA3 TC4 Error Interrupt Handler ISR Routine */
+extern void lisrEdma3TC4ErrHandler0(uint32_t arg);
+/**  EDMA3 TC5 Error Interrupt Handler ISR Routine */
+extern void lisrEdma3TC5ErrHandler0(uint32_t arg);
+/**  EDMA3 TC6 Error Interrupt Handler ISR Routine */
+extern void lisrEdma3TC6ErrHandler0(uint32_t arg);
+/**  EDMA3 TC7 Error Interrupt Handler ISR Routine */
+extern void lisrEdma3TC7ErrHandler0(uint32_t arg);
+
+/**
+ * Defines for the level of OS protection needed when calling
+ * edma3OsProtectEntry()
+ */
+/** Protection from All Interrupts required */
+#define EDMA3_OS_PROTECT_INTERRUPT                          1
+/** Protection from scheduling required */
+#define EDMA3_OS_PROTECT_SCHEDULER                          2
+/** Protection from EDMA3 Transfer Completion Interrupt required */
+#define EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION          3
+/** Protection from EDMA3 CC Error Interrupt required */
+#define EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR                 4
+/** Protection from EDMA3 TC Error Interrupt required */
+#define EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR                 5
+
+/**
+ * Critical section entry and exit functions (OS dependent) should be
+ * implemented by the application for proper linking with the EDMA3 Driver
+ * and/or EDMA3 Resource Manager. Without the definitions being provided,
+ * the image won\92t get linked properly.
+ *
+ * It is possible that for some regions of code, user needs ultimate
+ * degree of protection where some or all external interrupts are blocked,
+ * essentially locking out the CPU exclusively for the critical
+ * section of code. On the other hand, user may wish to merely avoid
+ * thread or task switch from occuring inside said region of code,
+ * but he may wish to entertain ISRs to run if so required.
+ *
+ * Depending on the underlying OS, the number of levels of protection
+ * offered may vary. At the least, these basic levels of protection are
+ * supported --
+ * - EDMA3_OS_PROTECT_INTERRUPT - Mask interrupts globally. This has
+ *   real-time implications and must be used with descretion.
+
+ * - EDMA3_OS_PROTECT_SCHEDULER - Only turns off Kernel scheduler
+ *   completely, but still allows h/w interrupts from being serviced.
+
+ * - EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION - Mask EDMA3 Transfer
+      Completion Interrupt.
+
+ * - EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR - Mask EDMA3 CC Error Interrupt.
+
+ * - EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR - Mask EDMA3 TC Error Interrupt.
+
+ * These APIs should be mandatorily implemented ONCE by the global
+ * initialization routine or by the user itself.
+ */
+
+/**
+ *  \brief  EDMA3 OS Protect Entry
+ *
+ *      This function saves the current state of protection in 'intState'
+ *      variable passed by caller, if the protection level is
+ *      EDMA3_OS_PROTECT_INTERRUPT. It then applies the requested level of
+ *      protection.
+ *      For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and
+ *      EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored,
+ *      and the requested interrupt is disabled.
+ *      For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, '*intState' specifies the
+ *      Transfer Controller number whose interrupt needs to be disabled.
+ *
+ * \param   edma3InstanceId is EDMA3 hardware instance id.
+ * \param   level is numeric identifier of the desired degree of protection.
+ * \param   intState is memory location where current state of protection is
+ *      saved for future use while restoring it via edma3OsProtectExit() (Only
+ *      for EDMA3_OS_PROTECT_INTERRUPT protection level).
+ *
+ * \return  None
+ */
+extern void edma3OsProtectEntry (uint32_t edma3InstanceId,
+                                                                               int32_t level,
+                                                                               uint32_t *intState);
+
+/**
+ *  \brief  EDMA3 OS Protect Exit
+ *
+ *      This function undoes the protection enforced to original state
+ *      as is specified by the variable 'intState' passed, if the protection
+ *      level is EDMA3_OS_PROTECT_INTERRUPT.
+ *      For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and
+ *      EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored,
+ *      and the requested interrupt is enabled.
+ *      For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 'intState' specifies the
+ *      Transfer Controller number whose interrupt needs to be enabled.
+ *
+ * \param   edma3InstanceId is EDMA3 hardware instance id.
+ * \param   level is numeric identifier of the desired degree of protection.
+ * \param   intState is original state of protection at time when the
+ *      corresponding edma3OsProtectEntry() was called (Only
+ *      for EDMA3_OS_PROTECT_INTERRUPT protection level).
+ *
+ * \return  None
+ */
+extern void edma3OsProtectExit (uint32_t edma3InstanceId,
+                                                                               int32_t level,
+                                                                               uint32_t intState);
+
+/**
+ * Counting Semaphore related functions (OS dependent) should be
+ * implemented by the application for proper linking with the EDMA3
+ * Driver and Resource Manager. The EDMA3 Resource Manager
+ * uses these functions for proper sharing of resources (among various users)
+ * and assume the implementation of these functions
+ * to be provided by the application. Without the definitions being provided,
+ * the image won\92t get linked properly.
+ */
+
+/**
+ *  \brief  EDMA3 OS Semaphore Take
+ *
+ *      This function takes a semaphore token if available.
+ *      If a semaphore is unavailable, it blocks currently
+ *      running thread in wait (for specified duration) for
+ *      a free semaphore.
+ *
+ * \param   hSem [IN] is the handle of the specified semaphore
+ * \param   mSecTimeout [IN] is wait time in milliseconds
+ *
+ * \return  EDMA3_DRV_Result if successful else a suitable error code
+ */
+extern EDMA3_DRV_Result edma3OsSemTake (EDMA3_OS_Sem_Handle hSem,
+                                        int32_t mSecTimeout);
+
+/**
+ *  \brief  EDMA3 OS Semaphore Give
+ *
+ *      This function gives or relinquishes an already
+ *      acquired semaphore token
+ *
+ * \param   hSem [IN] is the handle of the specified semaphore
+ *
+ * \return  EDMA3_DRV_Result if successful else a suitable error code
+ */
+extern EDMA3_DRV_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif  /* _EDMA3_COMMON_H_ */
diff --git a/debian/edma3/usr/include/edma3_drv.h b/debian/edma3/usr/include/edma3_drv.h
new file mode 100644 (file)
index 0000000..68130c6
--- /dev/null
@@ -0,0 +1,3165 @@
+/*
+ * edma3_drv.h
+ *
+ * This file contains Application Interface for the EDMA3 Driver. EDMA3 Driver
+ * uses the EDMA3 Resource Manager internally for resource allocation, interrupt
+ * handling and EDMA3 registers programming.
+ *
+ * Copyright (C) 2009-2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/** @defgroup EDMA3_LLD_DRV_API EDMA3 Driver
+ *
+ * @section Introduction
+ *
+ * @subsection xxx Overview
+ *  EDMA3 Driver is a functional library providing APIs for programming,
+ *  scheduling and synchronizing with EDMA transfers and many more.
+ */
+
+#ifndef _EDMA3_DRV_H_
+#define _EDMA3_DRV_H_
+
+#include <stdint.h>
+
+/* Include the Resource Manager header file */
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+@defgroup EDMA3_LLD_DRV_SYMBOL  EDMA3 Driver Symbols
+@ingroup EDMA3_LLD_DRV_API
+*/
+/**
+@defgroup EDMA3_LLD_DRV_DATASTRUCT  EDMA3 Driver Data Structures
+@ingroup EDMA3_LLD_DRV_API
+*/
+/**
+@defgroup EDMA3_LLD_DRV_FUNCTION  EDMA3 Driver APIs
+@ingroup EDMA3_LLD_DRV_API
+*/
+
+/**
+@defgroup EDMA3_LLD_DRV_SYMBOL_DEFINE  EDMA3 Driver Defines
+@ingroup EDMA3_LLD_DRV_SYMBOL
+*/
+/**
+@defgroup EDMA3_LLD_DRV_SYMBOL_ENUM  EDMA3 Driver Enums
+@ingroup EDMA3_LLD_DRV_SYMBOL
+*/
+
+/**
+@defgroup EDMA3_LLD_DRV_FUNCTION_INIT  EDMA3 Driver Initialization APIs
+@ingroup EDMA3_LLD_DRV_FUNCTION
+*/
+/**
+@defgroup EDMA3_LLD_DRV_FUNCTION_BASIC  EDMA3 Driver Basic APIs
+@ingroup EDMA3_LLD_DRV_FUNCTION
+*/
+/**
+@defgroup EDMA3_LLD_DRV_FUNCTION_ADVANCED  EDMA3 Driver Advanced APIs
+@ingroup EDMA3_LLD_DRV_FUNCTION
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_DEFINE
+ @{ */
+
+ /**
+  * @brief   This is the EDMA3 LLD Version. Versions numbers are encoded in the following 
+  * format:
+  *  0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD) 
+  */
+#define EDMA3_LLD_DRV_VERSION_ID                   (0x020B0908)
+
+/**
+ * @brief   This is the version string which describes the EDMA3 LLD along with the
+ * date and build information.
+ */
+#define EDMA3_LLD_DRV_VERSION_STR                  "EDMA3 LLD Revision: 02.11.09.08"
+
+
+/** @brief EDMA3 Driver Error Codes Base define */
+#define EDMA3_DRV_E_BASE                        (-128)
+
+/**
+ * EDMA3 Driver Object Not Deleted yet.
+ * So it cannot be created.
+ */
+#define EDMA3_DRV_E_OBJ_NOT_DELETED             (EDMA3_DRV_E_BASE)
+
+/**
+ * EDMA3 Driver Object Not Closed yet.
+ * So it cannot be deleted.
+ */
+#define EDMA3_DRV_E_OBJ_NOT_CLOSED              (EDMA3_DRV_E_BASE-1)
+
+/**
+ * EDMA3 Driver Object Not Opened yet
+ * So it cannot be closed.
+ */
+#define EDMA3_DRV_E_OBJ_NOT_OPENED              (EDMA3_DRV_E_BASE-2)
+
+/**
+ * While closing EDMA3 Driver, Resource Manager
+ * Close Failed.
+ */
+#define EDMA3_DRV_E_RM_CLOSE_FAIL               (EDMA3_DRV_E_BASE-3)
+
+/** The requested DMA Channel not available */
+#define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL         (EDMA3_DRV_E_BASE-4)
+
+/** The requested QDMA Channel not available */
+#define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL        (EDMA3_DRV_E_BASE-5)
+
+/** The requested PaRAM Set not available */
+#define EDMA3_DRV_E_PARAM_SET_UNAVAIL           (EDMA3_DRV_E_BASE-6)
+
+/** The requested TCC not available */
+#define EDMA3_DRV_E_TCC_UNAVAIL                 (EDMA3_DRV_E_BASE-7)
+
+/** The registration of TCC failed */
+#define EDMA3_DRV_E_TCC_REGISTER_FAIL           (EDMA3_DRV_E_BASE-8)
+
+/** The binding of Channel and PaRAM Set failed */
+#define EDMA3_DRV_E_CH_PARAM_BIND_FAIL          (EDMA3_DRV_E_BASE-9)
+
+/**
+ * The address of the memory location passed as argument
+ * is not properly aligned. It should be 32 bytes aligned.
+ */
+#define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED         (EDMA3_DRV_E_BASE-10)
+
+/** Invalid Parameter passed to API */
+#define EDMA3_DRV_E_INVALID_PARAM               (EDMA3_DRV_E_BASE-11)
+
+/** Invalid State of EDMA3 HW Obj */
+#define EDMA3_DRV_E_INVALID_STATE                (EDMA3_DRV_E_BASE-12)
+
+/** EDMA3 Driver instance already exists for the specified region */
+#define EDMA3_DRV_E_INST_ALREADY_EXISTS         (EDMA3_DRV_E_BASE-13)
+
+/** FIFO width not supported by the requested TC */
+#define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED        (EDMA3_DRV_E_BASE-14)
+
+/** Semaphore related error */
+#define EDMA3_DRV_E_SEMAPHORE                       (EDMA3_DRV_E_BASE-15)
+
+/** EDMA3 Driver Instance does not exist, it is not opened yet */
+#define EDMA3_DRV_E_INST_NOT_OPENED         (EDMA3_DRV_E_BASE-16)
+
+/**
+ * This define is used to specify that a DMA channel is NOT tied to any PaRAM
+ * Set and hence any available PaRAM Set could be used for that DMA channel.
+ * It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global
+ * configuration structure EDMA3_RM_GblConfigParams.
+ *
+ * This value should mandatorily be used to mark DMA channels with no initial
+ * mapping to specific PaRAM Sets.
+ */
+#define EDMA3_DRV_CH_NO_PARAM_MAP           EDMA3_RM_CH_NO_PARAM_MAP
+
+/**
+ * This define is used to specify that the DMA/QDMA channel is not tied to any
+ * TCC and hence any available TCC could be used for that DMA/QDMA channel.
+ * It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global
+ * configuration structure EDMA3_RM_GblConfigParams.
+ *
+ * This value should mandatorily be used to mark DMA channels with no initial
+ * mapping to specific TCCs.
+ */
+#define EDMA3_DRV_CH_NO_TCC_MAP             EDMA3_RM_CH_NO_TCC_MAP
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_DATASTRUCT
+ @{ */
+
+/**\struct  EDMA3_DRV_GblConfigParams
+ * \brief   Init-time Configuration structure for EDMA3
+ * controller, to provide Global SoC specific Information.
+ *
+ * This configuration structure is used to specify the EDMA3 Driver
+ * global settings, specific to the SoC. For e.g. number of DMA/QDMA channels,
+ * number of PaRAM sets, TCCs, event queues, transfer controllers, base
+ * addresses of CC global registers and TC registers, interrupt number for
+ * EDMA3 transfer completion, CC error, event queues' priority, watermark
+ * threshold level etc.
+ * This configuration information is SoC specific and could be provided by the
+ * user at run-time while creating the EDMA3 Driver Object, using API
+ * EDMA3_DRV_create. In case user doesn't provide it, this information could be
+ * taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in
+ * case it is available.
+ */
+typedef struct  {
+    /** Number of DMA Channels supported by the underlying EDMA3 Controller. */
+    uint32_t        numDmaChannels;
+
+    /** Number of QDMA Channels supported by the underlying EDMA3 Controller */
+    uint32_t        numQdmaChannels;
+
+    /**
+     * Number of Interrupt Channels supported by the underlying EDMA3
+     * Controller
+     */
+    uint32_t        numTccs;
+
+    /** Number of PaRAM Sets supported by the underlying EDMA3 Controller */
+    uint32_t        numPaRAMSets;
+
+    /** Number of Event Queues in the underlying EDMA3 Controller */
+    uint32_t        numEvtQueue;
+
+    /**
+     * Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller
+     */
+    uint32_t        numTcs;
+
+    /** Number of Regions in the underlying EDMA3 Controller  */
+    uint32_t        numRegions;
+
+    /**
+     * \brief Channel mapping existence
+     *
+     * A value of 0 (No channel mapping) implies that there is fixed
+     * association between a DMA channel and a PaRAM Set or, in other words,
+     * DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP
+     * registers) for transfers to happen.
+     *
+     * A value of 1 implies the presence of DCHMAP registers for the DMA
+     * channels and hence the flexibility of associating any DMA channel to
+     * any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA
+     * channel (like QDMA Channels).
+     */
+    uint32_t           dmaChPaRAMMapExists;
+
+    /** Existence of memory protection feature */
+    uint32_t           memProtectionExists;
+
+    /** Base address of EDMA3 CC memory mapped registers. */
+    void                *globalRegs;
+
+    /** Base address of EDMA3 TCs memory mapped registers. */
+    void                *tcRegs[EDMA3_MAX_TC];
+
+    /**
+     * EDMA3 transfer completion interrupt line (could be different for ARM
+     * and DSP)
+     */
+    uint32_t        xferCompleteInt;
+
+    /** EDMA3 CC error interrupt line (could be different for ARM and DSP) */
+    uint32_t        ccError;
+
+    /** EDMA3 TCs error interrupt line (could be different for ARM and DSP) */
+    uint32_t        tcError[EDMA3_MAX_TC];
+
+    /**
+     * \brief EDMA3 TC priority setting
+     *
+     * User can program the priority of the Event Queues
+     * at a system-wide level.  This means that the user can set the
+     * priority of an IO initiated by either of the TCs (Transfer Controllers)
+     * relative to IO initiated by the other bus masters on the
+     * device (ARM, DSP, USB, etc)
+     */
+    uint32_t        evtQPri [EDMA3_MAX_EVT_QUE];
+
+    /**
+     * \brief Event Queues Watermark Levels
+
+     * To Configure the Threshold level of number of events
+     * that can be queued up in the Event queues. EDMA3CC error register
+     * (CCERR) will indicate whether or not at any instant of time the
+     * number of events queued up in any of the event queues exceeds
+     * or equals the threshold/watermark value that is set
+     * in the queue watermark threshold register (QWMTHRA).
+     */
+    uint32_t        evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE];
+
+    /**
+     * \brief Default Burst Size (DBS) of TCs.
+
+     * An optimally-sized command is defined by the transfer controller
+     * default burst size (DBS). Different TCs can have different
+     * DBS values. It is defined in Bytes.
+     */
+    uint32_t        tcDefaultBurstSize[EDMA3_MAX_TC];
+
+    /**
+     * \brief Mapping from DMA channels to PaRAM Sets
+
+     * If channel mapping exists (DCHMAP registers are present), this array
+     * stores the respective PaRAM Set for each DMA channel. User can
+     * initialize each array member with a specific PaRAM Set or with
+     * EDMA3_DRV_CH_NO_PARAM_MAP.
+     * If channel mapping doesn't exist, it is of no use as the EDMA3 RM
+     * automatically uses the right PaRAM Set for that DMA channel.
+     * Useful only if mapping exists, otherwise of no use.
+     */
+    uint32_t        dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH];
+
+     /**
+      * \brief Mapping from DMA channels to TCCs
+      *
+      * This array stores the respective TCC (interrupt channel) for each
+      * DMA channel. User can initialize each array member with a specific TCC
+      * or with EDMA3_DRV_CH_NO_TCC_MAP. This specific
+      * TCC code will be returned when the transfer is completed
+      * on the mapped DMA channel.
+      */
+     uint32_t       dmaChannelTccMap [EDMA3_MAX_DMA_CH];
+
+    /**
+     * \brief Mapping from DMA channels to Hardware Events
+     *
+     * Each bit in this array corresponds to one DMA channel and tells whether
+     * this DMA channel is tied to any peripheral. That is whether any
+     * peripheral can send the synch event on this DMA channel or not.
+     * 1 means the channel is tied to some peripheral; 0 means it is not.
+     * DMA channels which are tied to some peripheral are RESERVED for that
+     * peripheral only. They are not allocated when user asks for 'ANY' DMA
+     * channel.
+     * All channels need not be mapped, some can be free also.
+     */
+    uint32_t        dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS];
+    } EDMA3_DRV_GblConfigParams;
+
+/**\struct  EDMA3_DRV_InstanceInitConfig
+ * \brief   Init-time Region Specific Configuration structure for
+ * EDMA3 Driver, to provide region specific Information.
+ *
+ * This configuration structure is used to specify which EDMA3 resources are
+ * owned and reserved by the EDMA3 Driver instance. This configuration
+ * structure is shadow region specific and will be provided by the user at
+ * run-time while calling EDMA3_DRV_open ().
+ *
+ * Owned resources:
+ * ****************
+ *
+ * EDMA3 Driver Instances are tied to different shadow regions and hence different
+ * masters. Regions could be:
+ *
+ * a) ARM,
+ * b) DSP,
+ * c) IMCOP (Imaging Co-processor) etc.
+ *
+ * User can assign each EDMA3 resource to a shadow region using this structure.
+ * In this way, user specifies which resources are owned by the specific EDMA3
+ * DRV Instance.
+ * This assignment should also ensure that the same resource is not assigned
+ * to more than one shadow regions (unless desired in that way). Any assignment
+ * not following the above mentioned approach may have catastrophic
+ * consequences.
+ *
+ *
+ * Reserved resources:
+ * *******************
+ *
+ * During EDMA3 DRV initialization, user can reserve some of the EDMA3 resources
+ * for future use, by specifying which resources to reserve in the configuration
+ * data structure. These (critical) resources are reserved in advance so that
+ * they should not be allocated to someone else and thus could be used in
+ * future for some specific purpose.
+ *
+ * User can request different EDMA3 resources using two methods:
+ * a) By passing the resource type and the actual resource id,
+ * b) By passing the resource type and ANY as resource id
+ *
+ * For e.g. to request DMA channel 31, user will pass 31 as the resource id.
+ * But to request ANY available DMA channel (mainly used for memory-to-memory
+ * data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the
+ * resource id.
+ *
+ * During initialization, user may have reserved some of the DMA channels for
+ * some specific purpose (mainly for peripherals using EDMA). These reserved
+ * DMA channels then will not be returned when user requests ANY as the
+ * resource id.
+ *
+ * Same logic applies for QDMA channels and TCCs.
+ *
+ * For PaRAM Set, there is one difference. If the DMA channels are one-to-one
+ * tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set
+ * for a particular DMA channel), EDMA3 Driver automatically reserves all those
+ * PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would
+ * not be returned when user requests for ANY PaRAM Set (specifically for
+ * linking purpose). This is done in order to avoid allocating the PaRAM Set,
+ * tied to a particular DMA channel, for linking purpose. If this constraint is
+ * not there, that DMA channel thus could not be used at all, because of the
+ * unavailability of the desired PaRAM Set.
+ */
+typedef struct
+{
+    /** PaRAM Sets owned by the EDMA3 Driver Instance. */
+    uint32_t        ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
+
+    /** DMA Channels owned by the EDMA3 Driver Instance. */
+    uint32_t        ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
+
+    /** QDMA Channels owned by the EDMA3 Driver Instance. */
+    uint32_t        ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
+
+    /** TCCs owned by the EDMA3 Driver Instance. */
+    uint32_t        ownTccs[EDMA3_MAX_TCC_DWRDS];
+
+    /**
+     * \brief   Reserved PaRAM Sets
+     *
+     * PaRAM Sets reserved during initialization for future use. These will not
+     * be given when user requests for ANY available PaRAM Set for linking
+     * using 'EDMA3_DRV_LINK_CHANNEL' as channel id.
+     */
+    uint32_t        resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
+
+    /**
+     * \brief   Reserved DMA channels
+     *
+     * DMA channels reserved during initialization for future use. These will
+     * not be given when user requests for ANY available DMA channel using
+     * 'EDMA3_DRV_DMA_CHANNEL_ANY' as channel id.
+     */
+    uint32_t        resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
+
+    /**
+     * \brief   Reserved QDMA channels
+     *
+     * QDMA channels reserved during initialization for future use. These will
+     * not be given when user requests for ANY available QDMA channel using
+     * 'EDMA3_DRV_QDMA_CHANNEL_ANY' as channel id.
+     */
+    uint32_t        resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
+
+    /**
+     * \brief   Reserved TCCs
+     *
+     * TCCs reserved during initialization for future use. These will not
+     * be given when user requests for ANY available TCC using
+     * 'EDMA3_DRV_TCC_ANY' as resource id.
+     */
+    uint32_t        resvdTccs[EDMA3_MAX_TCC_DWRDS];
+}EDMA3_DRV_InstanceInitConfig;
+
+/**\struct      EDMA3_DRV_InitConfig
+ * \brief       Used to Initialize the EDMA3 Driver Instance
+ *
+ * This configuration structure is used to initialize the EDMA3 DRV Instance.
+ * This configuration information is passed while opening the DRV instance.
+ */
+typedef struct
+{
+    /** Region Identification */
+    EDMA3_RM_RegionId       regionId;
+
+    /**
+     * It tells whether the EDMA3 DRV instance is Master or not. Only the shadow
+     * region associated with this master instance will receive the EDMA3
+     * interrupts (if enabled).
+     */
+    uint32_t                   isMaster;
+
+    /**
+     * EDMA3 resources related shadow region specific information. Which all
+     * EDMA3 resources are owned and reserved by this particular instance are
+     * told in this configuration structure.
+     * User can also pass this structure as NULL. In that case, default static
+     * configuration would be taken from the platform specific configuration
+     * files (part of the Resource Manager), if available.
+     */
+    EDMA3_DRV_InstanceInitConfig    *drvInstInitConfig;
+
+    /**
+     * EDMA3 Driver Instance specific semaphore handle.
+     * Used to share resources (DMA/QDMA channels, PaRAM Sets, TCCs etc)
+     * among different users.
+     */
+    void                    *drvSemHandle;
+
+    /**
+     * Instance wide global callback function to catch non-channel
+     * specific errors from the Channel controller. for eg, TCC
+     * error, queue threshold exceed error etc.
+     */
+    EDMA3_RM_GblErrCallback gblerrCb;
+
+    /**
+     * Application data to be passed back to the global error callback
+     * function
+     */
+    void                    *gblerrData;
+} EDMA3_DRV_InitConfig;
+
+/**\struct      EDMA3_DRV_MiscParam
+ * \brief       Used to specify the miscellaneous options during EDMA3 Driver
+ * Initialization.
+ *
+ * This configuration structure is used to specify some misc options
+ * while creating the Driver object. New options may also be added into this
+ * structure in future.
+ */
+typedef struct {
+    /**
+     * In a multi-master system (for e.g. ARM + DSP), this option is used to
+     * distinguish between Master and Slave. Only the Master is allowed  to
+     * program the global EDMA3 registers (like Queue priority, Queue water-
+     * mark level, error registers etc).
+     */
+    uint16_t          isSlave;
+
+    /** For future use **/
+    uint16_t          param;
+}EDMA3_DRV_MiscParam;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_INIT
+ @{ */
+
+/**
+ * \brief   Create EDMA3 Driver Object
+ *
+ * This API is used to create the EDMA3 Driver Object. It should be
+ * called only ONCE for each EDMA3 hardware instance.
+ *
+ * Init-time Configuration structure for EDMA3 hardware is provided to pass the
+ * SoC specific information. This configuration information could be provided
+ * by the user at init-time. In case user doesn't provide it, this information
+ * could be taken from the SoC specific configuration file
+ * edma3_<SOC_NAME>_cfg.c, in case it is available.
+ *
+ * This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR)
+ * and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam'
+ * argument is NULL. User can avoid these registers' programming (in some specific
+ * use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration
+ * structure and passing this structure as the third argument (miscParam).
+ *
+ * After successful completion of this API, Driver Object's state
+ * changes to EDMA3_DRV_CREATED from EDMA3_DRV_DELETED.
+ *
+ * \param phyCtrllerInstId  [IN]    EDMA3 Controller Instance Id
+ *                                 (Hardware instance id, starting from 0).
+ * \param gblCfgParams      [IN]    SoC specific configuration structure for the
+ *                                  EDMA3 Hardware.
+ * \param miscParam         [IN]    Misc configuration options provided in the
+ *                                  structure 'EDMA3_DRV_MiscParam'.
+ *                                  For default options, user can pass NULL
+ *                                  in this argument.
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error code
+ */
+EDMA3_DRV_Result EDMA3_DRV_create (uint32_t phyCtrllerInstId,
+                                const EDMA3_DRV_GblConfigParams *gblCfgParams,
+                                const void *miscParam);
+/**
+ * \brief Delete EDMA3 Driver Object
+ *
+ * Use this API to delete the EDMA3 Driver Object. It should be called only
+ * ONCE for each EDMA3 hardware instance. It should be called ONLY after
+ * closing all the EDMA3 Driver Instances.
+ *
+ * This API is used to delete the EDMA3 Driver Object. It should be called
+ * once for each EDMA3 hardware instance, ONLY after closing all the
+ * previously opened EDMA3 Driver Instances.
+ *
+ * After successful completion of this API, Driver Object's state
+ * changes to EDMA3_DRV_DELETED.
+ *
+ * \param phyCtrllerInstId  [IN]    EDMA3 Phy Controller Instance Id (Hardware
+ *                                  instance id, starting from 0).
+ * \param param             [IN]    For possible future use.
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error code
+ */
+EDMA3_DRV_Result EDMA3_DRV_delete (uint32_t phyCtrllerInstId,
+                                    const void *param);
+
+/**
+ * \brief   Open EDMA3 Driver Instance
+ *
+ * This API is used to open an EDMA3 Driver Instance. It could be
+ * called multiple times, for each possible EDMA3 shadow region. Maximum
+ * EDMA3_MAX_REGIONS instances are allowed for each EDMA3 hardware
+ * instance. Multiple instances on the same shadow region are NOT allowed.
+ *
+ * Also, only ONE Master Driver Instance is permitted. This master
+ * instance (and hence the region to which it belongs) will only receive the
+ * EDMA3 interrupts, if enabled.
+ *
+ * User could pass the instance specific configuration structure
+ * (initCfg.drvInstInitConfig) as a part of the 'initCfg' structure,
+ * during init-time. In case user doesn't provide it, this information could
+ * be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c,
+ * in case it is available.
+ *
+ * By default, this EDMA3 Driver instance will clear the PaRAM Sets while
+ * allocating them. To change the default behavior, user should use the IOCTL
+ * interface appropriately.
+ *
+ * \param   phyCtrllerInstId    [IN]    EDMA3 Controller Instance Id (Hardware
+ *                                      instance id, starting from 0).
+ * \param   initCfg             [IN]    Used to Initialize the EDMA3 Driver
+ *                                      Instance (Master or Slave).
+ * \param   errorCode           [OUT]   Error code while opening DRV instance.
+ *
+ * \return EDMA3_DRV_Handle : If successfully opened, the API will return the
+ *                            associated driver's instance handle.
+ *
+ * \note    This function disables the global interrupts (by calling API
+ *          edma3OsProtectEntry with protection level
+ *          EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data
+ *          structures, to make it re-entrant.
+ */
+EDMA3_DRV_Handle EDMA3_DRV_open (uint32_t phyCtrllerInstId,
+                        const EDMA3_DRV_InitConfig *initCfg,
+                        EDMA3_DRV_Result *errorCode);
+
+/**
+ * \brief Close the EDMA3 Driver Instance.
+ *
+ * This API is used to close a previously opened EDMA3 Driver Instance.
+ *
+ * \param  hEdma            [IN]    Handle to the previously opened EDMA3
+ *                                  Driver Instance.
+ * \param param             [IN]    For possible future use
+ *
+ * \return EDMA3_DRV_SOK or EDMA3_DRV Error code
+ *
+ * \note    This function disables the global interrupts (by calling API
+ *          edma3OsProtectEntry with protection level
+ *          EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data
+ *          structures, to make it re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
+                                const void *param);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_DEFINE
+ @{ */
+
+/* Defines for Logical Channel Values */
+/*---------------------------------------------------------------------------*/
+/**
+ * Used to specify any available DMA Channel while requesting
+ * one. Used in the API EDMA3_DRV_requestChannel().
+ * DMA channel from the pool of (owned && non_reserved && available_right_now)
+ * DMA channels will be chosen and returned.
+ */
+#define EDMA3_DRV_DMA_CHANNEL_ANY                   1002u
+
+/**
+ * Used to specify any available QDMA Channel while requesting
+ * one. Used in the API EDMA3_DRV_requestChannel().
+ * QDMA channel from the pool of (owned && non_reserved && available_right_now)
+ * QDMA channels will be chosen and returned.
+ */
+#define EDMA3_DRV_QDMA_CHANNEL_ANY                  1003u
+
+/**
+ * Used to specify any available TCC while requesting
+ * one. Used in the API EDMA3_DRV_requestChannel(), for
+ * both DMA and QDMA channels.
+ * TCC from the pool of (owned && non_reserved && available_right_now)
+ * TCCs will be chosen and returned.
+ */
+#define EDMA3_DRV_TCC_ANY                           1004u
+
+/**
+ * Used to specify any available PaRAM Set while requesting
+ * one. Used in the API EDMA3_DRV_requestChannel(), for Link channels.
+ * PaRAM Set from the pool of (owned && non_reserved && available_right_now)
+ * PaRAM Sets will be chosen and returned.
+ */
+#define EDMA3_DRV_LINK_CHANNEL                      1005u
+
+/**
+ * Used to specify any available PaRAM Set while requesting one. Used in the
+ * API EDMA3_DRV_requestChannel(), for Link channels.
+ * TCC code should also be specified and it will be used to populate the LINK
+ * field of the PaRAM Set. Without TCC code, the call will fail.
+ * PaRAM Set from the pool of (owned && non_reserved && available_right_now)
+ * PaRAM Sets will be chosen and returned.
+ */
+#define EDMA3_DRV_LINK_CHANNEL_WITH_TCC                                1006u
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
+
+/**
+ * \brief DMA Channels assigned to different Hardware Events.
+ *
+ * They should be used while requesting a specific DMA channel.
+ * One possible usage is to maintain a SoC specific file, which will
+ * contain the mapping of these hardware events to the respective
+ * peripherals for better understanding and lesser probability of
+ * errors. Also, if any event associated with a particular peripheral
+ * gets changed, only that SoC specific file needs to be changed.
+ * for eg, the sample SoC specific file "soc.h" can have these defines:
+ *
+ * #define EDMA3_DRV_HW_CHANNEL_MCBSP_TX        EDMA3_DRV_HW_CHANNEL_EVENT_2
+ * #define EDMA3_DRV_HW_CHANNEL_MCBSP_RX        EDMA3_DRV_HW_CHANNEL_EVENT_3
+ *
+ * These defines will be used by the MCBSP driver. The same event
+ * EDMA3_DRV_HW_CHANNEL_EVENT_2/3 could be mapped to some other
+ * peripheral also.
+ */
+typedef enum
+{
+    /** Channel assigned to EDMA3 Event 0 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_0 = 0,
+    /** Channel assigned to EDMA3 Event 1 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_1,
+    /** Channel assigned to EDMA3 Event 2 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_2,
+    /** Channel assigned to EDMA3 Event 3 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_3,
+    /** Channel assigned to EDMA3 Event 4 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_4,
+    /** Channel assigned to EDMA3 Event 5 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_5,
+    /** Channel assigned to EDMA3 Event 6 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_6,
+    /** Channel assigned to EDMA3 Event 7 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_7,
+    /** Channel assigned to EDMA3 Event 8 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_8,
+    /** Channel assigned to EDMA3 Event 9 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_9,
+    /** Channel assigned to EDMA3 Event 10 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_10,
+    /** Channel assigned to EDMA3 Event 11 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_11,
+    /** Channel assigned to EDMA3 Event 12 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_12,
+    /** Channel assigned to EDMA3 Event 13 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_13,
+    /** Channel assigned to EDMA3 Event 14 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_14,
+    /** Channel assigned to EDMA3 Event 15 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_15,
+    /** Channel assigned to EDMA3 Event 16 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_16,
+    /** Channel assigned to EDMA3 Event 17 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_17,
+    /** Channel assigned to EDMA3 Event 18 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_18,
+    /** Channel assigned to EDMA3 Event 19 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_19,
+    /** Channel assigned to EDMA3 Event 20 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_20,
+    /** Channel assigned to EDMA3 Event 21 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_21,
+    /** Channel assigned to EDMA3 Event 22 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_22,
+    /** Channel assigned to EDMA3 Event 23 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_23,
+    /** Channel assigned to EDMA3 Event 24 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_24,
+    /** Channel assigned to EDMA3 Event 25 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_25,
+    /** Channel assigned to EDMA3 Event 26 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_26,
+    /** Channel assigned to EDMA3 Event 27 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_27,
+    /** Channel assigned to EDMA3 Event 28 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_28,
+    /** Channel assigned to EDMA3 Event 29 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_29,
+    /** Channel assigned to EDMA3 Event 30 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_30,
+    /** Channel assigned to EDMA3 Event 31 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_31,
+    /** Channel assigned to EDMA3 Event 32 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_32,
+    /** Channel assigned to EDMA3 Event 33 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_33,
+    /** Channel assigned to EDMA3 Event 34 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_34,
+    /** Channel assigned to EDMA3 Event 35 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_35,
+    /** Channel assigned to EDMA3 Event 36 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_36,
+    /** Channel assigned to EDMA3 Event 37 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_37,
+    /** Channel assigned to EDMA3 Event 38 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_38,
+    /** Channel assigned to EDMA3 Event 39 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_39,
+    /** Channel assigned to EDMA3 Event 40 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_40,
+    /** Channel assigned to EDMA3 Event 41 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_41,
+    /** Channel assigned to EDMA3 Event 42 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_42,
+    /** Channel assigned to EDMA3 Event 43 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_43,
+    /** Channel assigned to EDMA3 Event 44 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_44,
+    /** Channel assigned to EDMA3 Event 45 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_45,
+    /** Channel assigned to EDMA3 Event 46 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_46,
+    /** Channel assigned to EDMA3 Event 47 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_47,
+    /** Channel assigned to EDMA3 Event 48 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_48,
+    /** Channel assigned to EDMA3 Event 49 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_49,
+    /** Channel assigned to EDMA3 Event 50 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_50,
+    /** Channel assigned to EDMA3 Event 51 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_51,
+    /** Channel assigned to EDMA3 Event 52 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_52,
+    /** Channel assigned to EDMA3 Event 53 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_53,
+    /** Channel assigned to EDMA3 Event 54 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_54,
+    /** Channel assigned to EDMA3 Event 55 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_55,
+    /** Channel assigned to EDMA3 Event 56 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_56,
+    /** Channel assigned to EDMA3 Event 57 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_57,
+    /** Channel assigned to EDMA3 Event 58 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_58,
+    /** Channel assigned to EDMA3 Event 59 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_59,
+    /** Channel assigned to EDMA3 Event 60 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_60,
+    /** Channel assigned to EDMA3 Event 61 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_61,
+    /** Channel assigned to EDMA3 Event 62 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_62,
+    /** Channel assigned to EDMA3 Event 63 */
+    EDMA3_DRV_HW_CHANNEL_EVENT_63
+} EDMA3_DRV_HW_CHANNEL_EVENT;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_DEFINE
+ @{ */
+
+/**
+ * \brief QDMA Channel defines
+ *
+ * They should be used while requesting a specific QDMA channel in API
+ * EDMA3_DRV_requestChannel() as the argument (*pLch). Please note that
+ * these defines should ONLY be used in the API EDMA3_DRV_requestChannel() and
+ * not in any other API to perform further operations. They are only provided
+ * to allow user allocate specific QDMA channels.
+ */
+/** QDMA Channel 0 */
+#define EDMA3_DRV_QDMA_CHANNEL_0    (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
+/** QDMA Channel 1 */
+#define EDMA3_DRV_QDMA_CHANNEL_1    (EDMA3_DRV_QDMA_CHANNEL_0+1u)
+/** QDMA Channel 2 */
+#define EDMA3_DRV_QDMA_CHANNEL_2    (EDMA3_DRV_QDMA_CHANNEL_0+2u)
+/** QDMA Channel 3 */
+#define EDMA3_DRV_QDMA_CHANNEL_3    (EDMA3_DRV_QDMA_CHANNEL_0+3u)
+/** QDMA Channel 4 */
+#define EDMA3_DRV_QDMA_CHANNEL_4    (EDMA3_DRV_QDMA_CHANNEL_0+4u)
+/** QDMA Channel 5 */
+#define EDMA3_DRV_QDMA_CHANNEL_5    (EDMA3_DRV_QDMA_CHANNEL_0+5u)
+/** QDMA Channel 6 */
+#define EDMA3_DRV_QDMA_CHANNEL_6    (EDMA3_DRV_QDMA_CHANNEL_0+6u)
+/** QDMA Channel 7 */
+#define EDMA3_DRV_QDMA_CHANNEL_7    (EDMA3_DRV_QDMA_CHANNEL_0+7u)
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_BASIC
+ @{ */
+
+/**
+ *  \brief Request a DMA/QDMA/Link channel.
+ *
+ *  Each channel (DMA/QDMA/Link) must be requested  before initiating a DMA
+ *  transfer on that channel.
+ *
+ * This API is used to allocate a logical channel (DMA/QDMA/Link) along with
+ * the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are
+ * also allocated along with the requested channel. User can also specify a
+ * specific TCC which needs to be allocated with the DMA/QDMA channel or else
+ * can request any available TCC.
+ *
+ * For Link channels, ONLY a PaRAM Set is allocated and the allocated PaRAM Set
+ * number is returned as the logical channel no. A TCC code can also be
+ * specified while making the request. This TCC code will be copied to the
+ * LINK field of the allocated PaRAM Set and will be associated with the Link
+ * channel.
+ *
+ * User can request a specific logical channel - DMA, QDMA and Link, by passing
+ * the channel id in 'pLCh'. Note that the channel id is the same as the actual
+ * resource id in case of DMA channels and Link channels. For DMA channels,
+ * channel id lies between 0 and (max dma channels - 1). For Link channels,
+ * channel id lies between (max dma channels) and (max param sets - 1). To
+ * allocate specific QDMA channels, user SHOULD use the defines
+ * EDMA3_DRV_QDMA_CHANNEL_X mentioned above.
+ *
+ * User can also request ANY available logical channel by specifying the
+ * below mentioned values in '*pLCh':
+ *  a)  EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels
+ *  b)  EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and
+ *  c)  EDMA3_DRV_LINK_CHANNEL: For Link channels. Normally user should use this
+ *      value to request link channels (PaRAM Sets used for linking purpose
+ *      only), unless he wants to use some specific link channels (PaRAM Sets)
+ *      which is also allowed.
+ *  d)  EDMA3_DRV_LINK_CHANNEL_WITH_TCC: For Link channels. User should
+ *      use this value to request link channels with TCC code.
+ *
+ * This API internally uses EDMA3_RM_allocResource () to allocate the desired
+ * resources (DMA/QDMA channel, PaRAM Set and TCC).
+ *
+ * This API also registers a specific callback function, in case the same is
+ * provided, against the allocated TCC. To do this, this API calls
+ * EDMA3_RM_registerTccCb(), which is a part of the Resource Manager. Please
+ * note that the interrupts are enabled for the specific TCC only if callback
+ * function is provided. In the absence of this, the API assumes that the
+ * requested logical channel is going to be used in Poll mode environment.
+ *
+ * For DMA/QDMA channels, after allocating all the EDMA3 resources, this API
+ * sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets
+ * the event queue for the channel allocated. The event queue needs to be
+ * specified by the user.
+ *
+ * For DMA channel, it also sets the DCHMAP register, if required.
+ *
+ * For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and
+ * enables the QDMA channel by writing to the QEESR register.
+ *
+ *  \param  hEdma           [IN]        Handle to the previously opened Driver
+ *                                      Instance.
+ *  \param  pLCh            [IN/OUT]    Requested logical channel id.
+ *                                      Examples:
+ *                                      - EDMA3_DRV_HW_CHANNEL_EVENT_0
+ *                                      - To request a DMA Master Channel
+ *                                        mapped to EDMA Event 0.
+ *
+ *                                      - EDMA3_DRV_DMA_CHANNEL_ANY
+ *                                      - For requesting any DMA Master channel
+ *                                        with no event mapping.
+ *
+ *                                      - EDMA3_DRV_QDMA_CHANNEL_ANY
+ *                                      - For requesting any QDMA Master channel
+ *
+ *                                      - EDMA3_DRV_QDMA_CHANNEL_0
+ *                                      - For requesting the QDMA Channel 0.
+ *
+ *                                      - EDMA3_DRV_LINK_CHANNEL
+ *                                      - For requesting a DMA Slave Channel,
+ *                                      - to be linked to some other Master
+ *                                      - channel.
+ *
+ *                                      - EDMA3_DRV_LINK_CHANNEL_WITH_TCC
+ *                                      - For requesting a DMA Slave Channel,
+ *                                      - to be linked to some other Master
+ *                                      - channel, with a TCC associated with it.
+ *
+ *                                      In case user passes a specific channel
+ *                                      Id, pLCh value is left unchanged. In
+ *                                      case user requests ANY available
+ *                                      resource, the allocated channel id is
+ *                                      returned in pLCh.
+ *
+ *  \note   To request  a PaRAM Set for the purpose of
+ *          linking to another channel,  call the function with
+ *
+ *          *pLCh = EDMA3_DRV_LINK_CHANNEL or EDMA3_DRV_LINK_CHANNEL_WITH_TCC
+ *
+ *          This function will update *pLCh with the allocated Link channel
+ *          handle.
+ *
+ *  \param  pTcc             [IN/OUT]   The channel number on which the
+ *                                      completion/error interrupt is generated.
+ *                                      Not used if user requested for a Link
+ *                                      channel.
+ *                                      Examples:
+ *                                      - EDMA3_DRV_HW_CHANNEL_EVENT_0
+ *                                      - To request TCC associated with
+ *                                      - DMA Master Channel mapped to EDMA
+ *                                      - event 0.
+ *
+ *                                      - EDMA3_DRV_TCC_ANY
+ *                                      - For requesting any TCC with no
+ *                                      - channel mapping.
+ *                                      In case user passes a specific TCC
+ *                                      value, pTcc value is left unchanged.
+ *                                      In case user requests ANY available TCC,
+ *                                      the allocated one is returned in pTcc
+ *
+ *  \param  evtQueue         [IN]       Event Queue Number to which the channel
+ *                                      will be mapped (valid only for the
+ *                                      Master Channel (DMA/QDMA) request)
+ *
+ *  \param tccCb             [IN]       TCC callback - caters to channel-
+ *                                      specific events like "Event Miss Error"
+ *                                      or "Transfer Complete"
+ *
+ *  \param cbData            [IN]       Data which will be passed directly to
+ *                                      the tccCb callback function
+ *
+ *  \return EDMA3_DRV_SOK or EDMA3_DRV Error code
+ *
+ *  \note    This function internally uses EDMA3 Resource Manager, which
+ *           acquires a RM Instance specific semaphore
+ *           to prevent simultaneous access to the global pool of resources.
+ *           It also disables the global interrupts while modifying
+ *           the global CC registers.
+ *           It is re-entrant, but SHOULD NOT be called from the user callback
+ *           function (ISR context).
+ */
+EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
+                                    uint32_t *pLCh,
+                                    uint32_t *pTcc,
+                                    EDMA3_RM_EventQueue evtQueue,
+                                    EDMA3_RM_TccCallback tccCb,
+                                    void *cbData);
+
+/**
+ * \brief Free the specified channel (DMA/QDMA/Link) and its associated
+ * resources (PaRAM Set, TCC etc) and removes various mappings.
+ *
+ * This API internally uses EDMA3_RM_freeResource () to free the desired
+ * resources.
+ *
+ * For Link channels, this API only frees the associated PaRAM Set.
+ *
+ * For DMA/QDMA channels, it does the following operations:
+ * a) Disable any ongoing transfer on the channel,
+ * b) Unregister the TCC Callback function and disable the interrupts,
+ * c) Remove the channel to Event Queue mapping,
+ * d) For DMA channels, clear the DCHMAP register, if available
+ * e) For QDMA channels, clear the QCHMAP register,
+ * f) Frees the DMA/QDMA channel in the end.
+ *
+ *  \param  hEdma            [IN]     Handle to the EDMA Driver Instance.
+ *  \param  channelId        [IN]     Logical Channel number to be freed.
+ *
+ *  \return EDMA3_DRV_SOK or EDMA3_DRV Error code
+ *
+ *  \note    This function disables the global interrupts while modifying
+ *           the global CC registers and while modifying global data structures,
+ *           to prevent simultaneous access to the global pool of resources.
+ *           It internally calls EDMA3_RM_freeResource () for resource
+ *           de-allocation. It is re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
+                                                uint32_t channelId);
+
+/**
+ *  \brief  Disables the DMA Channel by clearing the Event Enable Register and
+ *     clears Error Register & Secondary Event Register for a specific DMA channel.
+ *
+ *  This API clears the Event Enable register, Event Miss register and Secondary
+ *     Event register for a specific DMA channel. It also clears the CC Error
+ *     register.
+ *
+ *  \param  hEdma            [IN]     Handle to the EDMA Driver Instance.
+ *  \param  channelId        [IN]     DMA Channel needs to be cleaned.
+ *
+ *  \return EDMA3_DRV_SOK or EDMA3_DRV Error code
+ *
+ *  \note    This function is re-entrant for unique channelId values. It is non-
+ *          re-entrant for same channelId value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
+                                                    uint32_t channelId);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
+
+/**
+ * \brief  Link two logical channels.
+ *
+ * This API is used to link two previously allocated logical (DMA/QDMA/Link)
+ * channels.
+ *
+ * It sets the Link field of the PaRAM set associated with first logical
+ * channel (lCh1) to point it to the PaRAM set associated with second logical
+ * channel (lCh2).
+ *
+ * It also sets the TCC field of PaRAM set of second logical channel to the
+ * same as that of the first logical channel, only if the TCC field doesnot
+ * contain a valid TCC code. In case the second logical channel has its own TCC,
+ * the TCC field remains unchanged.
+ *
+ * \param   hEdma           [IN]    Handle to the EDMA Driver Instance.
+ * \param   lCh1            [IN]    Logical Channel to which particular channel
+ *                                  will be linked.
+ * \param   lCh2            [IN]    Logical Channel which needs to be linked to
+ *                                  the first channel.
+ *                                  After the transfer based on the PaRAM set
+ *                                  of lCh1 is over, the PaRAM set of lCh2 will
+ *                                  be copied to the PaRAM set of lCh1 and
+ *                                  transfer will resume.
+ *                                  For DMA channels, another sync event is
+ *                                  required to initiate the transfer on the
+ *                                  Link channel.
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh1 & lCh2 values. It is
+ *          non-re-entrant for same lCh1 & lCh2 values.
+ */
+EDMA3_DRV_Result EDMA3_DRV_linkChannel ( EDMA3_DRV_Handle hEdma,
+                                                uint32_t lCh1,
+                                                uint32_t lCh2);
+
+/**
+ * \brief  Unlink the channel from the earlier linked logical channel.
+ *
+ *         This function breaks the link between the specified
+ *         channel and the earlier linked logical channel
+ *         by clearing the Link Address field.
+ *
+ * \param  hEdma             [IN]    Handle to the EDMA Driver Instance.
+ * \param  lCh               [IN]    Channel for which linking has to be removed
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma,
+                                                    uint32_t lCh);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
+
+/**
+ * \brief OPT Field Offset.
+ *
+ * Use this enum to set or get any of the
+ * Fields within an OPT of a Parameter RAM set.
+ */
+typedef enum
+{
+        /**
+         * Source addressing mode (INCR / FIFO)
+         * (Bit 0)
+         */
+        EDMA3_DRV_OPT_FIELD_SAM = 0,
+
+        /**
+         * Destination addressing mode (INCR / FIFO)
+         * (Bit 1)
+         */
+        EDMA3_DRV_OPT_FIELD_DAM = 1,
+
+        /**
+         * Transfer synchronization dimension (A-synchronized / AB-synchronized)
+         * (Bit 2)
+         */
+        EDMA3_DRV_OPT_FIELD_SYNCDIM = 2,
+
+        /**
+         * The STATIC field
+         * PaRAM set is static/non-static?
+         * (Bit 3)
+         */
+        EDMA3_DRV_OPT_FIELD_STATIC  = 3,
+
+        /**
+         * FIFO Width. Applies if either SAM or DAM is set to FIFO mode.
+         * (Bitfield 8-10)
+         */
+        EDMA3_DRV_OPT_FIELD_FWID = 4,
+
+        /**
+         * Transfer complete code mode. Indicates the point at which a
+         * transfer is considered completed for chaining and interrupt
+         * generation.
+         * (Bit 11)
+         */
+        EDMA3_DRV_OPT_FIELD_TCCMODE = 5,
+
+        /**
+         * Transfer Complete Code (TCC).
+         * This 6-bit code is used to set the relevant bit in chaining enable
+         * register (CER[TCC]/CERH[TCC]) for chaining or in interrupt pending
+         * register (IPR[TCC]/IPRH[TCC]) for interrupts.
+         * (Bitfield 12-17)
+         */
+        EDMA3_DRV_OPT_FIELD_TCC = 6,
+
+        /**
+         * Transfer complete interrupt enable/disable.
+         * (Bit 20)
+         */
+        EDMA3_DRV_OPT_FIELD_TCINTEN = 7,
+
+        /**
+         * Intermediate transfer complete interrupt enable/disable.
+         * (Bit 21)
+         */
+        EDMA3_DRV_OPT_FIELD_ITCINTEN = 8,
+
+        /**
+         * Transfer complete chaining enable/disable
+         * (Bit 22)
+         */
+        EDMA3_DRV_OPT_FIELD_TCCHEN = 9,
+
+        /**
+         * Intermediate transfer completion chaining enable/disable
+         * (Bit 23)
+         */
+        EDMA3_DRV_OPT_FIELD_ITCCHEN = 10
+
+} EDMA3_DRV_OptField;
+
+/**
+ * \brief EDMA Addressing modes
+ *
+ * The EDMA3 TC supports two addressing modes
+ *           -# Increment transfer
+ *           -# FIFO transfer
+ *
+ * The SAM (Source Addressing Mode) and the DAM (Destination Addressing Mode)
+ * can be independently set to either of the two via the OPT register.
+ *
+ */
+typedef enum
+{
+        /**
+         * Increment (INCR) mode. Source addressing within an array increments.
+         * Source is not a FIFO.
+         */
+        EDMA3_DRV_ADDR_MODE_INCR            = 0,
+
+        /**
+         * FIFO mode. Source addressing within an array wraps around upon
+         * reaching FIFO width.
+         */
+        EDMA3_DRV_ADDR_MODE_FIFO            = 1
+
+} EDMA3_DRV_AddrMode;
+
+/**
+ * \brief EDMA Transfer Synchronization type.
+ *
+ * Two types of Synchronization of transfers are possible
+ *     -# A Synchronized
+ *     -# AB Syncronized
+ * - A Sync
+ *     -# Each Array is submitted as one TR
+ *     -# (BCNT*CCNT) number of sync events are needed to completely service
+ *        a PaRAM set. (Where BCNT = Num of Arrays in a Frame;
+ *                            CCNT = Num of Frames in a Block)
+ *     -# (S/D)CIDX = (Addr of First array in next frame)
+ *              minus (Addr of Last array in present frame)
+ *     (Where CIDX is the Inter-Frame index)
+ *
+ * - AB Sync
+ *     -# Each Frame is submitted as one TR
+ *     -# Only CCNT number of sync events are needed to completely service
+ *        a PaRAM set
+ *     -# (S/D)CIDX = (Addr of First array in next frame)
+ *              minus (Addr of First array of present frame)
+ *
+ * \note ABC sync transfers can be achieved logically by chaining multiple
+ *       AB sync transfers
+ *
+ */
+typedef enum
+{
+        /**
+         * A-synchronized.
+         * Each event triggers the transfer of a single array of ACNT bytes
+         */
+        EDMA3_DRV_SYNC_A = 0 ,
+
+        /**
+         * AB-synchronized.
+         * Each event triggers the transfer of BCNT arrays of ACNT bytes
+         */
+    EDMA3_DRV_SYNC_AB = 1
+
+} EDMA3_DRV_SyncType;
+
+/**
+ * \brief True/False: PaRAM set is Static or not. A Static PaRAM set
+ * is updated or linked after TR is submitted.
+ */
+typedef enum
+{
+    /**
+     * PaRAM set is not Static. PaRAM set is updated or linked
+     * after TR is submitted. A value of 0 should be used for
+     * DMA channels and for nonfinal transfers in a linked list
+     * of QDMA transfers
+     */
+    EDMA3_DRV_STATIC_DIS      = 0,
+
+    /**
+     * PaRAM set is Static. PaRAM set is not updated or linked
+     * after TR is submitted. A value of 1 should be used for
+     * isolated QDMA transfers or for the final transfer in a
+     * linked list of QDMA transfers.
+     */
+    EDMA3_DRV_STATIC_EN       = 1
+} EDMA3_DRV_StaticMode;
+
+/**
+ * \brief EDMA3 FIFO width.
+ *
+ * The user can set the width of the FIFO using this enum.
+ * This is done via the OPT register.
+ * This is valid only if the EDMA3_DRV_ADDR_MODE_FIFO value is used for the
+ * enum EDMA3_DRV_AddrMode.
+ */
+typedef enum
+{
+        /** FIFO width is 8-bit. */
+        EDMA3_DRV_W8BIT = 0,
+
+        /** FIFO width is 16-bit. */
+        EDMA3_DRV_W16BIT = 1,
+
+        /** FIFO width is 32-bit. */
+        EDMA3_DRV_W32BIT = 2,
+
+        /** FIFO width is 64-bit. */
+        EDMA3_DRV_W64BIT = 3,
+
+        /** FIFO width is 128-bit. */
+        EDMA3_DRV_W128BIT = 4,
+
+        /** FIFO width is 256-bit. */
+        EDMA3_DRV_W256BIT = 5
+
+} EDMA3_DRV_FifoWidth;
+
+/**
+ * \brief Transfer complete code mode.
+ * Indicates the point at which a transfer is considered completed for
+ * chaining and interrupt generation
+ */
+typedef enum
+{
+    /** A transfer is considered completed after transfer of data */
+    EDMA3_DRV_TCCMODE_NORMAL      = 0,
+
+    /**
+     * A transfer is considered completed after the EDMA3CC submits a TR
+     * to the EDMA3TC. TC may still be transferring data when interrupt/chain
+     * is triggered.
+     */
+    EDMA3_DRV_TCCMODE_EARLY       = 1
+} EDMA3_DRV_TccMode;
+
+/**
+ * \brief Transfer complete interrupt enable.
+ */
+typedef enum
+{
+    /** Transfer complete interrupt is disabled */
+    EDMA3_DRV_TCINTEN_DIS      = 0,
+
+    /**
+     * Transfer complete interrupt is enabled.
+     * When enabled, the interrupt pending register (IPR/IPRH) bit is set on
+     * transfer completion (upon completion of the final TR in the PaRAM set).
+     * The bit (position) set in IPR or IPRH is the TCC value specified. In
+     * order to generate a completion interrupt to the CPU, the corresponding
+     * IER [TCC] / IERH [TCC] bit must be set to 1.
+     */
+    EDMA3_DRV_TCINTEN_EN       = 1
+} EDMA3_DRV_TcintEn;
+
+/**
+ * \brief Intermediate Transfer complete interrupt enable.
+ */
+typedef enum
+{
+    /** Intermediate Transfer complete interrupt is disabled */
+    EDMA3_DRV_ITCINTEN_DIS      = 0,
+
+    /**
+     * Intermediate transfer complete interrupt is enabled.
+     * When enabled, the interrupt pending register (IPR/IPRH) bit is set on
+     * every intermediate transfer completion (upon completion of every
+     * intermediate TR in the PaRAM set, except the final TR in the PaRAM set).
+     * The bit (position) set in IPR or IPRH is the TCC value specified. In
+     * order to generate a completion interrupt to the CPU, the corresponding
+     * IER [TCC] / IERH [TCC] bit must be set to 1.
+     */
+    EDMA3_DRV_ITCINTEN_EN       = 1
+} EDMA3_DRV_ItcintEn;
+
+/**
+ * \brief Transfer complete chaining enable.
+ */
+typedef enum
+{
+    /** Transfer complete chaining is disabled */
+    EDMA3_DRV_TCCHEN_DIS      = 0,
+
+    /**
+     * Transfer complete chaining is enabled.
+     * When enabled, the chained event register (CER/CERH) bit is set on final
+     * chained transfer completion (upon completion of the final / last TR in
+     * the PaRAM set). The bit (position) set in CER or CERH is the TCC value
+     * specified.
+     */
+    EDMA3_DRV_TCCHEN_EN       = 1
+} EDMA3_DRV_TcchEn;
+
+/**
+ * \brief Intermediate Transfer complete chaining enable.
+ */
+typedef enum
+{
+    /** Intermediate Transfer complete chaining is disabled */
+    EDMA3_DRV_ITCCHEN_DIS      = 0,
+
+    /**
+     * Intermediate transfer complete chaining is enabled.
+     * When enabled, the chained event register (CER/CERH) bit is set on every
+     * intermediate chained transfer completion (upon completion of every
+     * intermediate TR in the PaRAM set, except the final TR in the PaRAM set).
+     * The bit (position) set in CER or CERH is the TCC value specified.
+     */
+    EDMA3_DRV_ITCCHEN_EN       = 1
+} EDMA3_DRV_ItcchEn;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_DATASTRUCT
+ @{ */
+
+/**
+ * \brief Structure to be used to configure interrupt generation
+ * and chaining options.
+ */
+typedef struct
+{
+    /** Transfer complete chaining enable */
+    EDMA3_DRV_TcchEn    tcchEn;
+
+    /** Intermediate Transfer complete chaining enable */
+    EDMA3_DRV_ItcchEn   itcchEn;
+
+    /** Transfer complete interrupt enable */
+    EDMA3_DRV_TcintEn   tcintEn;
+
+    /** Intermediate Transfer complete interrupt enable */
+    EDMA3_DRV_ItcintEn  itcintEn;
+} EDMA3_DRV_ChainOptions;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_BASIC
+ @{ */
+
+/**
+ * \brief   Set a particular OPT field in the PaRAM set associated with the
+ *          logical channel 'lCh'.
+ *
+ * This API can be used to set various optional parameters for an EDMA3
+ * transfer. Like enable/disable completion interrupts, enable/disable chaining,
+ * setting the transfer mode (A/AB Sync), setting the FIFO width etc.
+ *
+ * \param   hEdma               [IN]        Handle to the EDMA Driver Instance.
+ * \param   lCh                 [IN]        Logical Channel, bound to which
+ *                                          PaRAM set OPT field needs to be set.
+ * \param   optField            [IN]        The particular field of OPT Word
+ *                                          that needs setting
+ * \param   newOptFieldVal      [IN]        The new OPT field value
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,
+                    uint32_t lCh,
+                    EDMA3_DRV_OptField optField,
+                    uint32_t newOptFieldVal);
+
+/**
+ * \brief   Get a particular OPT field in the PaRAM set associated with the
+ *          logical channel 'lCh'.
+ *
+ * This API can be used to read various optional parameters for an EDMA3
+ * transfer. Like enable/disable completion interrupts, enable/disable chaining,
+ * setting the transfer mode (A/AB Sync), setting the FIFO width etc.
+ *
+ * \param   hEdma               [IN]        Handle to the EDMA Driver Instance.
+ * \param   lCh                 [IN]        Logical Channel, bound to which
+ *                                          PaRAM set OPT field is required.
+ * \param   optField            [IN]        The particular field of OPT Word
+ *                                          that is needed
+ * \param   optFieldVal         [IN/OUT]    Value of the OPT field
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,
+                    uint32_t lCh,
+                    EDMA3_DRV_OptField optField,
+                    uint32_t *optFieldVal);
+
+/**
+ * \brief  DMA source parameters setup
+ *
+ * It is used to program the source address, source side addressing mode
+ * (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.
+ *
+ * In FIFO Addressing mode, memory location must be 32 bytes aligned.
+ *
+ * \param   hEdma       [IN]    Handle to the EDMA Driver Instance
+ * \param   lCh         [IN]    Logical Channel for which the source parameters
+ *                              are to be configured
+ * \param   srcAddr     [IN]    Source address
+ * \param   addrMode    [IN]    Address mode [FIFO or Increment]
+ * \param   fifoWidth   [IN]    Width of FIFO (Valid only if addrMode is FIFO)
+ *                                  -# 0 - 8 bit
+ *                                  -# 1 - 16 bit
+ *                                  -# 2 - 32 bit
+ *                                  -# 3 - 64 bit
+ *                                  -# 4 - 128 bit
+ *                                  -# 5 - 256 bit
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_setSrcParams ( EDMA3_DRV_Handle hEdma,
+                    uint32_t lCh,
+                    uint32_t srcAddr,
+                    EDMA3_DRV_AddrMode addrMode,
+                    EDMA3_DRV_FifoWidth fifoWidth);
+
+/**
+ * \brief  DMA Destination parameters setup
+ *
+ * It is used to program the destination address, destination side addressing
+ * mode (INCR or FIFO) and the FIFO width in case the addressing mode is FIFO.
+ *
+ * In FIFO Addressing mode, memory location must be 32 bytes aligned.
+ *
+ * \param   hEdma       [IN]    Handle to the EDMA Driver Instance
+ * \param   lCh         [IN]    Logical Channel for which the destination
+ *                              parameters are to be configured
+ * \param   destAddr    [IN]    Destination address
+ * \param   addrMode    [IN]    Address mode [FIFO or Increment]
+ * \param   fifoWidth   [IN]    Width of FIFO (Valid only if addrMode is FIFO)
+ *                                  -# 0 - 8 bit
+ *                                  -# 1 - 16 bit
+ *                                  -# 2 - 32 bit
+ *                                  -# 3 - 64 bit
+ *                                  -# 4 - 128 bit
+ *                                  -# 5 - 256 bit
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_setDestParams ( EDMA3_DRV_Handle hEdma,
+                    uint32_t lCh,
+                    uint32_t destAddr,
+                    EDMA3_DRV_AddrMode addrMode,
+                    EDMA3_DRV_FifoWidth fifoWidth );
+
+/**
+ * \brief   DMA source index setup
+ *
+ * It is used to program the source B index and source C index.
+ *
+ * SRCBIDX is a 16-bit signed value (2s complement) used for source address
+ * modification between each array in the 2nd dimension. Valid values for
+ * SRCBIDX are between -32768 and 32767. It provides a byte address offset
+ * from the beginning of the source array to the beginning of the next source
+ * array. It applies to both A-synchronized and AB-synchronized transfers.
+ *
+ * SRCCIDX is a 16-bit signed value (2s complement) used for source address
+ * modification in the 3rd dimension. Valid values for SRCCIDX are between
+ * -32768 and 32767. It provides a byte address offset from the beginning of
+ * the current array (pointed to by SRC address) to the beginning of the first
+ * source array in the next frame. It applies to both A-synchronized and
+ * AB-synchronized transfers. Note that when SRCCIDX is applied, the current
+ * array in an A-synchronized transfer is the last array in the frame, while
+ * the current array in an AB-synchronized transfer is the first array in the
+ * frame.
+ *
+ * \param   hEdma           [IN]            Handle to the EDMA Driver Instance
+ * \param   lCh             [IN]            Logical Channel for which source
+ *                                          indices are to be configured
+ * \param   srcBIdx         [IN]            Source B index
+ * \param   srcCIdx         [IN]            Source C index
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_setSrcIndex ( EDMA3_DRV_Handle hEdma,
+                    uint32_t lCh,
+                    int32_t srcBIdx,
+                    int32_t srcCIdx );
+
+/**
+ * \brief   DMA destination index setup
+ *
+ * It is used to program the destination B index and destination C index.
+ *
+ * DSTBIDX is a 16-bit signed value (2s complement) used for destination
+ * address modification between each array in the 2nd dimension. Valid values
+ * for DSTBIDX are between -32768 and 32767. It provides a byte address offset
+ * from the beginning of the destination array to the beginning of the next
+ * destination array within the current frame. It applies to both
+ * A-synchronized and AB-synchronized transfers.
+ *
+ * DSTCIDX is a 16-bit signed value (2s complement) used for destination address
+ * modification in the 3rd dimension. Valid values are between -32768 and 32767.
+ * It provides a byte address offset from the beginning of the current array
+ * (pointed to by DST address) to the beginning of the first destination array
+ * TR in the next frame. It applies to both A-synchronized and AB-synchronized
+ * transfers. Note that when DSTCIDX is applied, the current array in an
+ * A-synchronized transfer is the last array in the frame, while the current
+ * array in a AB-synchronized transfer is the first array in the frame
+ *
+ * \param   hEdma           [IN]            Handle to the EDMA Driver Instance
+ * \param   lCh             [IN]            Logical Channel for which dest
+ *                                          indices are to be configured
+ * \param   destBIdx        [IN]            Destination B index
+ * \param   destCIdx        [IN]            Destination C index
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result  EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma,
+                    uint32_t lCh,
+                    int32_t destBIdx,
+                    int32_t destCIdx);
+
+/**
+ * \brief       DMA transfer parameters setup
+ *
+ * It is used to specify the various counts (ACNT, BCNT and CCNT), B count
+ * reload and the synchronization type
+ *
+ * ACNT represents the number of bytes within the 1st dimension of a transfer.
+ * ACNT is a 16-bit unsigned value with valid values between 0 and 65535.
+ * Therefore, the maximum number of bytes in an array is 65535 bytes (64K - 1
+ * bytes). ACNT must be greater than or equal to 1 for a TR to be submitted to
+ * EDMA3 Transfer Controller.
+ * An ACNT equal to 0 is considered either a null or dummy transfer. A dummy or
+ * null transfer generates a completion code depending on the settings of the
+ * completion bit fields in OPT.
+
+ * BCNT is a 16-bit unsigned value that specifies the number of arrays of length
+ * ACNT. For normal operation, valid values for BCNT are between 1 and 65535.
+ * Therefore, the maximum number of arrays in a frame is 65535 (64K - 1 arrays).
+ * A BCNT equal to 0 is considered either a null or dummy transfer. A dummy or
+ * null transfer generates a completion code depending on the settings of the
+ * completion bit fields in OPT.
+ *
+ * CCNT is a 16-bit unsigned value that specifies the number of frames in a
+ * block. Valid values for CCNT are between 1 and 65535. Therefore, the maximum
+ * number of frames in a block is 65535 (64K - 1 frames). A CCNT equal to 0 is
+ * considered either a null or dummy transfer. A dummy or null transfer
+ * generates a completion code depending on the settings of the completion bit
+ * fields in OPT. A CCNT value of 0 is considered either a null or dummy
+ * transfer.
+ *
+ * BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the
+ * last array in the 2nd dimension is transferred. This field is only used for
+ * A-synchronized transfers. In this case, the EDMA3CC decrements the BCNT
+ * value by 1 on each TR submission. When BCNT (conceptually) reaches 0, the
+ * EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT
+ * value.
+ * For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the
+ * EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers,
+ * BCNTRLD is not used.
+
+ * \param       hEdma           [IN]    Handle to the EDMA Driver Instance
+ * \param       lCh             [IN]    Logical Channel for which transfer
+ *                                      parameters are to be configured
+ * \param       aCnt            [IN]    Count for 1st Dimension.
+ * \param       bCnt            [IN]    Count for 2nd Dimension.
+ * \param       cCnt            [IN]    Count for 3rd Dimension.
+ * \param       bCntReload      [IN]    Reload value for bCnt.
+ * \param       syncType        [IN]    Transfer synchronization dimension
+ *                                      0: A-synchronized. Each event triggers
+ *                                      the transfer of a single array of
+ *                                      ACNT bytes.
+ *                                      1: AB-synchronized. Each event triggers
+ *                                      the transfer of BCNT arrays of ACNT
+ *                                      bytes.
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_setTransferParams (
+                        EDMA3_DRV_Handle hEdma,
+                        uint32_t lCh,
+                        uint32_t aCnt,
+                        uint32_t bCnt,
+                        uint32_t cCnt,
+                        uint32_t bCntReload,
+                        EDMA3_DRV_SyncType syncType);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
+
+/**
+ * \brief   Chain the two specified channels.
+ *
+ * This API is used to chain a DMA channel to a previously allocated DMA/QDMA
+ * channel.
+ *
+ * Chaining is different from Linking. The EDMA3 link feature reloads the
+ * current channel parameter set with the linked parameter set. The EDMA3
+ * chaining feature does not modify or update any channel parameter set;
+ * it provides a synchronization event (or trigger) to the chained DMA channel,
+ * as soon as the transfer (final or intermediate) completes on the main
+ * DMA/QDMA channel.
+ *
+ * \param   hEdma               [IN]    Handle to the EDMA Driver Instance.
+ *
+ * \param   lCh1                [IN]    DMA/QDMA channel to which a particular
+ *                                      DMA channel will be chained.
+ * \param   lCh2                [IN]    DMA channel which needs to be chained to
+ *                                      the first DMA/QDMA channel.
+ * \param   chainOptions        [IN]    Options such as intermediate interrupts
+ *                                      are required or not, intermediate/final
+ *                                      chaining is enabled or not etc.
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh1 & lCh2 values. It is
+ *          non-re-entrant for same lCh1 & lCh2 values.
+ */
+EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
+                                    uint32_t lCh1,
+                                    uint32_t lCh2,
+                                    const EDMA3_DRV_ChainOptions *chainOptions);
+
+/**
+ * \brief   Unchain the two channels.
+ *
+ * \param   hEdma               [IN]    Handle to the EDMA Driver Instance.
+ * \param   lCh                 [IN]    Channel whose chaining with the other
+ *                                      channel has to be removed.
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma,
+                        uint32_t lCh);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
+
+/**
+ * \brief EDMA Trigger Mode Selection
+ *
+ * Use this enum to select the EDMA trigger mode while enabling
+ * the EDMA transfer
+ */
+typedef enum
+{
+        /**
+         * Set the Trigger mode to Manual .
+         * The CPU manually triggers a transfer by writing a 1 to the
+         * corresponding bit in the event set register (ESR/ESRH).
+         */
+        EDMA3_DRV_TRIG_MODE_MANUAL = 0,
+
+        /**
+         * Set the Trigger mode to QDMA.
+         * A QDMA transfer is triggered when a CPU (or other EDMA3
+         * programmer) writes to the trigger word of the
+         * QDMA channel parameter set (autotriggered) or when the
+         * EDMA3CC performs a link update on a PaRAM
+         * set that has been mapped to a QDMA channel (link triggered).
+         */
+        EDMA3_DRV_TRIG_MODE_QDMA = 1,
+
+        /**
+         * Set the Trigger mode to Event.
+         * Allows for a peripheral, system, or externally-generated
+         * event to trigger a transfer request.
+         */
+        EDMA3_DRV_TRIG_MODE_EVENT = 2,
+
+        /** Used to specify the trigger mode NONE */
+        EDMA3_DRV_TRIG_MODE_NONE = 3
+} EDMA3_DRV_TrigMode;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_BASIC
+ @{ */
+
+/**
+ * \brief  Version information 
+ *
+ * The function is used to get the version information of the EDMA LLD.
+ *
+ * \return      Version Information.
+ */
+uint32_t EDMA3_DRV_getVersion (void);
+
+/**
+ * \brief  Version string querry 
+ *
+ * The function is used to get the version string for the EDMA LLD.
+ *
+ * \return      Version Information.
+ */
+const char* EDMA3_DRV_getVersionStr (void);
+
+/**
+ * \brief       Start EDMA transfer on the specified channel.
+ *
+ * There are multiple ways to trigger an EDMA3 transfer. The triggering mode
+ * option allows choosing from the available triggering modes: Event,
+ * Manual or QDMA.
+ *
+ * In event triggered, a peripheral or an externally generated event triggers
+ * the transfer. This API clears the Secondary Event Register and Event Miss
+ * Register and then enables the DMA channel by writing to the EESR.
+ *
+ * In manual triggered mode, CPU manually triggers a transfer by writing a 1
+ * in the Event Set Register (ESR/ESRH). This API writes to the ESR/ESRH to
+ * start the transfer.
+ *
+ * In QDMA triggered mode, a QDMA transfer is triggered when a CPU (or other
+ * EDMA3 programmer) writes to the trigger word of the QDMA channel PaRAM set
+ * (auto-triggered) or when the EDMA3CC performs a link update on a PaRAM set
+ * that has been mapped to a QDMA channel (link triggered). This API enables
+ * the QDMA channel by writing to the QEESR register.
+ *
+ * \param  hEdma        [IN]    Handle to the EDMA Driver Instance
+ * \param  lCh          [IN]    Channel on which transfer has to be started
+ * \param  trigMode     [IN]    Mode of triggering start of transfer (Manual,
+ *                              QDMA or Event)
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
+                        uint32_t lCh,
+                        EDMA3_DRV_TrigMode trigMode);
+
+/**
+ * \brief Disable DMA transfer on the specified channel
+ *
+ * There are multiple ways by which an EDMA3 transfer could be triggered.
+ * The triggering mode option allows choosing from the available triggering
+ * modes: Event, Manual or QDMA.
+ *
+ * To disable a channel which was previously triggered in manual mode,
+ * this API clears the Secondary Event Register and Event Miss Register,
+ * if set, for the specific DMA channel.
+ *
+ * To disable a channel which was previously triggered in QDMA mode, this
+ * API clears the QDMA Event Enable Register, for the specific QDMA channel.
+ *
+ * To disable a channel which was previously triggered in event mode, this API
+ * clears the Event Enable Register. It also clears Event Register, Secondary
+ * Event Register and Event Miss Register, if set, for the specific DMA channel.
+ *
+ * \param   hEdma       [IN]    Handle to the EDMA Driver Instance
+ * \param   lCh         [IN]    Channel on which transfer has to be stopped
+ * \param   trigMode    [IN]    Mode of triggering start of transfer
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
+                        uint32_t lCh,
+                        EDMA3_DRV_TrigMode trigMode);
+
+/**
+ * \brief Disable the event driven DMA channel or QDMA channel
+ *
+ * This API disables the DMA channel (which was previously triggered in event
+ * mode) by clearing the Event Enable Register; it disables the QDMA channel by
+ * clearing the QDMA Event Enable Register.
+ *
+ * This API should NOT be used for DMA channels which are not mapped to any
+ * hardware events and are used for memory-to-memory copy based transfers. In
+ * case of that, this API returns error.
+ *
+ * \param   hEdma       [IN]    Handle to the EDMA Driver Instance
+ * \param   lCh         [IN]    DMA/QDMA Channel which needs to be disabled
+ * \param   trigMode    [IN]    Mode of triggering start of transfer
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (
+                                               EDMA3_DRV_Handle hEdma,
+                        uint32_t lCh,
+                        EDMA3_DRV_TrigMode trigMode);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
+
+/**
+ * \brief PaRAM Set Entry type
+ *
+ * Use this enum to set or get any of the
+ * 8 DWords(uint32_t) within a Parameter RAM set
+ */
+typedef enum
+{
+    /**
+     * The OPT field (Offset Address 0x0 Bytes)
+     */
+    EDMA3_DRV_PARAM_ENTRY_OPT                       = 0,
+
+    /**
+     * The SRC field (Offset Address 0x4 Bytes)
+     */
+    EDMA3_DRV_PARAM_ENTRY_SRC                       = 1,
+
+    /**
+     * The (ACNT+BCNT) field (Offset Address 0x8 Bytes)
+     */
+    EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT                 = 2,
+
+    /**
+     * The DST field (Offset Address 0xC Bytes)
+     */
+    EDMA3_DRV_PARAM_ENTRY_DST                       = 3,
+
+    /**
+     * The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes)
+     */
+    EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX              = 4,
+
+    /**
+     * The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes)
+     */
+    EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD              = 5,
+
+    /**
+     * The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes)
+     */
+    EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX              = 6,
+
+    /**
+     * The (CCNT+RSVD) field (Offset Address 0x1C Bytes)
+     */
+    EDMA3_DRV_PARAM_ENTRY_CCNT                      = 7
+
+} EDMA3_DRV_PaRAMEntry;
+
+/**
+ * \brief PaRAM Set Field type
+ *
+ * Use this enum to set or get any of the PaRAM set fields
+ */
+typedef enum
+{
+    /** OPT field of PaRAM Set */
+    EDMA3_DRV_PARAM_FIELD_OPT           = 0,
+
+    /**
+     * \brief Starting byte address of Source
+     * For FIFO mode, srcAddr must be a 256-bit aligned address.
+     */
+    EDMA3_DRV_PARAM_FIELD_SRCADDR       = 1,
+
+    /**
+     * \brief Number of bytes in each Array (ACNT)
+     */
+    EDMA3_DRV_PARAM_FIELD_ACNT          = 2,
+
+    /**
+     * \brief Number of Arrays in each Frame (BCNT)
+     */
+    EDMA3_DRV_PARAM_FIELD_BCNT          = 3,
+
+    /**
+     * \brief Starting byte address of destination
+     * For FIFO mode, destAddr must be a 256-bit aligned address.
+     */
+    EDMA3_DRV_PARAM_FIELD_DESTADDR      = 4,
+
+    /**
+     * \brief Index between consec. arrays of a Source Frame (SRCBIDX)
+     * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should
+     * be an even multiple of 32 bytes.
+     */
+    EDMA3_DRV_PARAM_FIELD_SRCBIDX       = 5,
+
+    /**
+     * \brief Index between consec. arrays of a Destination Frame (DSTBIDX)
+     * If DAM is set to 1 (via channelOptions) then destInterArrIndex should
+     * be an even multiple of 32 bytes
+     */
+    EDMA3_DRV_PARAM_FIELD_DESTBIDX      = 6,
+
+    /**
+     * \brief Address for linking (AutoReloading of a PaRAM Set)
+     * This must point to a valid aligned 32-byte PaRAM set
+     * A value of 0xFFFF means no linking
+     * Linking is especially useful for use with ping-pong buffers and
+     * circular buffers
+     */
+    EDMA3_DRV_PARAM_FIELD_LINKADDR      = 7,
+
+    /**
+     * \brief Reload value of the numArrInFrame (BCNT)
+     * Relevant only for A-sync transfers
+     */
+    EDMA3_DRV_PARAM_FIELD_BCNTRELOAD    = 8,
+
+    /**
+     * \brief Index between consecutive frames of a Source Block (SRCCIDX)
+     */
+    EDMA3_DRV_PARAM_FIELD_SRCCIDX       = 9,
+
+    /**
+     * \brief Index between consecutive frames of a Dest Block (DSTCIDX)
+     */
+    EDMA3_DRV_PARAM_FIELD_DESTCIDX      = 10,
+
+    /**
+     * \brief Number of Frames in a block (CCNT)
+     */
+    EDMA3_DRV_PARAM_FIELD_CCNT          = 11
+
+} EDMA3_DRV_PaRAMField;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_DATASTRUCT
+ @{ */
+
+/**
+ * \brief EDMA3 PaRAM Set
+ *
+ * This is a mapping of the EDMA3 PaRAM set provided to the user
+ * for ease of modification of the individual PaRAM words.
+ */
+typedef struct  {
+    /** OPT field of PaRAM Set */
+    volatile uint32_t OPT;
+
+    /**
+     * \brief Starting byte address of Source
+     * For FIFO mode, srcAddr must be a 256-bit aligned address.
+     */
+    volatile uint32_t SRC;
+
+    /**
+     * Number of bytes in each Array (ACNT) (16 bits) and
+     * Number of Arrays in each Frame (BCNT) (16 bits).
+     */
+    volatile uint32_t A_B_CNT;
+
+    /**
+     * \brief Starting byte address of destination
+     * For FIFO mode, destAddr must be a 256-bit aligned address.
+     * i.e. 5 LSBs should be 0.
+     */
+    volatile uint32_t DST;
+
+    /**
+     * Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and
+     * Index between consec. arrays of a Destination Frame (DSTBIDX) (16 bits).
+     *
+     * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should
+     * be an even multiple of 32 bytes.
+     *
+     * If DAM is set to 1 (via channelOptions) then destInterArrIndex should
+     * be an even multiple of 32 bytes
+     */
+    volatile uint32_t SRC_DST_BIDX;
+
+    /**
+     * \brief Address for linking (AutoReloading of a PaRAM Set) (16 bits)
+     * and Reload value of the numArrInFrame (BCNT) (16 bits).
+     *
+     * Link field must point to a valid aligned 32-byte PaRAM set
+     * A value of 0xFFFF means no linking.
+     *
+     * B count reload field is relevant only for A-sync transfers.
+     */
+    volatile uint32_t LINK_BCNTRLD;
+
+    /**
+     * \brief Index between consecutive frames of a Source Block (SRCCIDX)
+     * (16 bits) and Index between consecutive frames of a Dest Block
+     * (DSTCIDX) (16 bits).
+     */
+    volatile uint32_t SRC_DST_CIDX;
+
+    /**
+     * \brief Number of Frames in a block (CCNT) (16 bits).
+     */
+    volatile uint32_t CCNT;
+
+} EDMA3_DRV_ParamentryRegs;
+
+/**
+ * \brief EDMA3 Parameter RAM Set in User Configurable format
+ *
+ * This is a mapping of the EDMA3 PaRAM set provided to the user
+ * for ease of modification of the individual fields
+ */
+#ifndef _BIG_ENDIAN
+/* LITTLE_ENDIAN_MODE */
+typedef struct  {
+        /** OPT field of PaRAM Set */
+        volatile uint32_t opt;
+
+        /**
+         * \brief Starting byte address of Source
+         * For FIFO mode, srcAddr must be a 256-bit aligned address.
+         */
+        volatile uint32_t srcAddr;
+
+        /**
+         * \brief Number of bytes in each Array (ACNT)
+         */
+        volatile uint16_t aCnt;
+
+        /**
+         * \brief Number of Arrays in each Frame (BCNT)
+         */
+        volatile uint16_t bCnt;
+
+        /**
+         * \brief Starting byte address of destination
+         * For FIFO mode, destAddr must be a 256-bit aligned address.
+         * i.e. 5 LSBs should be 0.
+         */
+        volatile uint32_t destAddr;
+
+        /**
+         * \brief Index between consec. arrays of a Source Frame (SRCBIDX)
+         * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should
+         * be an even multiple of 32 bytes.
+         */
+        volatile int16_t  srcBIdx;
+
+        /**
+         * \brief Index between consec. arrays of a Destination Frame (DSTBIDX)
+         * If DAM is set to 1 (via channelOptions) then destInterArrIndex should
+         * be an even multiple of 32 bytes
+         */
+        volatile int16_t  destBIdx;
+
+        /**
+         * \brief Address for linking (AutoReloading of a PaRAM Set)
+         * This must point to a valid aligned 32-byte PaRAM set
+         * A value of 0xFFFF means no linking
+         * Linking is especially useful for use with ping-pong buffers and
+         * circular buffers
+         */
+        volatile uint16_t linkAddr;
+
+        /**
+         * \brief Reload value of the numArrInFrame (BCNT)
+         * Relevant only for A-sync transfers
+         */
+        volatile uint16_t bCntReload;
+
+        /**
+         * \brief Index between consecutive frames of a Source Block (SRCCIDX)
+         */
+        volatile int16_t  srcCIdx;
+
+        /**
+         * \brief Index between consecutive frames of a Dest Block (DSTCIDX)
+         */
+        volatile int16_t  destCIdx;
+
+        /**
+         * \brief Number of Frames in a block (CCNT)
+         */
+        volatile uint16_t cCnt;
+
+        /**
+         * \brief Reserved
+         */
+        volatile int16_t  reserved;
+} EDMA3_DRV_PaRAMRegs;
+#else
+/* BIG_ENDIAN_MODE */
+typedef struct  {
+        /** OPT field of PaRAM Set */
+        volatile uint32_t opt;
+
+        /**
+         * \brief Starting byte address of Source
+         * For FIFO mode, srcAddr must be a 256-bit aligned address.
+         */
+        volatile uint32_t srcAddr;
+
+        /**
+         * \brief Number of Arrays in each Frame (BCNT)
+         */
+        volatile uint16_t bCnt;
+
+        /**
+         * \brief Number of bytes in each Array (ACNT)
+         */
+        volatile uint16_t aCnt;
+
+        /**
+         * \brief Starting byte address of destination
+         * For FIFO mode, destAddr must be a 256-bit aligned address.
+         * i.e. 5 LSBs should be 0.
+         */
+        volatile uint32_t destAddr;
+
+        /**
+         * \brief Index between consec. arrays of a Destination Frame (DSTBIDX)
+         * If DAM is set to 1 (via channelOptions) then destInterArrIndex should
+         * be an even multiple of 32 bytes
+         */
+        volatile int16_t  destBIdx;
+
+        /**
+         * \brief Index between consec. arrays of a Source Frame (SRCBIDX)
+         * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should
+         * be an even multiple of 32 bytes.
+         */
+        volatile int16_t  srcBIdx;
+
+        /**
+         * \brief Reload value of the numArrInFrame (BCNT)
+         * Relevant only for A-sync transfers
+         */
+        volatile uint16_t bCntReload;
+
+        /**
+         * \brief Address for linking (AutoReloading of a PaRAM Set)
+         * This must point to a valid aligned 32-byte PaRAM set
+         * A value of 0xFFFF means no linking
+         * Linking is especially useful for use with ping-pong buffers and
+         * circular buffers
+         */
+        volatile uint16_t linkAddr;
+
+        /**
+         * \brief Index between consecutive frames of a Dest Block (DSTCIDX)
+         */
+        volatile int16_t  destCIdx;
+
+        /**
+         * \brief Index between consecutive frames of a Source Block (SRCCIDX)
+         */
+        volatile int16_t  srcCIdx;
+
+        /**
+         * \brief Reserved
+         */
+        volatile int16_t  reserved;
+
+        /**
+         * \brief Number of Frames in a block (CCNT)
+         */
+        volatile uint16_t cCnt;
+} EDMA3_DRV_PaRAMRegs;
+#endif         /* #ifndef _BIG_ENDIAN */
+
+/**
+ * \brief Event queue priorities setup
+ *
+ * It allows to change the priority of the individual queues and the
+ * priority of the transfer request (TR) associated with the
+ * events queued in the queue.
+ */
+typedef struct
+{
+    /**
+     * \brief Event Queue Priorities
+     */
+    uint32_t evtQPri[EDMA3_MAX_EVT_QUE];
+}EDMA3_DRV_EvtQuePriority;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
+
+/**
+ * \brief  Assign a Trigger Word to the specified QDMA channel
+ *
+ * This API sets the Trigger word for the specific QDMA channel in the QCHMAP
+ * Register. Default QDMA trigger word is CCNT.
+ *
+ * \param   hEdma      [IN]    Handle to the EDMA Instance object
+ * \param   lCh        [IN]    QDMA Channel which needs to be assigned
+ *                             the Trigger Word
+ * \param   trigWord   [IN]    The Trigger Word for the QDMA channel.
+ *                             Trigger Word is the word in the PaRAM
+ *                             Register Set which, when written to by CPU,
+ *                             will start the QDMA transfer automatically.
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma,
+                    uint32_t lCh,
+                    EDMA3_RM_QdmaTrigWord trigWord);
+
+/**
+ * \brief   Copy the user specified PaRAM Set onto the PaRAM Set
+ *          associated with the logical channel (DMA/QDMA/Link).
+ *
+ * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set
+ * associated with the logical channel. OPT field of the PaRAM Set is written
+ * first and the CCNT field is written last.
+ *
+ * Caution: It should be used carefully when programming the QDMA channels whose
+ *          trigger words are not CCNT field.
+ *
+ * \param   hEdma       [IN]  Handle to the EDMA Instance object
+ * \param   lCh         [IN]  Logical Channel for which new PaRAM set is
+ *                            specified
+ * \param   newPaRAM    [IN]  Parameter RAM set to be copied onto existing PaRAM
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_setPaRAM ( EDMA3_DRV_Handle hEdma,
+                        uint32_t lCh,
+                        const EDMA3_DRV_PaRAMRegs *newPaRAM);
+
+/**
+ * \brief   Retrieve existing PaRAM set associated with specified logical
+ *          channel (DMA/QDMA/Link).
+ *
+ * \param   hEdma           [IN]     Handle to the EDMA Instance object
+ * \param   lCh             [IN]     Logical Channel whose PaRAM set is
+ *                                   requested
+ * \param   currPaRAM       [IN/OUT] User gets the existing PaRAM here
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma,
+                    uint32_t lCh,
+                    EDMA3_DRV_PaRAMRegs *currPaRAM);
+
+/**
+ * \brief   Set a particular PaRAM set entry of the specified PaRAM set
+ *
+ *
+ * \param   hEdma       [IN]    Handle to the EDMA Driver Instance
+ * \param   lCh         [IN]    Logical Channel bound to the Parameter RAM set
+ *                              whose specified field needs to be set
+ * \param   paRAMEntry  [IN]    Specify the PaRAM set entry which needs
+ *                              to be set
+ * \param   newPaRAMEntryVal [IN]    The new field setting
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This API should be used while setting the PaRAM set entry
+ *          for QDMA channels. If EDMA3_DRV_setPaRAMField () used,
+ *          it will trigger the QDMA channel before complete
+ *          PaRAM set entry is written. For DMA channels, no such
+ *          constraint is there.
+ *
+ *          This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma,
+                    uint32_t lCh,
+                    EDMA3_DRV_PaRAMEntry paRAMEntry,
+                    uint32_t newPaRAMEntryVal);
+
+/**
+ * \brief   Get a particular PaRAM set entry of the specified PaRAM set
+ *
+ *
+ * \param   hEdma       [IN]    Handle to the EDMA Driver Instance
+ * \param   lCh         [IN]    Logical Channel bound to the Parameter RAM set
+ *                              whose specified field value is needed
+ * \param   paRAMEntry  [IN]    Specify the PaRAM set entry which needs
+ *                              to be obtained
+ * \param   paRAMEntryVal [IN/OUT]  The value of the field is returned here
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma,
+                    uint32_t lCh,
+                    EDMA3_DRV_PaRAMEntry paRAMEntry,
+                    uint32_t *paRAMEntryVal);
+
+/**
+ * \brief   Set a particular PaRAM set field of the specified PaRAM set
+ *
+ *
+ * \param   hEdma               [IN]    Handle to the EDMA Driver Instance
+ * \param   lCh                 [IN]    Logical Channel bound to the PaRAM set
+ *                                      whose specified field needs to be set
+ * \param   paRAMField          [IN]    Specify the PaRAM set field which needs
+ *                                      to be set
+ * \param   newPaRAMFieldVal    [IN]    The new field setting
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This API CANNOT be used while setting the PaRAM set
+ *          field for QDMA channels. It can trigger the QDMA channel before
+ *          complete PaRAM set ENTRY (4-bytes field) is written (for eg, as
+ *          soon one sets the ACNT field for QDMA channel, transfer is started,
+ *          before one modifies the BCNT field). For DMA channels, no such
+ *          constraint is there.
+ *
+ *          This function is re-entrant for unique lCh values. It is non-
+ *          re-entrant for same lCh value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma,
+                    uint32_t lCh,
+                    EDMA3_DRV_PaRAMField paRAMField,
+                    uint32_t newPaRAMFieldVal);
+
+/**
+ * \brief   Get a particular PaRAM set field of the specified PaRAM set
+ *
+ *
+ * \param   hEdma               [IN]    Handle to the EDMA Driver Instance
+ * \param   lCh                 [IN]    Logical Channel bound to the PaRAM set
+ *                                      whose specified field value is needed
+ * \param   paRAMField          [IN]    Specify the PaRAM set field which needs
+ *                                      to be obtained
+ * \param   currPaRAMFieldVal [IN/OUT]  The value of the field is returned here
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma,
+                    uint32_t lCh,
+                    EDMA3_DRV_PaRAMField paRAMField,
+                    uint32_t *currPaRAMFieldVal);
+
+/**
+ * \brief   Sets EDMA TC priority
+ *
+ * User can program the priority of the Event Queues at a system-wide level.
+ * This means that the user can set the priority of an IO initiated by either
+ * of the TCs (Transfer Ctrllers) relative to IO initiated by the other bus
+ * masters on the device (ARM, DSP, USB, etc)
+ *
+ * \param   hEdma           [IN]    Handle to the EDMA Driver Instance
+ * \param   evtQPriObj     [IN]    Priority of the Event Queues
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function disables the global interrupts while modifying
+ *          the global CC Registers, to make it re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma,
+                    const EDMA3_DRV_EvtQuePriority *evtQPriObj);
+
+/**
+ * \brief   Associate Channel to Event Queue
+ *
+ *
+ * \param   hEdma       [IN]     Handle to the EDMA Driver Instance
+ * \param   channelId   [IN]     Logical Channel to which the Event
+ *                               Queue is to be mapped
+ * \param   eventQ      [IN]     The Event Queue which is to be mapped
+ *                               to the DMA channel
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note        There should not be any data transfer going on
+ *              while setting the mapping. Results could be unpredictable.
+ *
+ *              This function disables the global interrupts while modifying
+ *              the global CC Registers, to make it re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle hEdma,
+                    uint32_t channelId,
+                    EDMA3_RM_EventQueue eventQ);
+
+/**
+ * \brief   Get the Event Queue mapped to the specified DMA/QDMA channel.
+ *
+ * \param   hEdma       [IN]     Handle to the EDMA Driver Instance
+ * \param   channelId   [IN]     Logical Channel whose associated
+ *                               Event Queue is needed
+ * \param   mappedEvtQ  [IN/OUT] The Event Queue which is mapped
+ *                               to the DMA/QDMA channel
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma,
+                    uint32_t channelId,
+                    uint32_t *mappedEvtQ);
+
+/**
+ * \brief   Set the Channel Controller (CC) Register value
+ *
+ * \param   hEdma       [IN]     Handle to the EDMA Driver Instance
+ * \param   regOffset   [IN]     CC Register offset whose value needs to be set
+ * \param   newRegValue [IN]     New CC Register Value
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is non re-entrant for users using the same
+ *          EDMA handle i.e. working on the same shadow region.
+ *          Before modifying a register, it tries to acquire a semaphore
+ *          (Driver instance specific), to protect simultaneous
+ *          modification of the same register by two different users.
+ *          After the successful change, it releases the semaphore.
+ *          For users working on different shadow regions, thus different
+ *          EDMA handles, this function is re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,
+                    uint32_t regOffset,
+                    uint32_t newRegValue);
+
+/**
+ * \brief   Get the Channel Controller (CC) Register value
+ *
+ * \param   hEdma       [IN]     Handle to the EDMA Driver Instance
+ * \param   regOffset   [IN]     CC Register offset whose value is needed
+ * \param   regValue    [IN/OUT] CC Register Value
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma,
+                    uint32_t regOffset,
+                    uint32_t *regValue);
+
+/**
+ * \brief   Wait for a transfer completion interrupt to occur and clear it.
+ *
+ * This is a blocking function that returns when the IPR/IPRH bit corresponding
+ * to the tccNo specified, is SET. It clears the corresponding bit while
+ * returning also.
+ *
+ * This function waits for the specific bit indefinitely in a tight loop, with
+ * out any delay in between. USE IT CAUTIOUSLY.
+ *
+ * \param   hEdma       [IN]     Handle to the EDMA Driver Instance
+ * \param   tccNo       [IN]     TCC, specific to which the function
+ *                               waits on a IPR/IPRH bit.
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for different tccNo.
+ */
+EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
+                    uint32_t tccNo);
+
+/**
+ * \brief   Returns the status of a previously initiated transfer.
+ *
+ * This is a non-blocking function that returns the status of a previously
+ * initiated transfer, based on the IPR/IPRH bit. This bit corresponds to
+ * the tccNo specified by the user. It clears the corresponding bit, if SET,
+ * while returning also.
+ *
+ * \param   hEdma       [IN]     Handle to the EDMA Driver Instance
+ * \param   tccNo       [IN]     TCC, specific to which the function
+ *                               checks the status of the IPR/IPRH bit.
+ * \param   tccStatus   [IN/OUT] Status of the transfer is returned here.
+ *                               Returns "TRUE" if the transfer has
+ *                               completed (IPR/IPRH bit SET),
+ *                               "FALSE" if the transfer has not completed
+ *                               successfully (IPR/IPRH bit NOT SET).
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for different tccNo.
+ */
+EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma,
+                    uint32_t tccNo,
+                    uint16_t *tccStatus);
+
+/**
+ * \brief   Get the PaRAM Set Physical Address associated with a logical channel
+ *
+ * This function returns the PaRAM Set Phy Address (unsigned 32 bits).
+ * The returned address could be used by the advanced users to program the
+ * PaRAM Set directly without using any APIs.
+ *
+ * Least significant 16 bits of this address could be used to program
+ * the LINK field in the PaRAM Set.
+ * Users which program the LINK field directly SHOULD use this API
+ * to get the associated PaRAM Set address with the LINK channel.
+ *
+ *
+ * \param   hEdma       [IN]            Handle to the EDMA Driver Instance
+ * \param   lCh         [IN]            Logical Channel for which the PaRAM set
+ *                                      physical address is required
+ * \param   paramPhyAddr [IN/OUT]       PaRAM Set physical address is returned
+ *                                      here.
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr(EDMA3_DRV_Handle hEdma,
+                    uint32_t lCh,
+                    uint32_t *paramPhyAddr);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
+
+/**\enum    EDMA3_DRV_IoctlCmd
+ * \brief   EDMA3 Driver IOCTL commands
+ */
+typedef enum
+{
+    /* Min IOCTL */
+    EDMA3_DRV_IOCTL_MIN_IOCTL = 0,
+
+    /**
+     * PaRAM Sets will be cleared OR will not be cleared
+     * during allocation, depending upon this option.
+     *
+     * For e.g.,
+     * To clear the PaRAM Sets during allocation,
+     * cmdArg = (void *)1;
+     *
+     * To NOT clear the PaRAM Sets during allocation,
+     * cmdArg = (void *)0;
+     *
+     * For all other values, it will return error.
+     *
+     * By default, PaRAM Sets will be cleared during allocation.
+     * Note: Since this enum can change the behavior how the resources are
+     * initialized during their allocation, user is adviced to not use this
+     * command while allocating the resources. User should first change the
+     * behavior of resources' initialization and then should use start
+     * allocating resources.
+     */
+    EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION,
+
+    /**
+     * To check whether PaRAM Sets will be cleared or not
+     * during allocation.
+     * If the value read is '1', it means that PaRAM Sets are getting cleared
+     * during allocation.
+     * If the value read is '0', it means that PaRAM Sets are NOT getting cleared
+     * during allocation.
+     * For e.g.,
+     * uint16_t isParamClearingDone;
+     * cmdArg = &paramClearingRequired;
+     */
+    EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION,
+
+    /* Max IOCTLs */
+    EDMA3_DRV_IOCTL_MAX_IOCTL
+} EDMA3_DRV_IoctlCmd;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
+
+/**
+ *  \brief EDMA3 Driver IOCTL
+ *
+ *  This function provides IOCTL functionality for EDMA3 Driver.
+ *
+ *  \param   hEdma          [IN]        Handle to the EDMA Driver Instance
+ *  \param  cmd             [IN]        IOCTL command to be performed
+ *  \param  cmdArg          [IN/OUT]    IOCTL command argument (if any)
+ *  \param  param           [IN/OUT]    Device/Cmd specific argument
+ *
+ *  \return EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note For 'EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant.
+ * For 'EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for
+ * different EDMA3 Driver Instances (handles).
+ */
+EDMA3_DRV_Result EDMA3_DRV_Ioctl(
+                      EDMA3_DRV_Handle       hEdma,
+                      EDMA3_DRV_IoctlCmd     cmd,
+                      void                  *cmdArg,
+                      void                  *param
+                     );
+
+/**
+ * \brief      Return the previously opened EDMA3 Driver Instance handle
+ *
+ * This API is used to return the previously opened EDMA3 Driver's
+ * Instance Handle (region specific), which could be used to call other
+ * EDMA3 Driver APIs. Since EDMA3 Driver does not allow multiple instances,
+ * for a single shadow region, this API is provided. This API is meant
+ * for users who DO NOT want to / could not open a new Driver Instance and
+ * hence re-use the existing Driver Instance to allocate EDMA3 resources
+ * and use various other EDMA3 Driver APIs.
+ *
+ * In case the Driver Instance is not yet opened, NULL is returned as the
+ * function return value whereas EDMA3_DRV_E_INST_NOT_OPENED is returned
+ * in the errorCode.
+ *
+ * \param   phyCtrllerInstId    [IN]    EDMA3 Controller Instance Id (Hardware
+ *                                      instance id, starting from 0).
+ * \param   regionId                   [IN]    Shadow Region id for which the previously
+ *                                                                             opened driver's instance handle is
+ *                                                                             required.
+ * \param   errorCode           [OUT]   Error code while returning Driver Instance
+ *                                                                             Handle.
+ *
+ * \return EDMA3_DRV_Handle : If successful, this API will return the
+ *                            driver's instance handle.
+ *
+ * \note    1) This API returns the previously opened EDMA3 Driver's Instance
+ *             handle. The instance, if exists, could have been opened by some other
+ *             user (most probably) or may be by the same user calling this API. If
+ *             it was opened by some other user, then that user can very well close
+ *             this instance anytime, without even knowing that the same instance
+ *             handle is being used by other users as well. In that case, the
+ *             handle becomes INVALID and user has to open a valid driver
+ *             instance for his/her use.
+ *
+ *                     2) This function is re-entrant.
+ */
+EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(uint32_t phyCtrllerInstId,
+                                                               EDMA3_RM_RegionId regionId,
+                                                               EDMA3_DRV_Result *errorCode);
+
+/**
+ * \brief   Registers a transfer completion handler for a specific DMA/QDMA
+ *                     channel
+ *
+ * This function registers a non-NULL callback function for a specific DMA or QDMA
+ * channel and enables the completion interrupt for the TCC associated with
+ * the underlying channel in the IER/IERH register. It also sets the DRAE/DRAEH
+ * register for the TCC associated with the specified DMA/QDMA channel. If user
+ * enables the transfer completion interrupts (intermediate or final) in the OPT
+ * field of the associated PaRAM Set, the registered callback function will be
+ * called by the EDMA3 Resource Manager.
+ *
+ * If a call-back function is already registered for the channel, the API fails
+ * with the error code EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED.
+ *
+ * \param  hEdma               [IN]    Handle to the EDMA Driver Instance.
+ * \param  channelId           [IN]    DMA/QDMA channel for which the callback
+ *                                                                             function needs to be registered.
+ * \param   tccCb               [IN]    The callback function to be registered.
+ * \param   cbData              [IN]    Callback data to be passed while calling
+ *                                      the callback function.
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique channelId values. It is non-
+ *          re-entrant for same channelId value.
+ */
+EDMA3_DRV_Result EDMA3_DRV_registerTccCb(EDMA3_DRV_Handle hEdma,
+                    const uint32_t channelId,
+                    EDMA3_RM_TccCallback tccCb,
+                    void *cbData);
+
+/**
+ * \brief   Un-register the previously registered callback function against a
+ *          DMA/QDMA channel.
+ *
+ * This function un-registers the previously registered callback function for
+ * the DMA/QDMA channel by removing any stored callback function. Moreover, it
+ * clears the:
+ *             Interrupt Enable Register (IER/IERH) by writing to the IECR/IECRH
+ *                     register, for the TCC associated with that particular channel,
+ *             DRA/DRAEH register for the TCC associated with the specified DMA/QDMA
+ *                     channel
+ *
+ * \param  hEdma               [IN]    Handle to the EDMA Driver Instance.
+ * \param  channelId           [IN]    DMA/QDMA channel for which the callback
+ *                                                                             function needs to be un-registered.
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique channelId. It is
+ *                     non-re-entrant for same channelId.
+ */
+EDMA3_DRV_Result EDMA3_DRV_unregisterTccCb(EDMA3_DRV_Handle hEdma,
+                    const uint32_t channelId);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_ENUM
+ @{ */
+
+/**\enum    EDMA3_DRV_Tc_Err
+ * \brief   TC Error Enablers
+ *
+ * Use this enum to enable/disable the specific EDMA3 Transfer Controller
+ * Interrupts.
+ */
+typedef enum
+{
+       /**
+        * Interrupt disable for bus error
+        */
+       EDMA3_DRV_TC_ERR_BUSERR_DIS = 0,
+
+       /**
+        * Interrupt enable for bus error
+        */
+       EDMA3_DRV_TC_ERR_BUSERR_EN,
+
+       /**
+        * Interrupt disable for transfer request error
+        */
+       EDMA3_DRV_TC_ERR_TRERR_DIS,
+
+       /**
+        * Interrupt enable for transfer request error
+        */
+       EDMA3_DRV_TC_ERR_TRERR_EN,
+
+       /**
+        * Interrupt disable for MMR address error
+        */
+       EDMA3_DRV_TC_ERR_MMRAERR_DIS,
+
+       /**
+        * Interrupt enable for MMR address error
+        */
+       EDMA3_DRV_TC_ERR_MMRAERR_EN,
+
+       /**
+        * Disable all TC error interrupts
+        */
+       EDMA3_DRV_TC_ERR_DIS,
+
+       /**
+        * Enable all TC error interrupts
+        */
+       EDMA3_DRV_TC_ERR_EN
+} EDMA3_DRV_Tc_Err;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
+
+/**
+ * \brief   Enable/disable specific EDMA3 Transfer Controller Interrupts
+ *
+ * This function allows one to enable/disable specific EDMA3 Transfer Controller
+ * Interrupts. Since these interrupts don't get enabled by default, this API can
+ * be used to achieve the same.
+ *
+ * \param phyCtrllerInstId  [IN]    EDMA3 Controller Instance Id
+ *                                 (Hardware instance id, starting from 0).
+ * \param tcId                         [IN]    Transfer Controller Id. It starts from 0
+ *                                                                     for each EDMA3 hardware and can go upto
+ *                                                                     (TCs available on EDMA3 Hardware - 1).
+ * \param tcErr                        [IN]    TC Error Interrupts which need to be
+ *                                                                     enabled/disabled.
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error code
+ *
+ * \note    This function is re-entrant for unique combination of EDMA3 hw and
+ *                     TC. It is non-re-entrant for same combination.
+ */
+EDMA3_DRV_Result EDMA3_DRV_setTcErrorInt(uint32_t phyCtrllerInstId,
+                                       uint32_t tcId,
+                                       EDMA3_DRV_Tc_Err tcErr);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_SYMBOL_DEFINE
+ @{ */
+
+/**
+ * \brief Channel status defines
+ * These defines suggest the current state of the DMA / QDMA channel. They
+ * are used while returning the channel status from EDMA3_DRV_getChannelStatus().
+ */
+/** Channel is clean; no pending event, completion interrupt and event miss interrupt */
+#define EDMA3_DRV_CHANNEL_CLEAN                                0x0000u
+/** Pending event is detected on the DMA channel */
+#define EDMA3_DRV_CHANNEL_EVENT_PENDING                0x0001u
+/** Transfer completion interrupt is detected on the DMA/QDMA channel */
+#define EDMA3_DRV_CHANNEL_XFER_COMPLETE                0x0002u
+/** Event miss error interrupt is detected on the DMA/QDMA channel */
+#define EDMA3_DRV_CHANNEL_ERR                          0x0004u
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_DRV_FUNCTION_ADVANCED
+ @{ */
+
+/**
+ * \brief   Get the current status of the DMA/QDMA channel
+ *
+ * This function returns the current status of the specific DMA/QDMA channel.
+ * For a DMA channel, it checks whether an event is pending in ER, transfer
+ * completion interrupt is pending in IPR and event miss error interrupt is
+ * pending in EMR or not. For a QDMA channel, it checks whether a transfer
+ * completion interrupt is pending in IPR and event miss error interrupt is
+ * pending in QEMR or not.
+ *
+ * \param  hEdma               [IN]    Handle to the EDMA Driver Instance.
+ * \param  lCh                         [IN]    DMA/QDMA channel for which the current
+ *                                                                             status is required.
+ * \param  lchStatus           [IN/OUT]Status of the channel. Defines mentioned
+ *                                                                             above are used (and may be combined) to
+ *                                                                             return the actual status.
+ *
+ * \return  EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_getChannelStatus(EDMA3_DRV_Handle hEdma,
+                        uint32_t lCh, uint32_t *lchStatus);
+
+
+/**
+ * \brief  Associates a link channel and a TCC
+ *
+ * This API is used to map a TCC to a LINK channel. It should be used with LINK
+ * channels ONLY else it will fail. It will copy the TCC code in the OPT field
+ * of the param set associated with the link channel.
+ *
+ * \param   hEdma           [IN]    Handle to the EDMA Driver Instance.
+ * \param   linkCh          [IN]    Link Channel to which a particular TCC
+ *                                  needs to be mapped.
+ * \param   tcc             [IN]    TCC which needs to be mapped.
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique linkCh values. It is
+ *          non-re-entrant for same linkCh values.
+ */
+EDMA3_DRV_Result EDMA3_DRV_mapTccLinkCh (EDMA3_DRV_Handle hEdma,
+                                                uint32_t linkCh,
+                                                uint32_t tcc);
+
+#define EDMA3_DRV_MAX_XBAR_EVENTS (63u)
+
+/**\struct  EDMA3_DRV_GblXbarToChanConfigParams
+ * \brief   Init-time Configuration structure for EDMA3
+ * controller, to provide Global SoC specific Information.
+ *
+ * This configuration structure is used to specify the EDMA3 Driver
+ * global settings, specific to the SoC. 
+ * This configuraion structure provides the details of the mapping of cross bar 
+ * events to available channels.
+ * This configuration information is SoC specific and could be provided by the
+ * user at run-time while creating the EDMA3 Driver Object, using API
+ * EDMA3_DRV_initXbarEventMap. In case user doesn't provide it, 
+ * this information could be taken from the SoC specific configuration 
+ * file edma3_<SOC_NAME>_cfg.c, incase it is available.
+ */
+typedef struct  {
+    /**
+     * \brief Mapping from DMA channels to Hardware Events
+     *
+     * Each element in this array corresponds to one cross bar event and tells 
+     * whether this event is mapped to any DMA channel. That is whether any
+     * free or unused DMA channel can be mapped to this event.
+     * -1 means the cross bar event is not mapped to any DMA channel; 
+     * Any number from 0 to 63 means this event is mapped to specified channel.
+     * All channels need not be mapped, some can be free also.
+     * For the cross bar event mapped to DMA channel, appropriate Control Config 
+     * register of TPCC event mux register should be configured.
+     */
+    int32_t        dmaMapXbarToChan [EDMA3_DRV_MAX_XBAR_EVENTS];
+    } EDMA3_DRV_GblXbarToChanConfigParams;
+
+
+/**
+ * \brief  Associates cross bar mapped event to channel
+ *
+ * This function have to be defined in the configuration file. 
+ * This function will be called only if the channel requested for is beyond the
+ * maximum number of channels.
+ * This function should read from the global cross bar mapped configuration 
+ * data structure and return the mapped channel number to this event.
+ *
+ * \param   eventNum            [IN]    Event number
+ * \param   chanNum             [IN/OUT]Return the channel number to which the 
+ *                                      request event is mapped to.
+ * \param   edmaGblXbarConfig   [IN]    This is the configuration data structure
+ *                                      for mapping the events to the channel
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique event values. It is
+ *          non-re-entrant for same event values.
+ */
+typedef EDMA3_DRV_Result (*EDMA3_DRV_mapXbarEvtToChan) (uint32_t eventNum,
+                 uint32_t *chanNum,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);
+
+/**
+ * \brief  Writes to the cross bar mapped event to channel to system 
+ *         configuration register
+ *
+ * This function have to be defined in the configuration file. 
+ * This function will be called only if the event number requested for is 
+ * beyond the maximum number of channels and if any channel is allocated to this 
+ * event.
+ * This function should read the cross bar mapped event number and write the 
+ * allocated channel number in Control Config Event Mux registers.
+ *
+ * \param   eventNum            [IN]    Event number
+ * \param   chanNum             [IN/OUT]Return the channel number to which the 
+ *                                      request event is mapped to.
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function is re-entrant for unique event values. It is
+ *          non-re-entrant for same event values.
+ */
+typedef EDMA3_DRV_Result (*EDMA3_DRV_xbarConfigScr) (uint32_t eventNum,
+                                             uint32_t chanNum);
+
+/**
+ * \brief  Initialize the cross bar mapped event to channel function
+ *
+ * This API provides interface to associate the cross bar mapped event to edma 
+ * channel in the driver. 
+ * This function will called by the application during initilization.
+ * User could pass the application specific configuration structure
+ * during init-time. In case user doesn't provide it, this information could
+ * be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c,
+ * in case it is available.
+ * \param   hEdma               [IN]    Handle to the EDMA Driver Instance.
+ * \param   edmaGblXbarConfig   [IN]    This is the configuration data structure
+ *                                      for mapping the events to the channel
+ * \param   mapXbarEvtFunc      [IN]    This is the user defined function for 
+ *                                      mapping the cross bar event to channel.
+ *
+ * \return      EDMA3_DRV_SOK or EDMA3_DRV Error Code
+ *
+ * \note    This function disables the global interrupts (by calling API
+ *          edma3OsProtectEntry with protection level
+ *          EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data
+ *          structures, to make it re-entrant.
+ */
+EDMA3_DRV_Result EDMA3_DRV_initXbarEventMap (EDMA3_DRV_Handle hEdma,
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig,
+                 EDMA3_DRV_mapXbarEvtToChan mapXbarEvtFunc,
+                 EDMA3_DRV_xbarConfigScr configXbarScr);
+
+
+                                                
+/**
+@}
+*/
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif         /* _EDMA3_DRV_H_ */
diff --git a/debian/edma3/usr/include/edma3_rm.h b/debian/edma3/usr/include/edma3_rm.h
new file mode 100644 (file)
index 0000000..c431427
--- /dev/null
@@ -0,0 +1,2293 @@
+/*
+ * edma3_rm.h
+ *
+ * EDMA3 Controller Resource Manager Interface
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/** @defgroup EDMA3_LLD_RM_API EDMA3 Resource Manager
+ *
+ * @section Introduction
+ *
+ * @subsection xxx Overview
+ *  EDMA3 Resource Manager is a TI mandated library for all EDMA3 peripheral
+ * users to acquire and configure EDMA3 hardware resources (DMA/QDMA channels,
+ * PaRAM Sets, TCCs etc.) and DMA Interrupt Service Routines.
+ */
+
+#ifndef _EDMA3_RM_H_
+#define _EDMA3_RM_H_
+
+#include <stdint.h>
+/** Include common header file */
+#include <ti/sdo/edma3/rm/edma3_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+@defgroup EDMA3_LLD_RM_SYMBOL  EDMA3 Resource Manager Symbols
+@ingroup EDMA3_LLD_RM_API
+*/
+/**
+@defgroup EDMA3_LLD_RM_DATASTRUCT  EDMA3 Resource Manager Data Structures
+@ingroup EDMA3_LLD_RM_API
+*/
+/**
+@defgroup EDMA3_LLD_RM_FUNCTION  EDMA3 Resource Manager APIs
+@ingroup EDMA3_LLD_RM_API
+*/
+
+/**
+@defgroup EDMA3_LLD_RM_SYMBOL_DEFINE  EDMA3 Resource Manager Defines
+@ingroup EDMA3_LLD_RM_SYMBOL
+*/
+/**
+@defgroup EDMA3_LLD_RM_SYMBOL_ENUM  EDMA3 Resource Manager Enums
+@ingroup EDMA3_LLD_RM_SYMBOL
+*/
+/**
+@defgroup EDMA3_LLD_RM_SYMBOL_TYPEDEF  EDMA3 Resource Manager Typedefs
+@ingroup EDMA3_LLD_RM_SYMBOL
+*/
+
+/**
+@defgroup EDMA3_LLD_RM_FUNCTION_INIT  EDMA3 Resource Manager Initialization APIs
+@ingroup EDMA3_LLD_RM_FUNCTION
+*/
+/**
+@defgroup EDMA3_LLD_RM_FUNCTION_BASIC  EDMA3 Resource Manager Basic APIs
+@ingroup EDMA3_LLD_RM_FUNCTION
+*/
+/**
+@defgroup EDMA3_LLD_RM_FUNCTION_ADVANCED  EDMA3 Resource Manager Advanced APIs
+@ingroup EDMA3_LLD_RM_FUNCTION
+*/
+
+/** @addtogroup EDMA3_LLD_RM_SYMBOL_ENUM
+ @{ */
+
+/**\enum    EDMA3_RM_TccStatus
+ * \brief   This enum defines the channel specific status codes of
+ * an EDMA3 transfer. It is returned while calling the channel
+ * specific callback function to tell the status.
+ */
+typedef enum
+{
+    /**
+     * DMA Transfer successfully completed (true completion mode)
+     * or submitted to the TC (early completion mode).
+     */
+    EDMA3_RM_XFER_COMPLETE      = 1,
+
+    /** Channel Controller has reported an error */
+    /**
+     * DMA missed events:- for all 64 DMA channels.
+     * These get latched in the event missed registers (EMR/EMRH).
+     */
+    EDMA3_RM_E_CC_DMA_EVT_MISS = 2,
+
+    /**
+     * QDMA missed events:- for all QDMA channels.
+     * These get latched in the QDMA event missed register (QEMR).
+     */
+    EDMA3_RM_E_CC_QDMA_EVT_MISS = 3
+
+} EDMA3_RM_TccStatus;
+
+/**\enum    EDMA3_RM_GlobalError
+ * \brief   This enum defines the global (not specific to any channel)
+ * error codes of completion of an EDMA3 transfer.
+ */
+typedef enum
+{
+    /**
+     * Threshold exceed:- for all event queues.
+     * These get latched in EDMA3CC error register (CCERR).
+     * This error has a direct relation with the setting of
+     * EDMA3_RM_GblConfigParams.evtQueueWaterMarkLvl
+     */
+    EDMA3_RM_E_CC_QUE_THRES_EXCEED            = 1,
+
+    /**
+     * TCC error:- for outstanding transfer requests expected to return
+     * completion code (TCCHEN or TCINTEN bit in OPT is set to 1) exceeding
+     * the maximum limit of 63. This also gets latched in the CCERR.
+     */
+    EDMA3_RM_E_CC_TCC                           = 2,
+
+    /** Transfer Controller has reported an error */
+    /**
+     * Detection of a Read error signaled by the source or destination address
+     */
+    EDMA3_RM_E_TC_MEM_LOCATION_READ_ERROR      = 3,
+
+    /**
+     * Detection of a Write error signaled by the source or destination address
+     */
+    EDMA3_RM_E_TC_MEM_LOCATION_WRITE_ERROR     = 4,
+
+    /**
+     * Attempt to read or write to an invalid address in the configuration
+     * memory map.
+     */
+    EDMA3_RM_E_TC_INVALID_ADDR                 = 5,
+
+    /**
+     * Detection of a FIFO mode TR violating the FIFO mode transfer rules
+     * (the source/destination addresses and source/destination indexes must
+     * be aligned to 32 bytes).
+     */
+    EDMA3_RM_E_TC_TR_ERROR                     = 6
+} EDMA3_RM_GlobalError;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_SYMBOL_TYPEDEF
+ @{ */
+
+/**
+ * \brief Global Error callback - caters to module events like bus error etc
+ * which are not channel specific. Runs in ISR context.
+ *
+ * gblerrData is application provided data when open'ing the Resource Manager.
+ */
+typedef void (* EDMA3_RM_GblErrCallback)(EDMA3_RM_GlobalError deviceStatus,
+                                            uint32_t          instanceId,
+                                            void              *gblerrData);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_DATASTRUCT
+ @{ */
+
+/**\struct  EDMA3_RM_GblErrCallbackParams
+ * \brief   Global Error Callback parameters
+ *
+ * Consists of the Callback function and the data to be passed to it.
+ */
+typedef struct {
+        /**
+         * Instance wide callback function to catch non-channel specific errors.
+         */
+        EDMA3_RM_GblErrCallback gblerrCb;
+
+        /** Application data to be passed back to the Global Error callback */
+        void *gblerrData;
+
+} EDMA3_RM_GblErrCallbackParams;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_SYMBOL_TYPEDEF
+ @{ */
+
+/**
+ * \brief TCC callback - caters to channel-specific events like
+ * "Event Miss Error" or "Transfer Complete". Runs in ISR context.
+ *
+ * appData is passed by the application during Register'ing of
+ * TCC Callback function.
+ */
+typedef void (* EDMA3_RM_TccCallback)(uint32_t tcc,
+                    EDMA3_RM_TccStatus status,
+                    void *appData);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_SYMBOL_DEFINE
+ @{ */
+
+/**\def     EDMA3_RM_RES_ANY
+ * \brief   Used to specify any available Resource Id (EDMA3_RM_ResDesc.resId)
+ */
+#define EDMA3_RM_RES_ANY            (1010u)
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_SYMBOL_ENUM
+ @{ */
+
+/**\enum    EDMA3_RM_ResType
+ * \brief   EDMA3 Resource Type
+ */
+typedef enum
+{
+    /** DMA Channel resource */
+    EDMA3_RM_RES_DMA_CHANNEL        = 1,
+
+    /** QDMA Channel resource*/
+    EDMA3_RM_RES_QDMA_CHANNEL       = 2,
+
+    /** TCC resource*/
+    EDMA3_RM_RES_TCC                = 3,
+
+    /** Parameter RAM Set resource*/
+    EDMA3_RM_RES_PARAM_SET          = 4
+
+} EDMA3_RM_ResType;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_DATASTRUCT
+ @{ */
+
+/**\struct  EDMA3_RM_ResDesc
+ * \brief   Handle to a Resource.
+ */
+typedef struct
+{
+    /** Resource Id */
+    /**
+     * Range of resId values :
+     * As an example, for resource Type = EDMA3_RM_RES_DMA_CHANNEL,
+     * resId can take values from 0 to EDMA3_MAX_DMA_CH
+     * Or
+     * resId can take the value EDMA3_RM_RES_ANY.
+     */
+    uint32_t resId;
+
+    /** Resource Type */
+    EDMA3_RM_ResType type;
+} EDMA3_RM_ResDesc;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_FUNCTION_BASIC
+ @{ */
+
+/**
+ * \brief   Registers a transfer completion handler for a specific DMA/QDMA
+ *                     channel
+ *
+ * This function registers a non-NULL callback function for a specific DMA or QDMA
+ * channel and enables the completion interrupt for the TCC associated with
+ * the underlying channel in the IER/IERH register. It also sets the DRAE/DRAEH
+ * register for the TCC associated with the specified DMA/QDMA channel. If user
+ * enables the transfer completion interrupts (intermediate or final) in the OPT
+ * field of the associated PaRAM Set, the registered callback function will be
+ * called by the EDMA3 Resource Manager.
+ *
+ * If a call-back function is already registered for the channel, the API fails
+ * with the error code EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED.
+ *
+ * \param   hEdmaResMgr         [IN]    Handle to the previously opened
+ *                                      EDMA3 Resource Manager Instance
+ * \param   channelObj          [IN]    Channel ID and type (DMA or QDMA
+ *                                      Channel), allocated earlier, and
+ *                                      corresponding to which a callback
+ *                                      function needs to be registered
+ *                                      against the associated TCC.
+ * \param   tcc                 [IN]    TCC against which the handler needs to
+ *                                      be registered.
+ * \param   tccCb               [IN]    The Callback function to be registered
+ *                                      against the TCC.
+ * \param   cbData              [IN]    Callback data to be passed while calling
+ *                                      the callback function.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function is re-entrant for unique tcc values. It is non-
+ *          re-entrant for same tcc value.
+ */
+EDMA3_RM_Result EDMA3_RM_registerTccCb(EDMA3_RM_Handle hEdmaResMgr,
+                    const EDMA3_RM_ResDesc *channelObj,
+                    uint32_t             tcc,
+                    EDMA3_RM_TccCallback tccCb,
+                    void *cbData);
+
+/**
+ * \brief   Unregister the previously registered callback function against a
+ *          DMA/QDMA channel.
+ *
+ * This function un-registers the previously registered callback function for
+ * the DMA/QDMA channel by removing any stored callback function. Moreover, it
+ * clears the:
+ *             Interrupt Enable Register (IER/IERH) by writing to the IECR/IECRH
+ *                     register, for the TCC associated with that particular channel,
+ *             DRA/DRAEH register for the TCC associated with the specified DMA/QDMA
+ *                     channel
+ *
+ * \param   hEdmaResMgr         [IN]    Handle to the previously opened
+ *                                      EDMA3 Resource Manager Instance
+ * \param   channelObj          [IN]    Channel ID and type, allocated earlier
+ *                                      (DMA or QDMA Channel ONLY), and
+ *                                      corresponding to which a TCC is there.
+ *                                      Against that TCC, the callback needs
+ *                                      to be un-registered.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code.
+ *
+ * \note    This function is re-entrant for unique (channelObj->type +
+ *          channelObj->resId) combination. It is non-re-entrant for same
+ *          channelObj Resource.
+ */
+EDMA3_RM_Result EDMA3_RM_unregisterTccCb(EDMA3_RM_Handle hEdmaResMgr,
+                    const EDMA3_RM_ResDesc *channelObj);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_SYMBOL_DEFINE
+ @{ */
+
+/** Resource Manager Error Codes base define */
+#define EDMA3_RM_E_BASE                             (-155)
+
+/**
+ * Resource Manager Object Not Deleted yet.
+ * So the object cannot be created.
+ */
+#define EDMA3_RM_E_OBJ_NOT_DELETED                  (EDMA3_RM_E_BASE)
+
+/**
+ * Resource Manager Object Not Closed yet.
+ * So the object cannot be deleted.
+ */
+#define EDMA3_RM_E_OBJ_NOT_CLOSED                  (EDMA3_RM_E_BASE-1)
+
+/**
+ * Resource Manager Object Not Opened yet
+ * So the object cannot be closed.
+ */
+#define EDMA3_RM_E_OBJ_NOT_OPENED                  (EDMA3_RM_E_BASE-2)
+
+/** Invalid Parameter passed to API */
+#define EDMA3_RM_E_INVALID_PARAM                   (EDMA3_RM_E_BASE-3)
+
+/** Resource requested for freeing is already free */
+#define EDMA3_RM_E_RES_ALREADY_FREE                (EDMA3_RM_E_BASE-4)
+
+/** Resource requested for allocation/freeing is not owned */
+#define EDMA3_RM_E_RES_NOT_OWNED                   (EDMA3_RM_E_BASE-5)
+
+/** Resource is not available */
+#define EDMA3_RM_E_SPECIFIED_RES_NOT_AVAILABLE     (EDMA3_RM_E_BASE-6)
+
+/** No Resource of specified type is available */
+#define EDMA3_RM_E_ALL_RES_NOT_AVAILABLE           (EDMA3_RM_E_BASE-7)
+
+/** Invalid State of EDMA3 RM Obj */
+#define EDMA3_RM_E_INVALID_STATE                   (EDMA3_RM_E_BASE-8)
+
+/** Maximum no of Res Mgr Instances already Opened */
+#define EDMA3_RM_E_MAX_RM_INST_OPENED              (EDMA3_RM_E_BASE-9)
+
+/**
+ * More than one Res Mgr Master Instance NOT supported.
+ * Only 1 master can exist.
+ */
+#define EDMA3_RM_E_RM_MASTER_ALREADY_EXISTS         (EDMA3_RM_E_BASE-10)
+
+/** Callback function already registered. */
+#define EDMA3_RM_E_CALLBACK_ALREADY_REGISTERED      (EDMA3_RM_E_BASE-11)
+
+/** Semaphore related error */
+#define EDMA3_RM_E_SEMAPHORE                        (EDMA3_RM_E_BASE-12)
+
+/** Hardware feature NOT supported */
+#define EDMA3_RM_E_FEATURE_UNSUPPORTED                        (EDMA3_RM_E_BASE-13)
+
+/** EDMA3 Resource NOT allocated */
+#define EDMA3_RM_E_RES_NOT_ALLOCATED                        (EDMA3_RM_E_BASE-14)
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_SYMBOL_TYPEDEF
+ @{ */
+
+/**\typedef     EDMA3_RM_RegionId
+ * \brief       EDMA3 Region Id
+ *
+ * Use this to assign channels/PaRAM sets/TCCs to a particular Region.
+ */
+typedef uint32_t EDMA3_RM_RegionId;
+
+/**\typedef     EDMA3_RM_EventQueue
+ * \brief       EDMA3 Event Queue assignment
+ *
+ * There can be 8 Event Queues.  Either of them can be assigned
+ * to a DMA/QDMA channel using this.
+ *
+ */
+typedef uint32_t EDMA3_RM_EventQueue;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_DATASTRUCT
+ @{ */
+
+/**\struct  EDMA3_RM_GblConfigParams
+ * \brief   Init-time Configuration structure for EDMA3
+ * controller, to provide Global SoC specific Information.
+ *
+ * This configuration structure is used to specify the EDMA3 Resource Manager
+ * global settings, specific to the SoC. For e.g. number of DMA/QDMA channels,
+ * number of PaRAM sets, TCCs, event queues, transfer controllers, base
+ * addresses of CC global registers and TC registers, interrupt number for
+ * EDMA3 transfer completion, CC error, event queues' priority, watermark
+ * threshold level etc.
+ * This configuration information is SoC specific and could be provided by the
+ * user at run-time while creating the EDMA3 RM Object, using API
+ * EDMA3_RM_create. In case user doesn't provide it, this information could be
+ * taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c, in
+ * case it is available.
+ */
+typedef struct  {
+    /** Number of DMA Channels supported by the underlying EDMA3 Controller. */
+    uint32_t        numDmaChannels;
+
+    /** Number of QDMA Channels supported by the underlying EDMA3 Controller */
+    uint32_t        numQdmaChannels;
+
+    /**
+     * Number of Interrupt Channels supported by the underlying EDMA3
+     * Controller
+     */
+    uint32_t        numTccs;
+
+    /** Number of PaRAM Sets supported by the underlying EDMA3 Controller */
+    uint32_t        numPaRAMSets;
+
+    /** Number of Event Queues in the underlying EDMA3 Controller */
+    uint32_t        numEvtQueue;
+
+    /**
+     * Number of Transfer Controllers (TCs) in the underlying EDMA3 Controller
+     */
+    uint32_t        numTcs;
+
+    /** Number of Regions in the underlying EDMA3 Controller  */
+    uint32_t        numRegions;
+
+    /**
+     * \brief Channel mapping existence
+     *
+     * A value of 0 (No channel mapping) implies that there is fixed
+     * association between a DMA channel and a PaRAM Set or, in other words,
+     * DMA channel n can ONLY use PaRAM Set n (No availability of DCHMAP
+     * registers) for transfers to happen.
+     *
+     * A value of 1 implies the presence of DCHMAP registers for the DMA
+     * channels and hence the flexibility of associating any DMA channel to
+     * any PaRAM Set. In other words, ANY PaRAM Set can be used for ANY DMA
+     * channel (like QDMA Channels).
+     */
+    uint32_t           dmaChPaRAMMapExists;
+
+    /** Existence of memory protection feature */
+    uint32_t           memProtectionExists;
+
+    /** Base address of EDMA3 CC memory mapped registers. */
+    void                *globalRegs;
+
+    /** Base address of EDMA3 TCs memory mapped registers. */
+    void                *tcRegs[EDMA3_MAX_TC];
+
+    /**
+     * EDMA3 transfer completion interrupt line (could be different for ARM
+     * and DSP)
+     */
+    uint32_t        xferCompleteInt;
+
+    /** EDMA3 CC error interrupt line (could be different for ARM and DSP) */
+    uint32_t        ccError;
+
+    /** EDMA3 TCs error interrupt line (could be different for ARM and DSP) */
+    uint32_t        tcError[EDMA3_MAX_TC];
+
+    /**
+     * \brief EDMA3 TC priority setting
+     *
+     * User can program the priority of the Event Queues
+     * at a system-wide level.  This means that the user can set the
+     * priority of an IO initiated by either of the TCs (Transfer Controllers)
+     * relative to IO initiated by the other bus masters on the
+     * device (ARM, DSP, USB, etc)
+     */
+    uint32_t        evtQPri [EDMA3_MAX_EVT_QUE];
+
+    /**
+     * \brief Event Queues Watermark Levels
+
+     * To Configure the Threshold level of number of events
+     * that can be queued up in the Event queues. EDMA3CC error register
+     * (CCERR) will indicate whether or not at any instant of time the
+     * number of events queued up in any of the event queues exceeds
+     * or equals the threshold/watermark value that is set
+     * in the queue watermark threshold register (QWMTHRA).
+     */
+    uint32_t        evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE];
+
+    /**
+     * \brief Default Burst Size (DBS) of TCs.
+
+     * An optimally-sized command is defined by the transfer controller
+     * default burst size (DBS). Different TCs can have different
+     * DBS values. It is defined in Bytes.
+     */
+    uint32_t        tcDefaultBurstSize[EDMA3_MAX_TC];
+
+    /**
+     * \brief Mapping from DMA channels to PaRAM Sets
+
+     * If channel mapping exists (DCHMAP registers are present), this array
+     * stores the respective PaRAM Set for each DMA channel. User can
+     * initialize each array member with a specific PaRAM Set or with
+     * EDMA3_DRV_CH_NO_PARAM_MAP.
+     * If channel mapping doesn't exist, it is of no use as the EDMA3 RM
+     * automatically uses the right PaRAM Set for that DMA channel.
+     * Useful only if mapping exists, otherwise of no use.
+     */
+    uint32_t        dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH];
+
+     /**
+      * \brief Mapping from DMA channels to TCCs
+      *
+      * This array stores the respective TCC (interrupt channel) for each
+      * DMA channel. User can initialize each array member with a specific TCC
+      * or with EDMA3_DRV_CH_NO_TCC_MAP. This specific
+      * TCC code will be returned when the transfer is completed
+      * on the mapped DMA channel.
+      */
+     uint32_t       dmaChannelTccMap [EDMA3_MAX_DMA_CH];
+
+    /**
+     * \brief Mapping from DMA channels to Hardware Events
+     *
+     * Each bit in this array corresponds to one DMA channel and tells whether
+     * this DMA channel is tied to any peripheral. That is whether any
+     * peripheral can send the synch event on this DMA channel or not.
+     * 1 means the channel is tied to some peripheral; 0 means it is not.
+     * DMA channels which are tied to some peripheral are RESERVED for that
+     * peripheral only. They are not allocated when user asks for 'ANY' DMA
+     * channel.
+     * All channels need not be mapped, some can be free also.
+     */
+    uint32_t        dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS];
+    } EDMA3_RM_GblConfigParams;
+
+/**\struct  EDMA3_RM_InstanceInitConfig
+ * \brief   Init-time Region Specific Configuration structure for
+ * EDMA3 RM, to provide region specific Information.
+ *
+ * This configuration structure is used to specify which EDMA3 resources are
+ * owned and reserved by the EDMA3 RM instance. This configuration
+ * structure is shadow region specific and will be provided by the user at
+ * run-time while calling EDMA3_RM_open ().
+ *
+ * Owned resources:
+ * ****************
+ *
+ * EDMA3 RM Instances are tied to different shadow regions and hence different
+ * masters. Regions could be:
+ *
+ * a) ARM,
+ * b) DSP,
+ * c) IMCOP (Imaging Co-processor) etc.
+ *
+ * User can assign each EDMA3 resource to a shadow region using this structure.
+ * In this way, user specifies which resources are owned by the specific EDMA3
+ * RM Instance.
+ * This assignment should also ensure that the same resource is not assigned
+ * to more than one shadow regions (unless desired in that way). Any assignment
+ * not following the above mentioned approach may have catastrophic
+ * consequences.
+ *
+ *
+ * Reserved resources:
+ * *******************
+ *
+ * During EDMA3 RM initialization, user can reserve some of the EDMA3 resources
+ * for future use, by specifying which resources to reserve in the configuration
+ * data structure. These (critical) resources are reserved in advance so that
+ * they should not be allocated to someone else and thus could be used in
+ * future for some specific purpose.
+ *
+ * User can request different EDMA3 resources using two methods:
+ * a) By passing the resource type and the actual resource id,
+ * b) By passing the resource type and ANY as resource id
+ *
+ * For e.g. to request DMA channel 31, user will pass 31 as the resource id.
+ * But to request ANY available DMA channel (mainly used for memory-to-memory
+ * data transfer operations), user will pass EDMA3_DRV_DMA_CHANNEL_ANY as the
+ * resource id.
+ *
+ * During initialization, user may have reserved some of the DMA channels for
+ * some specific purpose (mainly for peripherals using EDMA). These reserved
+ * DMA channels then will not be returned when user requests ANY as the
+ * resource id.
+ *
+ * Same logic applies for QDMA channels and TCCs.
+ *
+ * For PaRAM Set, there is one difference. If the DMA channels are one-to-one
+ * tied to their respective PaRAM Sets (i.e. user cannot 'choose' the PaRAM Set
+ * for a particular DMA channel), EDMA3 RM automatically reserves all those
+ * PaRAM Sets which are tied to the DMA channels. Then those PaRAM Sets would
+ * not be returned when user requests for ANY PaRAM Set (specifically for
+ * linking purpose). This is done in order to avoid allocating the PaRAM Set,
+ * tied to a particular DMA channel, for linking purpose. If this constraint is
+ * not there, that DMA channel thus could not be used at all, because of the
+ * unavailability of the desired PaRAM Set.
+ */
+typedef struct
+{
+    /** PaRAM Sets owned by the EDMA3 RM Instance. */
+    uint32_t        ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
+
+    /** DMA Channels owned by the EDMA3 RM Instance. */
+    uint32_t        ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
+
+    /** QDMA Channels owned by the EDMA3 RM Instance. */
+    uint32_t        ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
+
+    /** TCCs owned by the EDMA3 RM Instance. */
+    uint32_t        ownTccs[EDMA3_MAX_TCC_DWRDS];
+
+    /**
+     * \brief   Reserved PaRAM Sets
+     *
+     * PaRAM Sets reserved during initialization for future use. These will not
+     * be given when user requests for ANY available PaRAM Set using
+     * 'EDMA3_RM_PARAM_ANY' as resource/channel id.
+     */
+    uint32_t        resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
+
+    /**
+     * \brief   Reserved DMA channels
+     *
+     * DMA channels reserved during initialization for future use. These will
+     * not be given when user requests for ANY available DMA channel using
+     * 'EDMA3_RM_DMA_CHANNEL_ANY' as resource/channel id.
+     */
+    uint32_t        resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
+
+    /**
+     * \brief   Reserved QDMA channels
+     *
+     * QDMA channels reserved during initialization for future use. These will
+     * not be given when user requests for ANY available QDMA channel using
+     * 'EDMA3_RM_QDMA_CHANNEL_ANY' as resource/channel id.
+     */
+    uint32_t        resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
+
+    /**
+     * \brief   Reserved TCCs
+     *
+     * TCCs reserved during initialization for future use. These will not
+     * be given when user requests for ANY available TCC using
+     * 'EDMA3_RM_TCC_ANY' as resource/channel id.
+     */
+    uint32_t        resvdTccs[EDMA3_MAX_TCC_DWRDS];
+}EDMA3_RM_InstanceInitConfig;
+
+/**\struct      EDMA3_RM_Param
+ * \brief       Used to Initialize the Resource Manager Instance
+ *
+ * This configuration structure is used to initialize the EDMA3 RM Instance.
+ * This configuration information is passed while opening the RM instance.
+ */
+typedef struct {
+    /** Shadow Region Identification */
+    EDMA3_RM_RegionId               regionId;
+
+    /**
+     * It tells whether the EDMA3 RM instance is Master or not. Only the shadow
+     * region associated with this master instance will receive the EDMA3
+     * interrupts (if enabled).
+     */
+    uint32_t                   isMaster;
+
+    /**
+     * EDMA3 resources related shadow region specific information. Which all
+     * EDMA3 resources are owned and reserved by this particular instance are
+     * told in this configuration structure.
+     * User can also pass this structure as NULL. In that case, default static
+     * configuration would be taken from the platform specific configuration
+     * files (part of the Resource Manager), if available.
+     */
+    EDMA3_RM_InstanceInitConfig     *rmInstInitConfig;
+
+    /**
+     * EDMA3 RM Instance specific semaphore handle.
+     * Used to share resources (DMA/QDMA channels, PaRAM Sets, TCCs etc)
+     * among different users.
+     */
+    void                            *rmSemHandle;
+
+    /**
+     * Whether initialization of Region Specific Registers is required or not?
+     */
+    uint32_t                                   regionInitEnable;
+
+    /** Instance wide Global Error callback parameters */
+    EDMA3_RM_GblErrCallbackParams   gblerrCbParams;
+} EDMA3_RM_Param;
+
+/**\struct      EDMA3_RM_MiscParam
+ * \brief       Used to specify the miscellaneous options during Resource
+ * Manager Initialization.
+ *
+ * This configuration structure is used to specify some misc options
+ * while creating the RM Object. New options may also be added into this
+ * structure in future.
+ */
+typedef struct {
+    /**
+     * In a multi-master system (for e.g. ARM + DSP), this option is used to
+     * distinguish between Master and Slave. Only the Master is allowed  to
+     * program the global EDMA3 registers (like Queue priority, Queue water-
+     * mark level, error registers etc).
+     */
+    uint16_t          isSlave;
+
+    /** For future use **/
+    uint16_t          param;
+}EDMA3_RM_MiscParam;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_FUNCTION_INIT
+ @{ */
+
+/**
+ * \brief   Create EDMA3 Resource Manager Object
+ *
+ * This API is used to create the EDMA3 Resource Manager Object. It should be
+ * called only ONCE for each EDMA3 hardware instance.
+ *
+ * Init-time Configuration structure for EDMA3 hardware is provided to pass the
+ * SoC specific information. This configuration information could be provided
+ * by the user at init-time. In case user doesn't provide it, this information
+ * could be taken from the SoC specific configuration file
+ * edma3_<SOC_NAME>_cfg.c, in case it is available.
+ *
+ * This API clears the error specific registers (EMCR/EMCRh, QEMCR, CCERRCLR)
+ * and sets the TCs priorities and Event Queues' watermark levels, if the 'miscParam'
+ * argument is NULL. User can avoid these registers' programming (in some specific
+ * use cases) by SETTING the 'isSlave' field of 'EDMA3_RM_MiscParam' configuration
+ * structure and passing this structure as the third argument (miscParam).
+ *
+ * After successful completion of this API, Resource Manager Object's state
+ * changes to EDMA3_RM_CREATED from EDMA3_RM_DELETED.
+ *
+ * \param phyCtrllerInstId  [IN]    EDMA3 Controller Instance Id
+ *                                 (Hardware instance id, starting from 0).
+ * \param gblCfgParams      [IN]    SoC specific configuration structure for the
+ *                                  EDMA3 Hardware.
+ * \param miscParam         [IN]    Misc configuration options provided in the
+ *                                  structure 'EDMA3_RM_MiscParam'.
+ *                                  For default options, user can pass NULL
+ *                                  in this argument.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ */
+EDMA3_RM_Result EDMA3_RM_create (uint32_t phyCtrllerInstId,
+                                const EDMA3_RM_GblConfigParams *gblCfgParams,
+                                const void *miscParam);
+
+/**
+ * \brief   Delete EDMA3 Resource Manager Object
+ *
+ * This API is used to delete the EDMA3 RM Object. It should be called
+ * once for each EDMA3 hardware instance, ONLY after closing all the
+ * previously opened EDMA3 RM Instances.
+ *
+ * After successful completion of this API, Resource Manager Object's state
+ * changes to EDMA3_RM_DELETED.
+ *
+ * \param phyCtrllerInstId  [IN]    EDMA3 Phy Controller Instance Id (Hardware
+ *                                  instance id, starting from 0).
+ * \param   param           [IN]    For possible future use.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ */
+EDMA3_RM_Result EDMA3_RM_delete (uint32_t phyCtrllerInstId,
+                                const void *param);
+
+/**
+ * \brief   Open EDMA3 Resource Manager Instance
+ *
+ * This API is used to open an EDMA3 Resource Manager Instance. It could be
+ * called multiple times, for each possible EDMA3 shadow region. Maximum
+ * EDMA3_MAX_RM_INSTANCES instances are allowed for each EDMA3 hardware
+ * instance.
+ *
+ * Also, only ONE Master Resource Manager Instance is permitted. This master
+ * instance (and hence the region to which it belongs) will only receive the
+ * EDMA3 interrupts, if enabled.
+ *
+ * User could pass the instance specific configuration structure
+ * (initParam->rmInstInitConfig) as a part of the 'initParam' structure,
+ * during init-time. In case user doesn't provide it, this information could
+ * be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c,
+ * in case it is available.
+ *
+ * By default, this Resource Manager instance will clear the PaRAM Sets while
+ * allocating them. To change the default behavior, user should use the IOCTL
+ * interface appropriately.
+ *
+ * \param   phyCtrllerInstId    [IN]    EDMA3 Controller Instance Id (Hardware
+ *                                      instance id, starting from 0).
+ * \param   initParam           [IN]    Used to Initialize the Resource Manager
+ *                                      Instance (Master or Slave).
+ * \param   errorCode           [OUT]   Error code while opening RM instance.
+ *
+ * \return  Handle to the opened Resource Manager instance Or NULL in case of
+ *          error.
+ *
+ * \note    This function disables the global interrupts (by calling API
+ *          edma3OsProtectEntry with protection level
+ *          EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data
+ *          structures, to make it re-entrant.
+ */
+EDMA3_RM_Handle EDMA3_RM_open (uint32_t phyCtrllerInstId,
+                                const EDMA3_RM_Param *initParam,
+                                EDMA3_RM_Result *errorCode);
+
+/**
+ * \brief  Close EDMA3 Resource Manager Instance
+ *
+ * This API is used to close a previously opened EDMA3 RM Instance.
+ *
+ * \param  hEdmaResMgr         [IN]    Handle to the previously opened Resource
+ *                                     Manager Instance.
+ * \param  param               [IN]    For possible future use.
+ *
+ * \return EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function disables the global interrupts (by calling API
+ *          edma3OsProtectEntry with protection level
+ *          EDMA3_OS_PROTECT_INTERRUPT) while modifying the global RM data
+ *          structures, to make it re-entrant.
+ */
+EDMA3_RM_Result EDMA3_RM_close (EDMA3_RM_Handle hEdmaResMgr,
+                                const void *param);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_FUNCTION_BASIC
+ @{ */
+
+/**
+ * \brief   This API is used to allocate specified EDMA3 Resources like
+ * DMA/QDMA channel, PaRAM Set or TCC.
+ *
+ * Note: To free the resources allocated by this API, user should call
+ * EDMA3_RM_freeResource () ONLY to de-allocate all the allocated resources.
+ *
+ * User can either request a specific resource by passing the resource id
+ * in 'resObj->resId' OR request ANY available resource of the type
+ * 'resObj->type'.
+ *
+ * ANY types of resources are those resources when user doesn't care about the
+ * actual resource allocated; user just wants a resource of the type specified.
+ * One use-case is to perform memory-to-memory data transfer operation. This
+ * operation can be performed using any available DMA or QDMA channel.
+ * User doesn't need any specific channel for the same.
+ *
+ * To allocate a specific resource, first this API checks whether that resource
+ * is OWNED by the Resource Manager instance. Then it checks the current
+ * availability of that resource.
+ *
+ * To allocate ANY available resource, this API tries to allocate a resource
+ * from the pool of (owned && non_reserved && available_right_now) resources.
+ *
+ * After allocating a DMA/QDMA channel, the same resource is enabled in
+ * the shadow region specific register (DRAE/DRAEH/QRAE). DRAE/DRAEH register
+ * for a TCC is updated only when user registers a callback function against
+ * that TCC using EDMA3_RM_registerTccCb().
+ *
+ * Allocated PaRAM Set is initialized to NULL before this API returns if user
+ * has requested for one.
+ *
+ * \param  hEdmaResMgr      [IN]        Handle to the previously opened Resource
+ *                                      Manager Instance.
+ * \param   resObj          [IN/OUT]    Handle to the resource descriptor
+ *                                      object, which needs to be allocated.
+ *                                      In case user passes a specific resource
+ *                                      Id, resObj value is left unchanged.
+ *                                      In case user requests ANY available
+ *                                      resource, the allocated resource id is
+ *                                      returned in resObj.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function acquires a RM Instance specific semaphore
+ *          to prevent simultaneous access to the global pool of resources.
+ *          It is re-entrant, but should not be called from the user callback
+ *          function (ISR context).
+ */
+EDMA3_RM_Result EDMA3_RM_allocResource (EDMA3_RM_Handle hEdmaResMgr,
+                                        EDMA3_RM_ResDesc *resObj);
+
+/**
+ * \brief   This API is used to free previously allocated EDMA3 Resources like
+ * DMA/QDMA channel, PaRAM Set or TCC.
+ *
+ * To free a specific resource, first this API checks whether that resource is
+ * OWNED by the Resource Manager Instance. Then it checks whether that resource
+ * has been allocated by the Resource Manager instance or not.
+ *
+ * After freeing a DMA/QDMA channel, the same resource is disabled in
+ * the shadow region specific register (DRAE/DRAEH/QRAE). This operation is
+ * performed for TCC while unregistering the callback function.
+ *
+ * \param  hEdmaResMgr         [IN]    Handle to the previously opened Resource
+ *                                     Manager Instance.
+ * \param   resObj             [IN]    Handle to the resource descriptor
+ *                                     object, which needs to be freed.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function disables the global interrupts to prevent
+ *          simultaneous access to the global pool of resources.
+ *          It is re-entrant.
+ */
+EDMA3_RM_Result EDMA3_RM_freeResource(EDMA3_RM_Handle hEdmaResMgr,
+                            const EDMA3_RM_ResDesc *resObj);
+
+/**
+ * \brief   Allocate a contiguous region of specified EDMA3 Resource
+ * like DMA channel, QDMA channel, PaRAM Set or TCC.
+ *
+ * This API is used to allocate a contiguous region of specified EDMA3
+ * Resources like DMA channel, QDMA channel, PaRAM Set or TCC.
+ *
+ * User can specify a particular resource Id to start with and go up to the
+ * number of resources requested. The specific resource id to start from could
+ * be passed in 'firstResIdObject->resId' and the number of resources requested
+ * in 'numResources'.
+ *
+ * User can also request ANY available resource(s) of the type
+ * 'firstResIdObject->type' by specifying 'firstResIdObject->resId' as
+ * EDMA3_RM_RES_ANY.
+ *
+ * ANY types of resources are those resources when user doesn't care about the
+ * actual resource allocated; user just wants a resource of the type specified.
+ * One use-case is to perform memory-to-memory data transfer operation. This
+ * operation can be performed using any available DMA or QDMA channel. User
+ * doesn't need any specific channel for the same.
+ *
+ * To allocate specific contiguous resources, first this API checks whether
+ * those requested resources are OWNED by the Resource Manager instance. Then
+ * it checks the current availability of those resources.
+ *
+ * To allocate ANY available contiguous resources, this API tries to allocate
+ * resources from the pool of (owned && non_reserved && available_right_now)
+ * resources.
+ *
+ * After allocating DMA/QDMA channels, the same resources are enabled in
+ * the shadow region specific register (DRAE/DRAEH/QRAE). DRAE/DRAEH register
+ * for a TCC is updated only when user registers a callback function against
+ * that TCC using EDMA3_RM_registerTccCb(). Allocated PaRAM Sets are initialized
+ * to NULL before this API returns.
+ *
+ * \param   hEdmaResMgr         [IN]    Handle to the previously opened Resource
+ *                                      Manager Instance.
+ * \param   firstResIdObj       [IN]    Handle to the first resource descriptor
+ *                                      object, which needs to be allocated.
+ *                                      firstResIdObject->resId could be a valid
+ *                                      resource id in case user wants to
+ *                                      allocate specific resources OR it could
+ *                                      be EDMA3_RM_RES_ANY in case user wants
+ *                                      only the required number of resources
+ *                                      and doesn't care about which resources
+ *                                      were allocated.
+ * \param   numResources        [IN]    Number of contiguous resources user
+ *                                      wants to allocate.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function acquires a RM Instance specific semaphore
+ *          to prevent simultaneous access to the global pool of resources.
+ *          It is re-entrant, but should not be called from the user callback
+ *          function (ISR context).
+ */
+EDMA3_RM_Result EDMA3_RM_allocContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
+                                            EDMA3_RM_ResDesc *firstResIdObj,
+                                            uint32_t numResources);
+
+/**
+ * \brief   Free a contiguous region of specified EDMA3 Resource
+ * like DMA channel, QDMA channel, PaRAM Set or TCC, previously allocated.
+ *
+ * This API frees a contiguous region of specified EDMA3 Resources
+ * like DMA channel, QDMA channel, PaRAM Set or TCC, which have been previously
+ * allocated. In case of an error during the freeing of any specific resource,
+ * user can check the 'firstResIdObj' object to know the last resource id
+ * whose freeing has failed. In case of success, there is no need to check this
+ * object.
+ *
+ * \param  hEdmaResMgr         [IN]         Handle to the previously opened
+ *                                          Resource Manager Instance.
+ * \param   firstResIdObj      [IN/OUT]     Handle to the first resource
+ *                                          descriptor object, which needs to be
+ *                                          freed. In case of an error while
+ *                                          freeing any particular resource,
+ *                                          the last resource id whose freeing has
+ *                                          failed is returned in this resource
+ *                                          descriptor object.
+ * \param   numResources      [IN]          Number of contiguous resources allocated
+ *                                          previously which user wants to release
+ *
+ * \note        This is a re-entrant function which internally calls
+ *              EDMA3_RM_freeResource() for resource de-allocation.
+ */
+EDMA3_RM_Result EDMA3_RM_freeContiguousResource(EDMA3_RM_Handle hEdmaResMgr,
+                                           EDMA3_RM_ResDesc *firstResIdObj,
+                                           uint32_t numResources);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_SYMBOL_DEFINE
+ @{ */
+
+/* Defines for Logical Channel Values */
+/*---------------------------------------------------------------------------*/
+/**
+ * Used to specify any available DMA Channel while requesting
+ * one. Used in the API EDMA3_RM_allocLogicalChannel ().
+ * DMA channel from the pool of (owned && non_reserved && available_right_now)
+ * DMA channels will be chosen and returned.
+ */
+#define EDMA3_RM_DMA_CHANNEL_ANY            (1011u)
+
+/**
+ * Used to specify any available QDMA Channel while requesting
+ * one. Used in the API EDMA3_RM_allocLogicalChannel().
+ * QDMA channel from the pool of (owned && non_reserved && available_right_now)
+ * QDMA channels will be chosen and returned.
+ */
+#define EDMA3_RM_QDMA_CHANNEL_ANY           (1012u)
+
+/**
+ * Used to specify any available TCC while requesting
+ * one. Used in the API EDMA3_RM_allocLogicalChannel(), for
+ * both DMA and QDMA channels.
+ * TCC from the pool of (owned && non_reserved && available_right_now)
+ * TCCs will be chosen and returned.
+ */
+#define EDMA3_RM_TCC_ANY                    (1013u)
+
+/**
+ * Used to specify any available PaRAM Set while requesting
+ * one. Used in the API EDMA3_RM_allocLogicalChannel(), for
+ * both DMA/QDMA and Link channels.
+ * PaRAM Set from the pool of (owned && non_reserved && available_right_now)
+ * PaRAM Sets will be chosen and returned.
+ */
+#define EDMA3_RM_PARAM_ANY                  (1014u)
+
+/**
+ * This define is used to specify that a DMA channel is NOT tied to any PaRAM
+ * Set and hence any available PaRAM Set could be used for that DMA channel.
+ * It could be used in dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH], in global
+ * configuration structure EDMA3_RM_GblConfigParams.
+ *
+ * This value should mandatorily be used to mark DMA channels with no initial
+ * mapping to specific PaRAM Sets.
+ */
+#define EDMA3_RM_CH_NO_PARAM_MAP           (1015u)
+
+/**
+ * This define is used to specify that the DMA/QDMA channel is not tied to any
+ * TCC and hence any available TCC could be used for that DMA/QDMA channel.
+ * It could be used in dmaChannelTccMap [EDMA3_MAX_DMA_CH], in global
+ * configuration structure EDMA3_RM_GblConfigParams.
+ *
+ * This value should mandatorily be used to mark DMA channels with no initial
+ * mapping to specific TCCs.
+ */
+#define EDMA3_RM_CH_NO_TCC_MAP             (1016u)
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_SYMBOL_ENUM
+ @{ */
+
+/**
+ * \brief DMA Channels assigned to different Hardware Events.
+ *
+ * They should be used while requesting a specific DMA channel.
+ * One possible usage is to maintain a SoC specific file, which will
+ * contain the mapping of these hardware events to the respective
+ * peripherals for better understanding and lesser probability of
+ * errors. Also, if any event associated with a particular peripheral
+ * gets changed, only that SoC specific file needs to be changed.
+ * for eg, the sample SoC specific file "soc.h" can have these defines:
+ *
+ * #define EDMA3_RM_HW_CHANNEL_MCBSP_TX        EDMA3_RM_HW_CHANNEL_EVENT_2
+ * #define EDMA3_RM_HW_CHANNEL_MCBSP_RX        EDMA3_RM_HW_CHANNEL_EVENT_3
+ *
+ * These defines will be used by the MCBSP driver. The same event
+ * EDMA3_RM_HW_CHANNEL_EVENT_2/3 could be mapped to some other
+ * peripheral also.
+ */
+typedef enum
+{
+   /** Channel assigned to EDMA3 Event 0 */
+    EDMA3_RM_HW_CHANNEL_EVENT_0 = 0,
+    /** Channel assigned to EDMA3 Event 1 */
+    EDMA3_RM_HW_CHANNEL_EVENT_1,
+    /** Channel assigned to EDMA3 Event 2 */
+    EDMA3_RM_HW_CHANNEL_EVENT_2,
+    /** Channel assigned to EDMA3 Event 3 */
+    EDMA3_RM_HW_CHANNEL_EVENT_3,
+    /** Channel assigned to EDMA3 Event 4 */
+    EDMA3_RM_HW_CHANNEL_EVENT_4,
+    /** Channel assigned to EDMA3 Event 5 */
+    EDMA3_RM_HW_CHANNEL_EVENT_5,
+    /** Channel assigned to EDMA3 Event 6 */
+    EDMA3_RM_HW_CHANNEL_EVENT_6,
+    /** Channel assigned to EDMA3 Event 7 */
+    EDMA3_RM_HW_CHANNEL_EVENT_7,
+    /** Channel assigned to EDMA3 Event 8 */
+    EDMA3_RM_HW_CHANNEL_EVENT_8,
+    /** Channel assigned to EDMA3 Event 9 */
+    EDMA3_RM_HW_CHANNEL_EVENT_9,
+    /** Channel assigned to EDMA3 Event 10 */
+    EDMA3_RM_HW_CHANNEL_EVENT_10,
+    /** Channel assigned to EDMA3 Event 11 */
+    EDMA3_RM_HW_CHANNEL_EVENT_11,
+    /** Channel assigned to EDMA3 Event 12 */
+    EDMA3_RM_HW_CHANNEL_EVENT_12,
+    /** Channel assigned to EDMA3 Event 13 */
+    EDMA3_RM_HW_CHANNEL_EVENT_13,
+    /** Channel assigned to EDMA3 Event 14 */
+    EDMA3_RM_HW_CHANNEL_EVENT_14,
+    /** Channel assigned to EDMA3 Event 15 */
+    EDMA3_RM_HW_CHANNEL_EVENT_15,
+    /** Channel assigned to EDMA3 Event 16 */
+    EDMA3_RM_HW_CHANNEL_EVENT_16,
+    /** Channel assigned to EDMA3 Event 17 */
+    EDMA3_RM_HW_CHANNEL_EVENT_17,
+    /** Channel assigned to EDMA3 Event 18 */
+    EDMA3_RM_HW_CHANNEL_EVENT_18,
+    /** Channel assigned to EDMA3 Event 19 */
+    EDMA3_RM_HW_CHANNEL_EVENT_19,
+    /** Channel assigned to EDMA3 Event 20 */
+    EDMA3_RM_HW_CHANNEL_EVENT_20,
+    /** Channel assigned to EDMA3 Event 21 */
+    EDMA3_RM_HW_CHANNEL_EVENT_21,
+    /** Channel assigned to EDMA3 Event 22 */
+    EDMA3_RM_HW_CHANNEL_EVENT_22,
+    /** Channel assigned to EDMA3 Event 23 */
+    EDMA3_RM_HW_CHANNEL_EVENT_23,
+    /** Channel assigned to EDMA3 Event 24 */
+    EDMA3_RM_HW_CHANNEL_EVENT_24,
+    /** Channel assigned to EDMA3 Event 25 */
+    EDMA3_RM_HW_CHANNEL_EVENT_25,
+    /** Channel assigned to EDMA3 Event 26 */
+    EDMA3_RM_HW_CHANNEL_EVENT_26,
+    /** Channel assigned to EDMA3 Event 27 */
+    EDMA3_RM_HW_CHANNEL_EVENT_27,
+    /** Channel assigned to EDMA3 Event 28 */
+    EDMA3_RM_HW_CHANNEL_EVENT_28,
+    /** Channel assigned to EDMA3 Event 29 */
+    EDMA3_RM_HW_CHANNEL_EVENT_29,
+    /** Channel assigned to EDMA3 Event 30 */
+    EDMA3_RM_HW_CHANNEL_EVENT_30,
+    /** Channel assigned to EDMA3 Event 31 */
+    EDMA3_RM_HW_CHANNEL_EVENT_31,
+    /** Channel assigned to EDMA3 Event 32 */
+    EDMA3_RM_HW_CHANNEL_EVENT_32,
+    /** Channel assigned to EDMA3 Event 33 */
+    EDMA3_RM_HW_CHANNEL_EVENT_33,
+    /** Channel assigned to EDMA3 Event 34 */
+    EDMA3_RM_HW_CHANNEL_EVENT_34,
+    /** Channel assigned to EDMA3 Event 35 */
+    EDMA3_RM_HW_CHANNEL_EVENT_35,
+    /** Channel assigned to EDMA3 Event 36 */
+    EDMA3_RM_HW_CHANNEL_EVENT_36,
+    /** Channel assigned to EDMA3 Event 37 */
+    EDMA3_RM_HW_CHANNEL_EVENT_37,
+    /** Channel assigned to EDMA3 Event 38 */
+    EDMA3_RM_HW_CHANNEL_EVENT_38,
+    /** Channel assigned to EDMA3 Event 39 */
+    EDMA3_RM_HW_CHANNEL_EVENT_39,
+    /** Channel assigned to EDMA3 Event 40 */
+    EDMA3_RM_HW_CHANNEL_EVENT_40,
+    /** Channel assigned to EDMA3 Event 41 */
+    EDMA3_RM_HW_CHANNEL_EVENT_41,
+    /** Channel assigned to EDMA3 Event 42 */
+    EDMA3_RM_HW_CHANNEL_EVENT_42,
+    /** Channel assigned to EDMA3 Event 43 */
+    EDMA3_RM_HW_CHANNEL_EVENT_43,
+    /** Channel assigned to EDMA3 Event 44 */
+    EDMA3_RM_HW_CHANNEL_EVENT_44,
+    /** Channel assigned to EDMA3 Event 45 */
+    EDMA3_RM_HW_CHANNEL_EVENT_45,
+    /** Channel assigned to EDMA3 Event 46 */
+    EDMA3_RM_HW_CHANNEL_EVENT_46,
+    /** Channel assigned to EDMA3 Event 47 */
+    EDMA3_RM_HW_CHANNEL_EVENT_47,
+    /** Channel assigned to EDMA3 Event 48 */
+    EDMA3_RM_HW_CHANNEL_EVENT_48,
+    /** Channel assigned to EDMA3 Event 49 */
+    EDMA3_RM_HW_CHANNEL_EVENT_49,
+    /** Channel assigned to EDMA3 Event 50 */
+    EDMA3_RM_HW_CHANNEL_EVENT_50,
+    /** Channel assigned to EDMA3 Event 51 */
+    EDMA3_RM_HW_CHANNEL_EVENT_51,
+    /** Channel assigned to EDMA3 Event 52 */
+    EDMA3_RM_HW_CHANNEL_EVENT_52,
+    /** Channel assigned to EDMA3 Event 53 */
+    EDMA3_RM_HW_CHANNEL_EVENT_53,
+    /** Channel assigned to EDMA3 Event 54 */
+    EDMA3_RM_HW_CHANNEL_EVENT_54,
+    /** Channel assigned to EDMA3 Event 55 */
+    EDMA3_RM_HW_CHANNEL_EVENT_55,
+    /** Channel assigned to EDMA3 Event 56 */
+    EDMA3_RM_HW_CHANNEL_EVENT_56,
+    /** Channel assigned to EDMA3 Event 57 */
+    EDMA3_RM_HW_CHANNEL_EVENT_57,
+    /** Channel assigned to EDMA3 Event 58 */
+    EDMA3_RM_HW_CHANNEL_EVENT_58,
+    /** Channel assigned to EDMA3 Event 59 */
+    EDMA3_RM_HW_CHANNEL_EVENT_59,
+    /** Channel assigned to EDMA3 Event 60 */
+    EDMA3_RM_HW_CHANNEL_EVENT_60,
+    /** Channel assigned to EDMA3 Event 61 */
+    EDMA3_RM_HW_CHANNEL_EVENT_61,
+    /** Channel assigned to EDMA3 Event 62 */
+    EDMA3_RM_HW_CHANNEL_EVENT_62,
+    /** Channel assigned to EDMA3 Event 63 */
+    EDMA3_RM_HW_CHANNEL_EVENT_63
+} EDMA3_RM_HW_CHANNEL_EVENT;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_FUNCTION_ADVANCED
+ @{ */
+
+/**
+ * \brief   Request a DMA/QDMA/Link channel.
+ *
+ * This API is used to allocate a logical channel (DMA/QDMA/Link) along with
+ * the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are
+ * also allocated along with the requested channel. For Link channel, ONLY a
+ * PaRAM Set is allocated.
+ *
+ * Note: To free the logical channel allocated by this API, user should call
+ * EDMA3_RM_freeLogicalChannel () ONLY to de-allocate all the allocated resources
+ * and remove certain mappings.
+ *
+ * User can request a specific logical channel by passing the channel id in
+ * 'lChObj->resId' and channel type in 'lChObj->type'. Note that the channel
+ * id is the same as the actual resource id. For e.g. in the case of QDMA
+ * channels, valid channel ids are from 0 to 7 only.
+ *
+ * User can also request ANY available logical channel of the type
+ * 'lChObj->type' by specifying 'lChObj->resId' as:
+ *  a)  EDMA3_RM_DMA_CHANNEL_ANY: For DMA channels
+ *  b)  EDMA3_RM_QDMA_CHANNEL_ANY: For QDMA channels, and
+ *  c)  EDMA3_RM_PARAM_ANY: For Link channels. Normally user should use this
+ *      value to request link channels (PaRAM Sets used for linking purpose
+ *      only), unless he wants to use some specific link channels (PaRAM Sets)
+ *      which is also allowed.
+ *
+ * This API internally uses EDMA3_RM_allocResource () to allocate the desired
+ * resources (DMA/QDMA channel, PaRAM Set and TCC).
+ *
+ * For DMA/QDMA channels, after allocating all the EDMA3 resources, this API
+ * sets the TCC field of the OPT PaRAM Word with the allocated TCC.
+ *
+ * For DMA channel, it also sets the DCHMAP register, if required.
+ *
+ * For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and
+ * enables the QDMA channel by writing to the QEESR register.
+ *
+ * \param  hEdmaResMgr      [IN]        Handle to the previously opened Resource
+ *                                      Manager Instance.
+ * \param  lChObj           [IN/OUT]    Handle to the requested logical channel
+ *                                      object, which needs to be allocated.
+ *                                      It could be a specific logical channel
+ *                                      or ANY available logical channel of the
+ *                                      requested type.
+ *                                      In case user passes a specific resource
+ *                                      Id, lChObj value is left unchanged. In
+ *                                      case user requests ANY available
+ *                                      resource, the allocated resource id is
+ *                                      returned in lChObj->resId.
+ *
+ *  \param  pParam          [IN/OUT]    PaRAM Set for a particular logical
+ *                                      (DMA/QDMA) channel. Not used if user
+ *                                      requested for a Link channel.
+ *                                      In case user passes a specific PaRAM
+ *                                      Set value, pParam value is left
+ *                                      unchanged. In case user requests ANY
+ *                                      available PaRAM Set by passing
+ *                                      'EDMA3_RM_PARAM_ANY' in pParam,
+ *                                      the allocated one is returned in pParam.
+ *
+ *  \param  pTcc            [IN/OUT]    TCC for a particular logical (DMA/QDMA)
+ *                                      channel. Not used if user requested for
+ *                                      a Link channel.
+ *                                      In case user passes a specific TCC
+ *                                      value, pTcc value is left unchanged.
+ *                                      In case user requests ANY
+ *                                      available TCC by passing
+ *                                      'EDMA3_RM_TCC_ANY' in pTcc,
+ *                                      the allocated one is returned in pTcc.
+ *
+ * \return  EDMA3_RM_SOK or EDMA_RM Error Code
+ *
+ * \note    This function internally calls EDMA3_RM_allocResource (), which
+ *          acquires a RM Instance specific semaphore to prevent simultaneous
+ *          access to the global pool of resources. It is re-entrant for unique
+ *          logical channel values, but SHOULD NOT be called from the user
+ *          callback function (ISR context).
+ */
+EDMA3_RM_Result EDMA3_RM_allocLogicalChannel(EDMA3_RM_Handle hEdmaResMgr,
+                            EDMA3_RM_ResDesc *lChObj,
+                            uint32_t *pParam,
+                            uint32_t *pTcc);
+
+/** \fn     EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle
+ *                       hEdmaResMgr, EDMA3_RM_ResDesc *lChObj)
+ *  \brief  This API is used to free the specified channel (DMA/QDMA/Link) and
+ *          its associated resources (PaRAM Set, TCC etc).
+ *
+ * This API internally uses EDMA3_RM_freeResource () to free the desired
+ * resources.
+ *
+ * For DMA/QDMA channels, it also clears the DCHMAP/QCHMAP registers
+ *
+ * \param  hEdmaResMgr      [IN]    Handle to the previously opened Resource
+ *                                  Manager Instance.
+ * \param  lChObj           [IN]    Handle to the logical channel object,
+ *                                  which needs to be freed
+ *
+ * \return  EDMA3_RM_SOK or EDMA_RM Error Code
+ *
+ * \note    This is a re-entrant function which internally calls
+ *          EDMA3_RM_freeResource () for resource de-allocation.
+ */
+EDMA3_RM_Result EDMA3_RM_freeLogicalChannel (EDMA3_RM_Handle hEdmaResMgr,
+                                                EDMA3_RM_ResDesc *lChObj);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_DATASTRUCT
+ @{ */
+
+/**\struct  EDMA3_RM_ParamentryRegs
+ * \brief   EDMA3 PaRAM Set
+ *
+ * This is a mapping of the EDMA3 PaRAM set provided to the user
+ * for ease of modification of the individual PaRAM words.
+ *
+ * It could be used by the advanced users to program the PaRAM Set directly,
+ * without using any API.
+ */
+typedef struct  {
+    /** OPT field of PaRAM Set */
+    volatile uint32_t OPT;
+
+    /**
+     * \brief Starting byte address of Source
+     * For FIFO mode, srcAddr must be a 256-bit aligned address.
+     */
+    volatile uint32_t SRC;
+
+    /**
+     * Number of bytes in each Array (ACNT) (16 bits) and
+     * Number of Arrays in each Frame (BCNT) (16 bits).
+     */
+    volatile uint32_t A_B_CNT;
+
+    /**
+     * \brief Starting byte address of destination
+     * For FIFO mode, destAddr must be a 256-bit aligned address.
+     * i.e. 5 LSBs should be 0.
+     */
+    volatile uint32_t DST;
+
+    /**
+     * Index between consec. arrays of a Source Frame (SRCBIDX) (16 bits) and
+     * Index between consec. arrays of a Destination Frame (DSTBIDX) (16 bits).
+     *
+     * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should
+     * be an even multiple of 32 bytes.
+     *
+     * If DAM is set to 1 (via channelOptions) then destInterArrIndex should
+     * be an even multiple of 32 bytes
+     */
+    volatile uint32_t SRC_DST_BIDX;
+
+    /**
+     * \brief Address for linking (AutoReloading of a PaRAM Set) (16 bits)
+     * and Reload value of the numArrInFrame (BCNT) (16 bits).
+     *
+     * Link field must point to a valid aligned 32-byte PaRAM set
+     * A value of 0xFFFF means no linking.
+     *
+     * B count reload field is relevant only for A-sync transfers.
+     */
+    volatile uint32_t LINK_BCNTRLD;
+
+    /**
+     * \brief Index between consecutive frames of a Source Block (SRCCIDX)
+     * (16 bits) and Index between consecutive frames of a Dest Block
+     * (DSTCIDX) (16 bits).
+     */
+    volatile uint32_t SRC_DST_CIDX;
+
+    /**
+     * \brief Number of Frames in a block (CCNT) (16 bits).
+     */
+    volatile uint32_t CCNT;
+} EDMA3_RM_ParamentryRegs;
+
+/**\struct      EDMA3_RM_PaRAMRegs
+ * \brief       EDMA3 PaRAM Set in User Configurable format
+ *
+ * This is a mapping of the EDMA3 PaRAM set provided to the user
+ * for ease of modification of the individual fields.
+ */
+#ifndef _BIG_ENDIAN
+/* LITTLE_ENDIAN_MODE */
+typedef struct  {
+        /** OPT field of PaRAM Set */
+        volatile uint32_t opt;
+
+        /**
+         * \brief Starting byte address of Source
+         * For FIFO mode, srcAddr must be a 256-bit aligned address.
+         */
+        volatile uint32_t srcAddr;
+
+        /**
+         * \brief Number of bytes in each Array (ACNT)
+         */
+        volatile uint16_t aCnt;
+
+        /**
+         * \brief Number of Arrays in each Frame (BCNT)
+         */
+        volatile uint16_t bCnt;
+
+        /**
+         * \brief Starting byte address of destination
+         * For FIFO mode, destAddr must be a 256-bit aligned address.
+         * i.e. 5 LSBs should be 0.
+         */
+        volatile uint32_t destAddr;
+
+        /**
+         * \brief Index between consec. arrays of a Source Frame (SRCBIDX)
+         * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should
+         * be an even multiple of 32 bytes.
+         */
+        volatile int16_t  srcBIdx;
+
+        /**
+         * \brief Index between consec. arrays of a Destination Frame (DSTBIDX)
+         * If DAM is set to 1 (via channelOptions) then destInterArrIndex should
+         * be an even multiple of 32 bytes
+         */
+        volatile int16_t  destBIdx;
+
+        /**
+         * \brief Address for linking (AutoReloading of a PaRAM Set)
+         * This must point to a valid aligned 32-byte PaRAM set
+         * A value of 0xFFFF means no linking
+         * Linking is especially useful for use with ping-pong buffers and
+         * circular buffers
+         */
+        volatile uint16_t linkAddr;
+
+        /**
+         * \brief Reload value of the numArrInFrame (BCNT)
+         * Relevant only for A-sync transfers
+         */
+        volatile uint16_t bCntReload;
+
+        /**
+         * \brief Index between consecutive frames of a Source Block (SRCCIDX)
+         */
+        volatile int16_t  srcCIdx;
+
+        /**
+         * \brief Index between consecutive frames of a Dest Block (DSTCIDX)
+         */
+        volatile int16_t  destCIdx;
+
+        /**
+         * \brief Number of Frames in a block (CCNT)
+         */
+        volatile uint16_t cCnt;
+
+        /**
+         * \brief Reserved
+         */
+        volatile int16_t  reserved;
+} EDMA3_RM_PaRAMRegs;
+#else
+/* BIG_ENDIAN_MODE */
+typedef struct  {
+        /** OPT field of PaRAM Set */
+        volatile uint32_t opt;
+
+        /**
+         * \brief Starting byte address of Source
+         * For FIFO mode, srcAddr must be a 256-bit aligned address.
+         */
+        volatile uint32_t srcAddr;
+
+        /**
+         * \brief Number of Arrays in each Frame (BCNT)
+         */
+        volatile uint16_t bCnt;
+
+        /**
+         * \brief Number of bytes in each Array (ACNT)
+         */
+        volatile uint16_t aCnt;
+
+        /**
+         * \brief Starting byte address of destination
+         * For FIFO mode, destAddr must be a 256-bit aligned address.
+         * i.e. 5 LSBs should be 0.
+         */
+        volatile uint32_t destAddr;
+
+        /**
+         * \brief Index between consec. arrays of a Destination Frame (DSTBIDX)
+         * If DAM is set to 1 (via channelOptions) then destInterArrIndex should
+         * be an even multiple of 32 bytes
+         */
+        volatile int16_t  destBIdx;
+
+        /**
+         * \brief Index between consec. arrays of a Source Frame (SRCBIDX)
+         * If SAM is set to 1 (via channelOptions) then srcInterArrIndex should
+         * be an even multiple of 32 bytes.
+         */
+        volatile int16_t  srcBIdx;
+
+        /**
+         * \brief Reload value of the numArrInFrame (BCNT)
+         * Relevant only for A-sync transfers
+         */
+        volatile uint16_t bCntReload;
+
+        /**
+         * \brief Address for linking (AutoReloading of a PaRAM Set)
+         * This must point to a valid aligned 32-byte PaRAM set
+         * A value of 0xFFFF means no linking
+         * Linking is especially useful for use with ping-pong buffers and
+         * circular buffers
+         */
+        volatile uint16_t linkAddr;
+
+        /**
+         * \brief Index between consecutive frames of a Dest Block (DSTCIDX)
+         */
+        volatile int16_t  destCIdx;
+
+        /**
+         * \brief Index between consecutive frames of a Source Block (SRCCIDX)
+         */
+        volatile int16_t  srcCIdx;
+
+        /**
+         * \brief Reserved
+         */
+        volatile int16_t  reserved;
+
+        /**
+         * \brief Number of Frames in a block (CCNT)
+         */
+        volatile uint16_t cCnt;
+} EDMA3_RM_PaRAMRegs;
+#endif         /* #ifndef _BIG_ENDIAN */
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_SYMBOL_ENUM
+ @{ */
+
+/**\enum    EDMA3_RM_QdmaTrigWord
+ * \brief   QDMA Trigger Word
+ *
+ * Use this enum to set the QDMA trigger word to any of the
+ * 8 DWords(uint32_t) within a Parameter RAM set
+ */
+typedef enum
+{
+        /**
+         * Set the OPT field (Offset Address 0h Bytes)
+         * as the QDMA trigger word
+         */
+        EDMA3_RM_QDMA_TRIG_OPT                  = 0,
+        /**
+         * Set the SRC field (Offset Address 4h Bytes)
+         * as the QDMA trigger word
+         */
+        EDMA3_RM_QDMA_TRIG_SRC                  = 1,
+        /**
+         * Set the (ACNT + BCNT) field (Offset Address 8h Bytes)
+         * as the QDMA trigger word
+         */
+        EDMA3_RM_QDMA_TRIG_ACNT_BCNT            = 2,
+        /**
+         * Set the DST field (Offset Address Ch Bytes)
+         * as the QDMA trigger word
+         */
+        EDMA3_RM_QDMA_TRIG_DST                  = 3,
+        /**
+         * Set the (SRCBIDX + DSTBIDX) field (Offset Address 10h Bytes)
+         * as the QDMA trigger word
+         */
+        EDMA3_RM_QDMA_TRIG_SRC_DST_BIDX         = 4,
+        /**
+         * Set the (LINK + BCNTRLD) field (Offset Address 14h Bytes)
+         * as the QDMA trigger word
+         */
+        EDMA3_RM_QDMA_TRIG_LINK_BCNTRLD         = 5,
+        /**
+         * Set the (SRCCIDX + DSTCIDX) field (Offset Address 18h Bytes)
+         * as the QDMA trigger word
+         */
+        EDMA3_RM_QDMA_TRIG_SRC_DST_CIDX         = 6,
+        /**
+         * Set the (CCNT + RSVD) field (Offset Address 1Ch Bytes)
+         * as the QDMA trigger word
+         */
+        EDMA3_RM_QDMA_TRIG_CCNT                 = 7,
+        /** Default Trigger Word */
+        EDMA3_RM_QDMA_TRIG_DEFAULT              = 7
+} EDMA3_RM_QdmaTrigWord;
+
+/**\enum    EDMA3_RM_Cntrlr_PhyAddr
+ * \brief   CC/TC Physical Address
+ *
+ * Use this enum to get the physical address of the Channel Controller or the
+ * Transfer Controller. The address returned could be used by the advanced
+ * users to set/get some specific registers direclty.
+ */
+typedef enum
+{
+    /** Channel Controller Physical Address */
+    EDMA3_RM_CC_PHY_ADDR = 0,
+    /** Transfer Controller 0 Physical Address */
+    EDMA3_RM_TC0_PHY_ADDR,
+    /** Transfer Controller 1 Physical Address */
+    EDMA3_RM_TC1_PHY_ADDR,
+    /** Transfer Controller 2 Physical Address */
+    EDMA3_RM_TC2_PHY_ADDR,
+    /** Transfer Controller 3 Physical Address */
+    EDMA3_RM_TC3_PHY_ADDR,
+    /** Transfer Controller 4 Physical Address */
+    EDMA3_RM_TC4_PHY_ADDR,
+    /** Transfer Controller 5 Physical Address */
+    EDMA3_RM_TC5_PHY_ADDR,
+    /** Transfer Controller 6 Physical Address */
+    EDMA3_RM_TC6_PHY_ADDR,
+    /** Transfer Controller 7 Physical Address */
+    EDMA3_RM_TC7_PHY_ADDR
+}EDMA3_RM_Cntrlr_PhyAddr;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_FUNCTION_ADVANCED
+ @{ */
+
+/**
+ * \brief   Bind the resources DMA Channel and PaRAM Set. Both the DMA channel
+ * and the PaRAM set should be previously allocated. If they are not,
+ * this API will result in error.
+ *
+ * This API sets the DCHMAP register for a specific DMA channel. This register
+ * is used to specify the PaRAM Set associated with that particular DMA Channel.
+ *
+ * \param   hEdmaResMgr         [IN]    Handle to the previously opened Resource
+ *                                      Manager Instance.
+ * \param   channelId           [IN]    Previously allocated DMA Channel on which
+ *                                      Transfer will occur.
+ * \param   paRAMId             [IN]    Previously allocated PaRAM Set which
+ *                                      needs to be associated with the dma channel.
+ *
+ * \return  EDMA3_RM_SOK or EDMA_RM Error Code
+ *
+ * \note    This API is useful only for the EDMA3 Controllers which have a
+ *          register for mapping a DMA Channel to a particular PaRAM Set
+ *          (DCHMAP register).
+ *          On platforms where this feature is not supported, this API
+ *          returns error code: EDMA3_RM_E_FEATURE_UNSUPPORTED.
+ *          This function is re-entrant for unique channelId. It is
+ *          non-re-entrant for same channelId values.
+ */
+EDMA3_RM_Result EDMA3_RM_mapEdmaChannel (EDMA3_RM_Handle hEdmaResMgr,
+                                        uint32_t channelId,
+                                        uint32_t paRAMId);
+
+/**
+ * \brief   Bind the resources QDMA Channel and PaRAM Set. Also, Set the
+ * trigger word for the QDMA channel. Both the QDMA channel and the PaRAM set
+ * should be previously allocated. If they are not, this API will result in error.
+ *
+ * This API sets the QCHMAP register for a specific QDMA channel. This register
+ * is used to specify the PaRAM Set associated with that particular QDMA
+ * Channel along with the trigger word.
+ *
+ * \param   hEdmaResMgr     [IN]    Handle to the previously opened Resource
+ *                                  Manager Instance.
+ * \param   channelId       [IN]    Previously allocated  QDMA Channel on which
+ *                                  Transfer will occur.
+ * \param   paRAMId         [IN]    Previously allocated PaRAM Set, which needs to
+ *                                      be associated with channelId
+ * \param   trigWord        [IN]    The Trigger Word for the channel.
+ *                                  Trigger Word is the word in the PaRAM
+ *                                  Register Set which - when written to by CPU
+ *                                  -will start the QDMA transfer automatically
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function is re-entrant for unique channelId. It is non-re-entrant
+ *          for same channelId values.
+ */
+EDMA3_RM_Result EDMA3_RM_mapQdmaChannel (EDMA3_RM_Handle hEdmaResMgr,
+                                        uint32_t channelId,
+                                        uint32_t paRAMId,
+                                        EDMA3_RM_QdmaTrigWord trigWord);
+
+/**
+ * \brief   Set the Channel Controller (CC) Register value
+ *
+ * \param   hEdmaResMgr     [IN]    Handle to the previously opened Resource
+ *                                  Manager Instance.
+ * \param   regOffset       [IN]    CC Register offset whose value needs to be
+ *                                  set. It should be word-aligned.
+ * \param   newRegValue     [IN]    New CC Register Value
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function is non re-entrant for users using the same
+ *          Resource Manager handle.
+ *          Before modifying a register, it tries to acquire a semaphore
+ *          (RM instance specific), to protect simultaneous
+ *          modification of the same register by two different users.
+ *          After the successful change, it releases the semaphore.
+ *          For users using different RM handles, this function is re-entrant.
+ */
+EDMA3_RM_Result EDMA3_RM_setCCRegister (EDMA3_RM_Handle hEdmaResMgr,
+                    uint32_t regOffset,
+                    uint32_t newRegValue);
+
+/**
+ * \brief   Get the Channel Controller (CC) Register value
+ *
+ * \param   hEdmaResMgr     [IN]        Handle to the previously opened Resource
+ *                                      Manager Instance.
+ * \param   regOffset       [IN]        CC Register offset whose value is
+ *                                      needed. It should be word-aligned.
+ * \param   regValue        [IN/OUT]    Fetched CC Register Value
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function is re-entrant.
+ */
+EDMA3_RM_Result EDMA3_RM_getCCRegister (EDMA3_RM_Handle hEdmaResMgr,
+                    uint32_t regOffset,
+                    uint32_t *regValue);
+
+/**
+ * \brief   Wait for a transfer completion interrupt to occur and clear it.
+ *
+ * This is a blocking function that returns when the IPR/IPRH bit corresponding
+ * to the tccNo specified, is SET. It clears the corresponding bit while
+ * returning also.
+ *
+ * This function waits for the specific bit indefinitely in a tight loop, with
+ * out any delay in between. USE IT CAUTIOUSLY.
+ *
+ * \param   hEdmaResMgr     [IN]        Handle to the previously opened Resource
+ *                                      Manager Instance.
+ * \param   tccNo           [IN]        TCC, specific to which the function
+ *                                      waits on a IPR/IPRH bit.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function is re-entrant for different tccNo.
+ *
+ */
+EDMA3_RM_Result EDMA3_RM_waitAndClearTcc (EDMA3_RM_Handle hEdmaResMgr,
+                    uint32_t tccNo);
+
+/**
+ * \brief   Returns the status of a previously initiated transfer.
+ *
+ * This is a non-blocking function that returns the status of a previously
+ * initiated transfer, based on the IPR/IPRH bit. This bit corresponds to
+ * the tccNo specified by the user. It clears the corresponding bit, if SET,
+ * while returning also.
+ *
+ * \param   hEdmaResMgr     [IN]        Handle to the previously opened Resource
+ *                                      Manager Instance.
+ * \param   tccNo           [IN]        TCC, specific to which the function
+ *                                      checks the status of the IPR/IPRH bit.
+ * \param   tccStatus       [IN/OUT]    Status of the transfer is returned here.
+ *                                      Returns "TRUE" if the transfer has
+ *                                      completed (IPR/IPRH bit SET),
+ *                                      "FALSE" if the transfer has not
+ *                                      completed successfully (IPR/IPRH bit
+ *                                      NOT SET).
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function is re-entrant for different tccNo.
+ */
+EDMA3_RM_Result EDMA3_RM_checkAndClearTcc (EDMA3_RM_Handle hEdmaResMgr,
+                    uint32_t tccNo,
+                    uint16_t *tccStatus);
+
+/**
+ * \brief   Copy the user specified PaRAM Set onto the PaRAM Set
+ *          associated with the logical channel (DMA/QDMA/Link).
+ *
+ * This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set
+ * associated with the logical channel. OPT field of the PaRAM Set is written
+ * first and the CCNT field is written last.
+ *
+ * Caution: It should be used carefully when programming the QDMA channels whose
+ *          trigger words are not CCNT field.
+ *
+ * \param   hEdmaResMgr     [IN]        Handle to the previously opened Resource
+ *                                      Manager Instance.
+ * \param   lChObj          [IN]        Logical Channel object for which new
+ *                                      PaRAM set is specified. User should pass
+ *                                      the resource type and id in this object.
+ * \param   newPaRAM        [IN]        PaRAM set to be copied onto existing one
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function is re-entrant for unique lChObj values. It is non-
+ *          re-entrant for same lChObj value.
+ */
+EDMA3_RM_Result EDMA3_RM_setPaRAM (EDMA3_RM_Handle hEdmaResMgr,
+                        EDMA3_RM_ResDesc *lChObj,
+                        const EDMA3_RM_PaRAMRegs *newPaRAM);
+
+/**
+ * \brief   Retrieve existing PaRAM set associated with specified logical
+ *          channel (DMA/QDMA/Link).
+ *
+ * \param   hEdmaResMgr     [IN]        Handle to the previously opened Resource
+ *                                      Manager Instance.
+ * \param   lChObj          [IN]        Logical Channel object for which the
+ *                                      PaRAM set is requested. User should pass
+ *                                      the resource type and id in this object.
+ * \param   currPaRAM       [IN/OUT]    User gets the existing PaRAM here.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function is re-entrant.
+ */
+EDMA3_RM_Result EDMA3_RM_getPaRAM (EDMA3_RM_Handle hEdmaResMgr,
+                    EDMA3_RM_ResDesc *lChObj,
+                    EDMA3_RM_PaRAMRegs *currPaRAM);
+
+/**
+ * \brief   Get the PaRAM Set Physical Address associated with a logical channel
+ *
+ * This function returns the PaRAM Set Phy Address (unsigned 32 bits).
+ * The returned address could be used by the advanced users to program the
+ * PaRAM Set directly without using any APIs.
+ *
+ * Least significant 16 bits of this address could be used to program
+ * the LINK field in the PaRAM Set.
+ * Users which program the LINK field directly SHOULD use this API
+ * to get the associated PaRAM Set address with the LINK channel.
+ *
+ * \param   hEdmaResMgr     [IN]        Handle to the previously opened Resource
+ *                                      Manager Instance.
+ * \param   lChObj          [IN]        Logical Channel object for which the
+ *                                      PaRAM set physical address is required.
+ *                                      User should pass the resource type and
+ *                                      id in this object.
+ * \param   paramPhyAddr [IN/OUT]       PaRAM Set physical address is returned
+ *                                      here.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function is re-entrant.
+ */
+EDMA3_RM_Result EDMA3_RM_getPaRAMPhyAddr(EDMA3_RM_Handle hEdmaResMgr,
+                    EDMA3_RM_ResDesc *lChObj,
+                    uint32_t *paramPhyAddr);
+
+/**
+ * \brief   Get the Channel Controller or Transfer Controller (n) Physical
+ *          Address.
+ *
+ * \param   hEdmaResMgr     [IN]        Handle to the previously opened Resource
+ *                                      Manager Instance.
+ * \param   controllerId    [IN]        Channel Controller or Transfer
+ *                                      Controller (n) for which the physical
+ *                                      address is required.
+ * \param   phyAddress      [IN/OUT]    Physical address is returned here.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function is re-entrant.
+ */
+EDMA3_RM_Result EDMA3_RM_getBaseAddress (EDMA3_RM_Handle hEdmaResMgr,
+                    EDMA3_RM_Cntrlr_PhyAddr controllerId,
+                    uint32_t *phyAddress);
+
+/**
+ * \brief   Get the SoC specific configuration structure for the EDMA3 Hardware.
+ *
+ * This API is used to fetch the global SoC specific configuration structure
+ * for the EDMA3 Hardware. It is useful for the user who has not passed
+ * this information during EDMA3_RM_create() and taken the default configuration
+ * coming along with the package.
+ *
+ * \param phyCtrllerInstId  [IN]    EDMA3 Controller Instance Id
+ *                                 (Hardware instance id, starting from 0).
+ * \param gblCfgParams      [IN/OUT]    SoC specific configuration structure for the
+ *                                  EDMA3 Hardware will be returned here.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function is re-entrant.
+ */
+EDMA3_RM_Result EDMA3_RM_getGblConfigParams (uint32_t                 phyCtrllerInstId,
+                                             EDMA3_RM_GblConfigParams *gblCfgParams);
+
+/**
+ * \brief   Get the RM Instance specific configuration structure for different
+ *           EDMA3 resources' usage (owned resources, reserved resources etc).
+ *
+ * This API is used to fetch the Resource Manager Instance specific configuration
+ * structure, for a specific shadow region. It is useful for the user who has not passed
+ * this information during EDMA3_RM_opn() and taken the default configuration
+ * coming along with the package. EDMA3 resources, owned and reserved by this RM
+ * instance, will be returned from this API.
+ *
+ * \param   hEdmaResMgr         [IN]    Handle to the previously opened Resource
+ *                                      Manager Instance.
+ * \param   instanceInitConfig      [IN/OUT]    RM Instance specific configuration
+ *                                      structure will be returned here.
+ *
+ * \return  EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function is re-entrant.
+ */
+EDMA3_RM_Result EDMA3_RM_getInstanceInitCfg (EDMA3_RM_Handle hEdmaResMgr,
+                                        EDMA3_RM_InstanceInitConfig *instanceInitConfig);
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_SYMBOL_ENUM
+ @{ */
+
+/**\enum    EDMA3_RM_IoctlCmd
+ * \brief   EDMA3 Resource Manager IOCTL commands
+ */
+typedef enum
+{
+    /* Min IOCTL */
+    EDMA3_RM_IOCTL_MIN_IOCTL = 0,
+
+    /**
+     * PaRAM Sets will be cleared OR will not be cleared
+     * during allocation, depending upon this option.
+     *
+     * For e.g.,
+     * To clear the PaRAM Sets during allocation,
+     * cmdArg = (void *)1;
+     *
+     * To NOT clear the PaRAM Sets during allocation,
+     * cmdArg = (void *)0;
+     *
+     * For all other values, it will return error.
+     *
+     * By default, PaRAM Sets will be cleared during allocation.
+     *
+     * Note: Since this enum can change the behavior how the resources are
+     * initialized during their allocation, user is adviced to not use this
+     * command while allocating the resources. User should first change the
+     * behavior of resources' initialization and then should use start
+     * allocating resources.
+     */
+    EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION,
+
+    /**
+     * To check whether PaRAM Sets will be cleared or not
+     * during allocation.
+     * If the value read is '1', it means that PaRAM Sets are getting cleared
+     * during allocation.
+     * If the value read is '0', it means that PaRAM Sets are NOT getting cleared
+     * during allocation.
+     *
+     * For e.g.,
+     * uint32_t *isParamClearingDone = (uint32_t *)cmdArg;
+     * (*isParamClearingDone) = paramClearingRequired;
+     */
+    EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION,
+
+    /**
+     * Global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets will be modified
+     * OR will not be modified during EDMA3_RM_allocLogicalChannel (), depending
+     * upon this option.
+     *
+     * For e.g.,
+     * To modify the Registers or PaRAM Sets during allocation,
+     * cmdArg = (void *)1;
+     *
+     * To NOT modify the Registers or PaRAM Sets during allocation,
+     * cmdArg = (void *)0;
+     *
+     * For all other values, it will return error.
+     *
+     * By default, Registers or PaRAM Sets will be programmed during allocation.
+     *
+     * Note: Since this enum can change the behavior how the resources are
+     * initialized during their allocation, user is adviced to not use this
+     * command while allocating the resources. User should first change the
+     * behavior of resources' initialization and then should use start
+     * allocating resources.
+     */
+    EDMA3_RM_IOCTL_SET_GBL_REG_MODIFY_OPTION,
+
+    /**
+     * To check whether Global EDMA3 registers (DCHMAP/QCHMAP) and PaRAM Sets
+     * will be programmed or not during allocation (EDMA3_RM_allocLogicalChannel ()).
+     * If the value read is '1', it means that the registers/PaRAMs are getting programmed
+     * during allocation.
+     * If the value read is '0', it means that the registers/PaRAMs are NOT getting programmed
+     * during allocation.
+     *
+     * For e.g.,
+     * uint32_t *isParamClearingDone = (uint32_t *)cmdArg;
+     * (*isParamClearingDone) = paramClearingRequired;
+     */
+    EDMA3_RM_IOCTL_GET_GBL_REG_MODIFY_OPTION,
+
+    /* Max IOCTLs */
+    EDMA3_RM_IOCTL_MAX_IOCTL
+} EDMA3_RM_IoctlCmd;
+
+/**
+@}
+*/
+
+/** @addtogroup EDMA3_LLD_RM_FUNCTION_ADVANCED
+ @{ */
+
+/**
+ *  \brief EDMA3 Resource Manager IOCTL
+ *
+ *  This function provides IOCTL functionality for EDMA3 Resource Manager
+ *
+ *  \param  hEdmaResMgr      [IN]       Handle to the previously opened Resource
+ *                                      Manager Instance.
+ *  \param  cmd             [IN]        IOCTL command to be performed
+ *  \param  cmdArg          [IN/OUT]    IOCTL command argument (if any)
+ *  \param  param           [IN/OUT]    Device/Cmd specific argument.
+ *
+ *  \return EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note For 'EDMA3_RM_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant.
+ * For 'EDMA3_RM_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for
+ * different Resource Manager Instances (handles).
+ */
+EDMA3_RM_Result EDMA3_RM_Ioctl(
+                      EDMA3_RM_Handle       hEdmaResMgr,
+                      EDMA3_RM_IoctlCmd     cmd,
+                      void                  *cmdArg,
+                      void                  *param
+                     );
+
+#define EDMA3_RM_MAX_XBAR_EVENTS (31u)
+
+/**\struct  EDMA3_RM_GblXbarToChanConfigParams
+ * \brief   Init-time Configuration structure for EDMA3
+ * controller, to provide Global SoC specific Information.
+ *
+ * This configuration structure is used to specify the EDMA3 Driver
+ * global settings, specific to the SoC. 
+ * This configuraion structure provides the details of the mapping of cross bar 
+ * events to available channels.
+ * This configuration information is SoC specific and could be provided by the
+ * user at run-time while creating the EDMA3 Driver Object, using API
+ * EDMA3_RM_initXbarEventMap. In case user doesn't provide it, 
+ * this information could be taken from the SoC specific configuration 
+ * file edma3_<SOC_NAME>_cfg.c, incase it is available.
+ */
+typedef struct  {
+    /**
+     * \brief Mapping from DMA channels to Hardware Events
+     *
+     * Each element in this array corresponds to one cross bar event and tells 
+     * whether this event is mapped to any DMA channel. That is whether any
+     * free or unused DMA channel can be mapped to this event.
+     * -1 means the cross bar event is not mapped to any DMA channel; 
+     * Any number from 0 to 63 means this event is mapped to specified channel.
+     * All channels need not be mapped, some can be free also.
+     * For the cross bar event mapped to DMA channel, appropriate Control Config 
+     * register of TPCC event mux register should be configured.
+     */
+    int32_t         dmaMapXbarToChan [EDMA3_RM_MAX_XBAR_EVENTS];
+    } EDMA3_RM_GblXbarToChanConfigParams;
+
+
+/**
+ * \brief  Associates cross bar mapped event to channel
+ *
+ * This function have to be defined in the configuration file. 
+ * This function will be called only if the channel requested for is beyond the
+ * maximum number of channels.
+ * This function should read from the global cross bar mapped configuration 
+ * data structure and return the mapped channel number to this event.
+ *
+ * \param   eventNum            [IN]    Event number
+ * \param   chanNum             [IN/OUT]Return the channel number to which the 
+ *                                      request event is mapped to.
+ * \param   edmaGblXbarConfig   [IN]    This is the configuration data structure
+ *                                      for mapping the events to the channel
+ *
+ * \return      EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function is re-entrant for unique event values. It is
+ *          non-re-entrant for same event values.
+ */
+typedef EDMA3_RM_Result (*EDMA3_RM_mapXbarEvtToChan) (uint32_t eventNum,
+                                                      uint32_t *chanNum,
+                 const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig);
+
+/**
+ * \brief  Writes to the cross bar mapped event to channel to system 
+ *         configuration register
+ *
+ * This function have to be defined in the configuration file. 
+ * This function will be called only if the event number requested for is 
+ * beyond the maximum number of channels and if any channel is allocated to this 
+ * event.
+ * This function should read the cross bar mapped event number and write the 
+ * allocated channel number in Control Config Event Mux registers.
+ *
+ * \param   eventNum            [IN]    Event number
+ * \param   chanNum             [IN/OUT]Return the channel number to which the 
+ *                                      request event is mapped to.
+ *
+ * \return      EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function is re-entrant for unique event values. It is
+ *          non-re-entrant for same event values.
+ */
+typedef EDMA3_RM_Result (*EDMA3_RM_xbarConfigScr) (uint32_t eventNum,
+                                                   uint32_t chanNum);
+
+/**
+ * \brief  Initialize the cross bar mapped event to channel function
+ *
+ * This API provides interface to associate the cross bar mapped event to edma 
+ * channel in the driver. 
+ * This function will called by the application during initilization.
+ * User could pass the application specific configuration structure
+ * during init-time. In case user doesn't provide it, this information could
+ * be taken from the SoC specific configuration file edma3_<SOC_NAME>_cfg.c,
+ * in case it is available.
+ * \param   hEdma               [IN]    Handle to the EDMA Driver Instance.
+ * \param   edmaGblXbarConfig   [IN]    This is the configuration data structure
+ *                                      for mapping the events to the channel
+ * \param   mapXbarEvtFunc      [IN]    This is the user defined function for 
+ *                                      mapping the cross bar event to channel.
+ *
+ * \return      EDMA3_RM_SOK or EDMA3_RM Error Code
+ *
+ * \note    This function disables the global interrupts (by calling API
+ *          edma3OsProtectEntry with protection level
+ *          EDMA3_OS_PROTECT_INTERRUPT) while modifying the global data
+ *          structures, to make it re-entrant.
+ */
+EDMA3_RM_Result EDMA3_RM_initXbarEventMap (EDMA3_RM_Handle hEdma,
+                 const EDMA3_RM_GblXbarToChanConfigParams * edmaGblXbarConfig,
+                 EDMA3_RM_mapXbarEvtToChan mapXbarEvtFunc,
+                 EDMA3_RM_xbarConfigScr configXbarScr);
+
+
+
+/**
+@}
+*/
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif    /* _EDMA3_RM_H_ */
diff --git a/debian/edma3/usr/share/doc/edma3/README.Debian b/debian/edma3/usr/share/doc/edma3/README.Debian
new file mode 100644 (file)
index 0000000..3533f40
--- /dev/null
@@ -0,0 +1,4 @@
+EDMA3 for Debian
+--------------
+
+ -- Hao Zhang <hzhang@ti.com>  Tue, 20 Aug 2013 13:55:04 -0400
diff --git a/debian/edma3/usr/share/doc/edma3/changelog.Debian.gz b/debian/edma3/usr/share/doc/edma3/changelog.Debian.gz
new file mode 100644 (file)
index 0000000..6ce8f93
Binary files /dev/null and b/debian/edma3/usr/share/doc/edma3/changelog.Debian.gz differ
diff --git a/debian/edma3/usr/share/doc/edma3/copyright b/debian/edma3/usr/share/doc/edma3/copyright
new file mode 100644 (file)
index 0000000..4882ede
--- /dev/null
@@ -0,0 +1,39 @@
+Format: http://www.debian.org/doc/packaging-manuals/copyright-format/1.0/
+Upstream-Name: edma3 
+Source: <https://gitorious.design.ti.com/+edma3-lld-developers/edma3/edma3_lld_development>
+
+Files: *
+(C) Copyright 2013, Texas Instruments, Inc.
+
+Redistribution and use in source and binary forms, with or without 
+modification, are permitted provided that the following conditions 
+are met:
+
+  Redistributions of source code must retain the above copyright 
+  notice, this list of conditions and the following disclaimer.
+
+  Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the 
+  documentation and/or other materials provided with the   
+  distribution.
+
+  Neither the name of Texas Instruments Incorporated nor the names of
+  its contributors may be used to endorse or promote products derived
+  from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+# Please also look if there are files or directories which have a
+# different copyright/license attached and list them here.
+# Please avoid to pick license terms that are more restrictive than the
+# packaged work, as it may make Debian's contributions unacceptable upstream.
diff --git a/debian/files b/debian/files
new file mode 100644 (file)
index 0000000..3525301
--- /dev/null
@@ -0,0 +1 @@
+edma3_01.00.00.00-0ubuntu1~ppa2_armhf.deb admin extra
diff --git a/debian/install b/debian/install
new file mode 100644 (file)
index 0000000..2feecc9
--- /dev/null
@@ -0,0 +1,2 @@
+packages/ti/sdo/edma3/drv/*.h  /usr/include
+packages/ti/sdo/edma3/rm/*.h   /usr/include
diff --git a/debian/rules b/debian/rules
new file mode 100755 (executable)
index 0000000..21dd5d2
--- /dev/null
@@ -0,0 +1,20 @@
+#!/usr/bin/make -f
+# -*- makefile -*-
+# Sample debian/rules that uses debhelper.
+# This file was originally written by Joey Hess and Craig Small.
+# As a special exception, when this file is copied by dh-make into a
+# dh-make output file, you may use that output file without restriction.
+# This special exception was added by Craig Small in version 0.37 of dh-make.
+
+# Uncomment this to turn on verbose mode.
+export DH_VERBOSE=1
+export ROOTDIR=$(PWD)
+export INTERNAL_SW_ROOT=$(ROOTDIR)
+export CROSSCC=gcc
+export CROSSAR=ar
+export CROSSLNK=gcc
+%:
+       dh $@ 
+
+override_dh_auto_build:
+       $(MAKE) -C packages PLATFORM=tci6636k2h-evm TARGET=a15 TOOLCHAIN_a15=GCC FORMAT=ELF
diff --git a/examples/edma3_driver/evmC66AK2E/makefile b/examples/edma3_driver/evmC66AK2E/makefile
new file mode 100644 (file)
index 0000000..aa8f3c0
--- /dev/null
@@ -0,0 +1,35 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_EVMc66ak2e_sample
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files 
+#  need to be included for this component
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_c66ak2e_st_sample.cfg
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
+              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
+              qdma_link_test.c
+CFLAGS_LOCAL_COMMON = 
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example: 
+#   SRCS_<core/SoC/platform-name> = 
+#   CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk 
+#     and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/examples/edma3_driver/evmC66AK2E/maketemp_configuro_cmd_c6xdsp.bat b/examples/edma3_driver/evmC66AK2E/maketemp_configuro_cmd_c6xdsp.bat
new file mode 100644 (file)
index 0000000..52bce55
--- /dev/null
@@ -0,0 +1 @@
+C:/ti/xdctools_3_25_04_88/xs xdc.tools.configuro --generationOnly -o obj/c66ak2e-evm/c6xdsp/release/edma3_drv_EVMc66ak2e_sample_configuro -t ti.targets.elf.C66 -p ti.platforms.evmC66AK2E -r release -c C:/ti/ccsv5/tools/compiler/c6000_7.4.2 -b C:/data/project/edma3-lld/edma3_lld_development/packages/_config.bld rtsc_config/edma3_drv_bios6_c66ak2e_st_sample.cfg
diff --git a/examples/edma3_driver/evmC66AK2E/rtsc_config/.ccsproject b/examples/edma3_driver/evmC66AK2E/rtsc_config/.ccsproject
new file mode 100644 (file)
index 0000000..4472703
--- /dev/null
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<?ccsproject version="1.0"?>
+<projectOptions>
+       <deviceVariant value="com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+       <deviceEndianness value="little"/>
+       <codegenToolVersion value="6.1.10"/>
+       <linkerCommandFile value=""/>
+       <rts value="rts64plus.lib"/>
+       <defaultAssemblyOnly value="false"/>
+       <deviceFamily value="C6000"/>
+       <isTargetManual value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/evmC66AK2E/rtsc_config/.cdtbuild b/examples/edma3_driver/evmC66AK2E/rtsc_config/.cdtbuild
new file mode 100644 (file)
index 0000000..34e7683
--- /dev/null
@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="edma3_drv_bios6_c66ak2e_st_sample_configuration.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.342693649" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType">
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" errorParsers="com.ti.ccstudio.errorparser.CoffErrorParser;com.ti.ccstudio.errorparser.AsmErrorParser;com.ti.ccstudio.errorparser.LinkErrorParser;org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.VCErrorParser" id="com.ti.ccstudio.buildDefinitions.C6000.Release.943131545" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Release">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain.1563963858" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1134204148">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1154018327" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.11" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1883300211" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC67xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.15.02.62"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.00.06.eng;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1134204148" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH.1770670681" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value="&quot;${BIOS_CG_ROOT}/packages&quot;"/>
+<listOptionValue builtIn="false" value="&quot;../../../../../packages&quot;"/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR.1246521365" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR" value="&quot;configPkg&quot;" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET.837994107" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET" value="ti.targets.C64P" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM.1571201647" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM" value="ti.platforms.evmC66AK2E" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR.1365815017" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR" value="&quot;${CG_TOOL_ROOT}&quot;" valueType="string"/>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="cmd" artifactName="configPkg/linker" description="" errorParsers="com.ti.ccstudio.errorparser.CoffErrorParser;com.ti.ccstudio.errorparser.AsmErrorParser;com.ti.ccstudio.errorparser.LinkErrorParser;org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.890447493" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1970878876">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.366366805" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.11" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.699258970" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>
+<listOptionValue builtIn="false" value="XDC_VERSION=3.15.02.62"/>
+<listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.DSPBIOS:6.21.00.06.eng;"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+</option>
+<tool id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.1970878876" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool">
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH.1202211094" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.XDC_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value="&quot;${BIOS_CG_ROOT}/packages&quot;"/>
+<listOptionValue builtIn="false" value="&quot;../../../../../packages&quot;"/>
+</option>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR.325184681" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.OUTPUT_DIR" value="&quot;configPkg&quot;" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET.1214798586" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.TARGET" value="ti.targets.C64P" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM.973623826" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.PLATFORM" value="ti.platforms.evmC66AK2E" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.BUILD_PROFILE.223734638" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.BUILD_PROFILE" value="debug" valueType="string"/>
+<option id="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR.1984079746" superClass="com.ti.rtsc.buildDefinitions.XDC_3.15.tool.CODEGEN_TOOL_DIR" value="&quot;${CG_TOOL_ROOT}&quot;" valueType="string"/>
+</tool>
+<macros/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/evmC66AK2E/rtsc_config/.cdtproject b/examples/edma3_driver/evmC66AK2E/rtsc_config/.cdtproject
new file mode 100644 (file)
index 0000000..69c6890
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.rtsc.xdctools.buildDefinitions.XDC.XDCROOT_CONTAINER"/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/evmC66AK2E/rtsc_config/.cproject b/examples/edma3_driver/evmC66AK2E/rtsc_config/.cproject
new file mode 100644 (file)
index 0000000..c6efa95
--- /dev/null
@@ -0,0 +1,79 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+       <storageModule configRelations="2" moduleId="org.eclipse.cdt.core.settings">
+               <cconfiguration id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688">
+                       <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                               <externalSettings/>
+                               <extensions>
+                                       <extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+                                       <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                                       <extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                                       <extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                                       <extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                                       <extension id="org.eclipse.rtsc.xdctools.parsers.ErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                                       <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                                       <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                                       <extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                                       <extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                               </extensions>
+                       </storageModule>
+                       <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                               <configuration artifactExtension="cmd" artifactName="configPkg/linker" buildProperties="" description="" errorParsers="com.ti.ccstudio.errorparser.CoffErrorParser;com.ti.ccstudio.errorparser.AsmErrorParser;com.ti.ccstudio.errorparser.LinkErrorParser;org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug">
+                                       <folderInfo id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688.6510111" name="/" resourcePath="">
+                                               <toolChain id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.DebugToolchain.1936320626" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.DebugToolchain" targetTool="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.1880121928">
+                                                       <option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.761440051" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+                                                               <listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC66xxDevice"/>
+                                                               <listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+                                                               <listOptionValue builtIn="false" value="OUTPUT_FORMAT=ELF"/>
+                                                               <listOptionValue builtIn="false" value="CCS_MBS_VERSION=5.1.0.01"/>
+                                                               <listOptionValue builtIn="false" value="RTSC_MBS_VERSION=2.2.0"/>
+                                                               <listOptionValue builtIn="false" value="XDC_VERSION=3.25.4.88"/>
+                                                               <listOptionValue builtIn="false" value="RTSC_PRODUCTS=com.ti.rtsc.SYSBIOS:6.37.0.16_eng;"/>
+                                                               <listOptionValue builtIn="false" value="INACTIVE_REPOS="/>
+                                                               <listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>
+                                                               <listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+                                                               <listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+                                                               <listOptionValue builtIn="false" value="PROJECT_KIND=org.eclipse.rtsc.xdctools.buildDefinitions.XDC.ProjectKind_Configuration"/>
+                                                               <listOptionValue builtIn="false" value="OUTPUT_TYPE=rtscConfiguration"/>
+                                                       </option>
+                                                       <option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.773801436" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="7.4.2" valueType="string"/>
+                                                       <targetPlatform id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.targetPlatformDebug.542502056" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.targetPlatformDebug"/>
+                                                       <builder buildPath="${BuildDirectory}" id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.builderDebug.259721414" keepEnvironmentInBuildfile="false" name="GNU Make" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.builderDebug"/>
+                                                       <tool id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.1880121928" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool">
+                                                               <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH.175119947" name="Package repositories (--xdcpath)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH" valueType="stringList">
+                                                                       <listOptionValue builtIn="false" value="&quot;${BIOS_CG_ROOT}/packages&quot;"/>
+                                                                       <listOptionValue builtIn="false" value="&quot;${TARGET_CONTENT_BASE}&quot;"/>
+                                                                       <listOptionValue builtIn="false" value="&quot;${COM_TI_RTSC_SYSBIOS_INSTALL_DIR}/packages&quot;"/>
+                                                                       <listOptionValue builtIn="false" value="&quot;C:\data\project\edma3-lld\edma3_lld_development&quot;"/>
+                                                               </option>
+                                                               <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR.1107991821" name="Output directory (-o)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.OUTPUT_DIR" value="&quot;configPkg&quot;" valueType="string"/>
+                                                               <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET.1832288131" name="Target (-t)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET" value="ti.targets.elf.C66" valueType="string"/>
+                                                               <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM.449927550" name="Platform (-p)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM" value="ti.platforms.evmC66AK2E" valueType="string"/>
+                                                               <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM_RAW.681528462" name="Platform (-p)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM_RAW" value="ti.platforms.evmC66AK2E" valueType="string"/>
+                                                               <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.BUILD_PROFILE.2128603471" name="Build-profile (-r)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.BUILD_PROFILE" value="debug" valueType="string"/>
+                                                               <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR.753157724" name="Compiler tools directory (-c)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR" value="&quot;${CG_TOOL_ROOT}&quot;" valueType="string"/>
+                                                       </tool>
+                                               </toolChain>
+                                       </folderInfo>
+                               </configuration>
+                       </storageModule>
+                       <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+               </cconfiguration>
+       </storageModule>
+       <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+               <project id="edma3_drv_bios6_c66ak2e_st_sample_configuration.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.342693649" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType"/>
+       </storageModule>
+       <storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+               <project-mappings>
+                       <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.asmSource" language="com.ti.ccstudio.core.TIASMLanguage"/>
+                       <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.ti.ccstudio.core.TIGCCLanguage"/>
+                       <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.ti.ccstudio.core.TIGCCLanguage"/>
+                       <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/>
+                       <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.ti.ccstudio.core.TIGPPLanguage"/>
+               </project-mappings>
+       </storageModule>
+       <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+       <storageModule moduleId="scannerConfiguration"/>
+</cproject>
diff --git a/examples/edma3_driver/evmC66AK2E/rtsc_config/.project b/examples/edma3_driver/evmC66AK2E/rtsc_config/.project
new file mode 100644 (file)
index 0000000..e5da1d2
--- /dev/null
@@ -0,0 +1,84 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+       <name>edma3_drv_bios6_c66ak2e_st_sample_configuration</name>
+       <comment></comment>
+       <projects>
+       </projects>
+       <buildSpec>
+               <buildCommand>
+                       <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+                       <arguments>
+                               <dictionary>
+                                       <key>?name?</key>
+                                       <value></value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.append_environment</key>
+                                       <value>true</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+                                       <value>all</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.buildArguments</key>
+                                       <value>-k</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.buildCommand</key>
+                                       <value>${CCS_INSTALL_ROOT}/utils/gmake/gmake</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.buildLocation</key>
+                                       <value>${workspace_loc:/edma3_drv_bios6_c66ak2e_st_sample_configuration/Debug}</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+                                       <value>clean</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.contents</key>
+                                       <value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+                                       <value>true</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+                                       <value>true</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.enableFullBuild</key>
+                                       <value>true</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+                                       <value>all</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.stopOnError</key>
+                                       <value>true</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+                                       <value>true</value>
+                               </dictionary>
+                       </arguments>
+               </buildCommand>
+               <buildCommand>
+                       <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+                       <triggers>full,incremental,</triggers>
+                       <arguments>
+                       </arguments>
+               </buildCommand>
+       </buildSpec>
+       <natures>
+               <nature>com.ti.ccstudio.core.ccsNature</nature>
+               <nature>org.eclipse.rtsc.xdctools.buildDefinitions.XDC.xdcNature</nature>
+               <nature>org.eclipse.cdt.core.cnature</nature>
+               <nature>org.eclipse.cdt.core.ccnature</nature>
+               <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+               <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+       </natures>
+</projectDescription>
diff --git a/examples/edma3_driver/evmC66AK2E/rtsc_config/.settings/org.eclipse.cdt.codan.core.prefs b/examples/edma3_driver/evmC66AK2E/rtsc_config/.settings/org.eclipse.cdt.codan.core.prefs
new file mode 100644 (file)
index 0000000..f653028
--- /dev/null
@@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+inEditor=false
+onBuild=false
diff --git a/examples/edma3_driver/evmC66AK2E/rtsc_config/.settings/org.eclipse.cdt.debug.core.prefs b/examples/edma3_driver/evmC66AK2E/rtsc_config/.settings/org.eclipse.cdt.debug.core.prefs
new file mode 100644 (file)
index 0000000..2adc7b1
--- /dev/null
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker
diff --git a/examples/edma3_driver/evmC66AK2E/rtsc_config/.settings/org.eclipse.core.resources.prefs b/examples/edma3_driver/evmC66AK2E/rtsc_config/.settings/org.eclipse.core.resources.prefs
new file mode 100644 (file)
index 0000000..093dbb9
--- /dev/null
@@ -0,0 +1,6 @@
+eclipse.preferences.version=1
+encoding//Debug/makefile=UTF-8
+encoding//Debug/objects.mk=UTF-8
+encoding//Debug/sources.mk=UTF-8
+encoding//Debug/subdir_rules.mk=UTF-8
+encoding//Debug/subdir_vars.mk=UTF-8
diff --git a/examples/edma3_driver/evmC66AK2E/rtsc_config/edma3_drv_bios6_c66ak2e_st_sample.cfg b/examples/edma3_driver/evmC66AK2E/rtsc_config/edma3_drv_bios6_c66ak2e_st_sample.cfg
new file mode 100644 (file)
index 0000000..d43196c
--- /dev/null
@@ -0,0 +1,20 @@
+/*use modules*/
+var Task = xdc.useModule ("ti.sysbios.knl.Task");
+var BIOS = xdc.useModule ("ti.sysbios.BIOS");
+var ECM = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
+var C64_Hwi = xdc.useModule ("ti.sysbios.family.c64p.Hwi");
+var Startup = xdc.useModule ("xdc.runtime.Startup");
+var System = xdc.useModule ("xdc.runtime.System");
+var Log = xdc.useModule ("xdc.runtime.Log");
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Cache = xdc.useModule('ti.sysbios.hal.Cache');
+var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');
+
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+/* USE EDMA3 Sample App */
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');
diff --git a/examples/edma3_driver/evmC66AK2E/sample_app/.ccsproject b/examples/edma3_driver/evmC66AK2E/sample_app/.ccsproject
new file mode 100644 (file)
index 0000000..4cedadf
--- /dev/null
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<?ccsproject version="1.0"?>
+<projectOptions>
+       <deviceVariant value=""/>
+       <deviceEndianness value="little"/>
+       <codegenToolVersion value="6.1.10"/>
+       <linkerCommandFile value=""/>
+       <rts value="rts64plus.lib"/>
+       <defaultAssemblyOnly value="false"/>
+       <deviceFamily value="C6000"/>
+       <isTargetManual value="false"/>
+</projectOptions>
diff --git a/examples/edma3_driver/evmC66AK2E/sample_app/.cdtbuild b/examples/edma3_driver/evmC66AK2E/sample_app/.cdtbuild
new file mode 100644 (file)
index 0000000..76ea50e
--- /dev/null
@@ -0,0 +1,94 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?fileVersion 3.1.0?>
+
+<ManagedProjectBuildInfo>
+<project id="edma3_drv_bios6_c66ak2e_st_sample.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.2056179817" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType">
+<configuration artifactExtension="out" artifactName="edma3_drv_bios6_c66ak2e_st_sample" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain.1095429107" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerDebug.1009459640">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.689753528" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.10" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1272193492" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=com.ti.ccstudio.managedbuild.core.ProjectKind_Executable"/>
+<listOptionValue builtIn="false" value="DEPENDENCIES=edma3_drv_bios6_c66ak2e_st_sample_configuration:Debug;"/>
+</option>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerDebug.82874858" name="C6000 Compiler" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerDebug">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.SILICON_VERSION.2018438805" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.SILICON_VERSION" value="64+" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.INCLUDE_PATH.1920644674" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.INCLUDE_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/include&quot;"/>
+<listOptionValue builtIn="false" value="&quot;${C6000_CG_ROOT}/include&quot;"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DIAG_WARNING.282910755" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DIAG_WARNING" valueType="stringList">
+<listOptionValue builtIn="false" value="225"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE.1133990629" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE" valueType="stringList">
+<listOptionValue builtIn="false" value="&quot;${workspace_loc:/edma3_drv_bios6_c66ak2e_st_sample_configuration/Debug/configPkg/compiler.opt}&quot;"/>
+</option>
+</tool>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerDebug.1009459640" name="C6000 Linker" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerDebug">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE.554395848" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE" value="&quot;edma3_drv_bios6_c66ak2e_st_sample.out&quot;" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE.1553639741" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE" value="&quot;edma3_drv_bios6_c66ak2e_st_sample.map&quot;" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY.1901031176" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY" valueType="libs">
+<listOptionValue builtIn="false" value="&quot;${workspace_loc:/edma3_drv_bios6_c66ak2e_st_sample_configuration/Debug/configPkg/linker.cmd}&quot;"/>
+<listOptionValue builtIn="false" value="&quot;rts64plus.lib&quot;"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH.1195541588" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH" valueType="stringList">
+<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/lib&quot;"/>
+<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/include&quot;"/>
+<listOptionValue builtIn="false" value="&quot;${C6000_CG_ROOT}/lib&quot;"/>
+<listOptionValue builtIn="false" value="&quot;${C6000_CG_ROOT}/include&quot;"/>
+</option>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<configuration artifactExtension="out" artifactName="edma3_drv_bios6_c66ak2e_st_sample" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Release.1606259107" name="Release" parent="com.ti.ccstudio.buildDefinitions.C6000.Release">
+<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain.409541288" name="TI Code Generation Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.ReleaseToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease.2086845964">
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1716500704" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="6.1.10" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1179762671" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC64xPlusDevice"/>
+<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE="/>
+<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=rts64plus.lib"/>
+<listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+<listOptionValue builtIn="false" value="CCS_MBS_VERSION=4.0.1"/>
+<listOptionValue builtIn="false" value="PROJECT_KIND=com.ti.ccstudio.managedbuild.core.ProjectKind_Executable"/>
+<listOptionValue builtIn="false" value="DEPENDENCIES=edma3_drv_bios6_c66ak2e_st_sample_configuration:Release;"/>
+</option>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerRelease.970508825" name="C6000 Compiler" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.compilerRelease">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.SILICON_VERSION.592066712" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.SILICON_VERSION" value="64+" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.INCLUDE_PATH.383955403" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.INCLUDE_PATH" valueType="includePath">
+<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/include&quot;"/>
+<listOptionValue builtIn="false" value="&quot;${C6000_CG_ROOT}/include&quot;"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DIAG_WARNING.623946889" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.DIAG_WARNING" valueType="stringList">
+<listOptionValue builtIn="false" value="225"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE.343769706" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.compilerID.CMD_FILE" valueType="stringList">
+<listOptionValue builtIn="false" value="&quot;${workspace_loc:/edma3_drv_bios6_c66ak2e_st_sample_configuration/Release/configPkg/compiler.opt}&quot;"/>
+</option>
+</tool>
+<tool id="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease.2086845964" name="C6000 Linker" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.exe.linkerRelease">
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE.500257992" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.OUTPUT_FILE" value="&quot;edma3_drv_bios6_c66ak2e_st_sample.out&quot;" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE.1657894292" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.MAP_FILE" value="&quot;edma3_drv_bios6_c66ak2e_st_sample.map&quot;" valueType="string"/>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY.452265586" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.LIBRARY" valueType="libs">
+<listOptionValue builtIn="false" value="&quot;${workspace_loc:/edma3_drv_bios6_c66ak2e_st_sample_configuration/Release/configPkg/linker.cmd}&quot;"/>
+<listOptionValue builtIn="false" value="&quot;rts64plus.lib&quot;"/>
+</option>
+<option id="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH.217717418" superClass="com.ti.ccstudio.buildDefinitions.C6000_6.1.linkerID.SEARCH_PATH" valueType="stringList">
+<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/lib&quot;"/>
+<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/include&quot;"/>
+<listOptionValue builtIn="false" value="&quot;${C6000_CG_ROOT}/lib&quot;"/>
+<listOptionValue builtIn="false" value="&quot;${C6000_CG_ROOT}/include&quot;"/>
+</option>
+</tool>
+<macros expandEnvironmentMacros="true"/>
+</toolChain>
+</configuration>
+<macros/>
+</project>
+</ManagedProjectBuildInfo>
diff --git a/examples/edma3_driver/evmC66AK2E/sample_app/.cdtproject b/examples/edma3_driver/evmC66AK2E/sample_app/.cdtproject
new file mode 100644 (file)
index 0000000..b7f8759
--- /dev/null
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.managedbuilder.core.managedMake">
+<extension id="org.eclipse.cdt.managedbuilder.core.ManagedBuildManager" point="org.eclipse.cdt.core.ScannerInfoProvider"/>
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.cdt.managedbuilder.MANAGED_CONTAINER"/>
+</item>
+</data>
+</cdtproject>
diff --git a/examples/edma3_driver/evmC66AK2E/sample_app/.cproject b/examples/edma3_driver/evmC66AK2E/sample_app/.cproject
new file mode 100644 (file)
index 0000000..a4a98e4
--- /dev/null
@@ -0,0 +1,101 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+       <storageModule configRelations="2" moduleId="org.eclipse.cdt.core.settings">
+               <cconfiguration id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823">
+                       <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+                               <macros>
+                                       <stringMacro name="EDMA3LLD_BIOS6_INSTALLDIR" type="VALUE_PATH_DIR" value="${PROJECT_ROOT}/../../../.."/>
+                               </macros>
+                               <externalSettings/>
+                               <extensions>
+                                       <extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+                                       <extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                                       <extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                                       <extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+                               </extensions>
+                       </storageModule>
+                       <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+                               <configuration artifactExtension="out" artifactName="edma3_drv_bios6_c66ak2e_st_sample" buildProperties="" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug">
+                                       <folderInfo id="com.ti.ccstudio.buildDefinitions.C6000.Debug.1445591823.1216648393" name="/" resourcePath="">
+                                               <toolChain id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.DebugToolchain.343280795" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.linkerDebug.78769747">
+                                                       <option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1510402360" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+                                                               <listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=com.ti.ccstudio.deviceModel.C6000.GenericC66xxDevice"/>
+                                                               <listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+                                                               <listOptionValue builtIn="false" value="OUTPUT_FORMAT=ELF"/>
+                                                               <listOptionValue builtIn="false" value="CCS_MBS_VERSION=5.1.0.01"/>
+                                                               <listOptionValue builtIn="false" value="LINKER_COMMAND_FILE=linker.cmd"/>
+                                                               <listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
+                                                               <listOptionValue builtIn="false" value="PROJECT_KIND=com.ti.ccstudio.managedbuild.core.ProjectKind_Executable"/>
+                                                               <listOptionValue builtIn="false" value="IS_ASSEMBLY_ONLY=false"/>
+                                                               <listOptionValue builtIn="false" value="OUTPUT_TYPE=executable"/>
+                                                       </option>
+                                                       <option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.1406215310" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="7.4.2" valueType="string"/>
+                                                       <targetPlatform id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.targetPlatformDebug.1745735202" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.targetPlatformDebug"/>
+                                                       <builder buildPath="${BuildDirectory}" id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.builderDebug.293699660" name="GNU Make.Debug" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.builderDebug"/>
+                                                       <tool id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.compilerDebug.2137008552" name="C6000 Compiler" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.compilerDebug">
+                                                               <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.SILICON_VERSION.551457588" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.SILICON_VERSION" value="6600" valueType="string"/>
+                                                               <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.DEBUGGING_MODEL.899155420" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.DEBUGGING_MODEL" value="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.DEBUGGING_MODEL.SYMDEBUG__DWARF" valueType="enumerated"/>
+                                                               <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.INCLUDE_PATH.1113404254" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.INCLUDE_PATH" valueType="includePath">
+                                                                       <listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/include&quot;"/>
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+                                                                       <listOptionValue builtIn="false" value="225"/>
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+                                                               <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.CMD_FILE.1917814471" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.CMD_FILE" valueType="stringList">
+                                                                       <listOptionValue builtIn="false" value="&quot;${workspace_loc:/edma3_drv_bios6_c66ak2e_st_sample_configuration/Debug/configPkg/compiler.opt}&quot;"/>
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+                                                       </tool>
+                                                       <tool id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.linkerDebug.78769747" name="C6000 Linker" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.linkerDebug">
+                                                               <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.linkerID.OUTPUT_FILE.486413128" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.linkerID.OUTPUT_FILE" value="&quot;edma3_drv_bios6_c66ak2e_st_sample.out&quot;" valueType="string"/>
+                                                               <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.linkerID.MAP_FILE.210555290" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.linkerID.MAP_FILE" value="&quot;edma3_drv_bios6_c66ak2e_st_sample.map&quot;" valueType="string"/>
+                                                               <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.linkerID.LIBRARY.320571423" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.linkerID.LIBRARY" valueType="libs">
+                                                                       <listOptionValue builtIn="false" value="edma3_lld_drv_sample.ae66"/>
+                                                                       <listOptionValue builtIn="false" value="edma3_lld_rm.ae66"/>
+                                                                       <listOptionValue builtIn="false" value="edma3_lld_drv.ae66"/>
+                                                                       <listOptionValue builtIn="false" value="&quot;libc.a&quot;"/>
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+                                                               <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.linkerID.SEARCH_PATH.296667581" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.linkerID.SEARCH_PATH" valueType="libPaths">
+                                                                       <listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/lib&quot;"/>
+                                                                       <listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/include&quot;"/>
+                                                                       <listOptionValue builtIn="false" value="&quot;${EDMA3_LLD_INSTALL_DIR}\packages\ti\sdo\edma3\drv\lib\66\debug&quot;"/>
+                                                                       <listOptionValue builtIn="false" value="&quot;${EDMA3_LLD_INSTALL_DIR}\packages\ti\sdo\edma3\drv\sample\lib\c66ak2e-evm\66\debug&quot;"/>
+                                                                       <listOptionValue builtIn="false" value="&quot;${EDMA3_LLD_INSTALL_DIR}\packages\ti\sdo\edma3\rm\lib\c66ak2e-evm\66\debug&quot;"/>
+                                                                       <listOptionValue builtIn="false" value="&quot;${C6000_CG_ROOT}/lib&quot;"/>
+                                                                       <listOptionValue builtIn="false" value="&quot;${C6000_CG_ROOT}/include&quot;"/>
+                                                               </option>
+                                                               <inputType id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exeLinker.inputType__CMD_SRCS.42221074" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exeLinker.inputType__CMD_SRCS"/>
+                                                               <inputType id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exeLinker.inputType__CMD2_SRCS.1832267718" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exeLinker.inputType__CMD2_SRCS"/>
+                                                               <inputType id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exeLinker.inputType__GEN_CMDS.1567406125" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exeLinker.inputType__GEN_CMDS"/>
+                                                       </tool>
+                                               </toolChain>
+                                       </folderInfo>
+                               </configuration>
+                       </storageModule>
+                       <storageModule moduleId="org.eclipse.cdt.core.externalSettings">
+                               <externalSettings containerId="edma3_drv_bios6_c66ak2e_st_sample_configuration;com.ti.ccstudio.buildDefinitions.C6000.Debug.1831950688" factoryId="org.eclipse.cdt.core.cfg.export.settings.sipplier"/>
+                       </storageModule>
+                       <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+               </cconfiguration>
+       </storageModule>
+       <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+               <project id="edma3_drv_bios6_c66ak2e_st_sample.com.ti.ccstudio.buildDefinitions.C6000.ProjectType.2056179817" name="C6000" projectType="com.ti.ccstudio.buildDefinitions.C6000.ProjectType"/>
+       </storageModule>
+       <storageModule moduleId="scannerConfiguration"/>
+       <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+       <storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+               <project-mappings>
+                       <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.asmSource" language="com.ti.ccstudio.core.TIASMLanguage"/>
+                       <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.ti.ccstudio.core.TIGCCLanguage"/>
+                       <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.ti.ccstudio.core.TIGCCLanguage"/>
+                       <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/>
+                       <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.ti.ccstudio.core.TIGPPLanguage"/>
+               </project-mappings>
+       </storageModule>
+</cproject>
diff --git a/examples/edma3_driver/evmC66AK2E/sample_app/.project b/examples/edma3_driver/evmC66AK2E/sample_app/.project
new file mode 100644 (file)
index 0000000..f3434fb
--- /dev/null
@@ -0,0 +1,142 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+       <name>edma3_drv_bios6_c66ak2e_st_sample</name>
+       <comment></comment>
+       <projects>
+               <project>edma3_drv_bios6_c66ak2e_st_sample_configuration</project>
+       </projects>
+       <buildSpec>
+               <buildCommand>
+                       <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+                       <arguments>
+                               <dictionary>
+                                       <key>?name?</key>
+                                       <value></value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.append_environment</key>
+                                       <value>true</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+                                       <value>all</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.buildArguments</key>
+                                       <value>-k</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.buildCommand</key>
+                                       <value>${CCS_INSTALL_ROOT}/utils/gmake/gmake</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.buildLocation</key>
+                                       <value>${workspace_loc:/edma3_drv_bios6_c66ak2e_st_sample/Debug}</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+                                       <value>clean</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.contents</key>
+                                       <value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+                                       <value>true</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+                                       <value>true</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.enableFullBuild</key>
+                                       <value>true</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+                                       <value>all</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.stopOnError</key>
+                                       <value>true</value>
+                               </dictionary>
+                               <dictionary>
+                                       <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+                                       <value>true</value>
+                               </dictionary>
+                       </arguments>
+               </buildCommand>
+               <buildCommand>
+                       <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+                       <triggers>full,incremental,</triggers>
+                       <arguments>
+                       </arguments>
+               </buildCommand>
+       </buildSpec>
+       <natures>
+               <nature>com.ti.ccstudio.core.ccsNature</nature>
+               <nature>org.eclipse.cdt.core.cnature</nature>
+               <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+               <nature>org.eclipse.cdt.core.ccnature</nature>
+               <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+       </natures>
+       <linkedResources>
+               <link>
+                       <name>common.c</name>
+                       <type>1</type>
+                       <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/common.c</locationURI>
+               </link>
+               <link>
+                       <name>dma_chain_test.c</name>
+                       <type>1</type>
+                       <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_chain_test.c</locationURI>
+               </link>
+               <link>
+                       <name>dma_link_test.c</name>
+                       <type>1</type>
+                       <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_link_test.c</locationURI>
+               </link>
+               <link>
+                       <name>dma_misc_test.c</name>
+                       <type>1</type>
+                       <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_misc_test.c</locationURI>
+               </link>
+               <link>
+                       <name>dma_ping_pong_test.c</name>
+                       <type>1</type>
+                       <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c</locationURI>
+               </link>
+               <link>
+                       <name>dma_poll_test.c</name>
+                       <type>1</type>
+                       <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_poll_test.c</locationURI>
+               </link>
+               <link>
+                       <name>dma_test.c</name>
+                       <type>1</type>
+                       <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_test.c</locationURI>
+               </link>
+               <link>
+                       <name>main.c</name>
+                       <type>1</type>
+                       <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/main.c</locationURI>
+               </link>
+               <link>
+                       <name>qdma_link_test.c</name>
+                       <type>1</type>
+                       <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_link_test.c</locationURI>
+               </link>
+               <link>
+                       <name>qdma_test.c</name>
+                       <type>1</type>
+                       <locationURI>EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_test.c</locationURI>
+               </link>
+       </linkedResources>
+       <variableList>
+               <variable>
+                       <name>EDMA3LLD_BIOS6_INSTALLDIR</name>
+                       <value>$%7BPARENT-4-PROJECT_LOC%7D</value>
+               </variable>
+       </variableList>
+</projectDescription>
diff --git a/examples/edma3_driver/evmC66AK2E/sample_app/.settings/org.eclipse.cdt.codan.core.prefs b/examples/edma3_driver/evmC66AK2E/sample_app/.settings/org.eclipse.cdt.codan.core.prefs
new file mode 100644 (file)
index 0000000..f653028
--- /dev/null
@@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+inEditor=false
+onBuild=false
diff --git a/examples/edma3_driver/evmC66AK2E/sample_app/.settings/org.eclipse.cdt.debug.core.prefs b/examples/edma3_driver/evmC66AK2E/sample_app/.settings/org.eclipse.cdt.debug.core.prefs
new file mode 100644 (file)
index 0000000..2adc7b1
--- /dev/null
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker
diff --git a/examples/edma3_driver/evmC66AK2E/sample_app/.settings/org.eclipse.core.resources.prefs b/examples/edma3_driver/evmC66AK2E/sample_app/.settings/org.eclipse.core.resources.prefs
new file mode 100644 (file)
index 0000000..093dbb9
--- /dev/null
@@ -0,0 +1,6 @@
+eclipse.preferences.version=1
+encoding//Debug/makefile=UTF-8
+encoding//Debug/objects.mk=UTF-8
+encoding//Debug/sources.mk=UTF-8
+encoding//Debug/subdir_rules.mk=UTF-8
+encoding//Debug/subdir_vars.mk=UTF-8
diff --git a/examples/edma3_driver/evmC66AK2E/sample_app/linker.cmd b/examples/edma3_driver/evmC66AK2E/sample_app/linker.cmd
new file mode 100644 (file)
index 0000000..5fac6ed
--- /dev/null
@@ -0,0 +1,6 @@
+
+SECTIONS
+{
+       .my_sect_iram  > L2SRAM
+       .my_sect_ddr  > L2SRAM
+}
diff --git a/examples/edma3_driver/evmC66AK2E/sample_app/macros.ini_initial b/examples/edma3_driver/evmC66AK2E/sample_app/macros.ini_initial
new file mode 100644 (file)
index 0000000..17411f4
--- /dev/null
@@ -0,0 +1,2 @@
+
+EDMA3LLD_BIOS6_INSTALLDIR    = ..\..\..\..\
diff --git a/examples/edma3_driver/evmC66AK2EBE/makefile b/examples/edma3_driver/evmC66AK2EBE/makefile
new file mode 100644 (file)
index 0000000..9d97adf
--- /dev/null
@@ -0,0 +1,35 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_EVMc66ak2ebe_sample
+
+SRCDIR = ../src
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files 
+#  need to be included for this component
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld
+
+# List all the components required by the application
+COMP_LIST_c6xdsp = edma3_lld_drv edma3_lld_rm
+
+# XDC CFG File
+XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_c66ak2ebe_st_sample.cfg
+