Merged from master, added a15 support for k2l, c66ak2e
authorIvan Pang <i-pang@ti.com>
Mon, 6 Jan 2014 23:18:23 +0000 (18:18 -0500)
committerIvan Pang <i-pang@ti.com>
Mon, 6 Jan 2014 23:18:23 +0000 (18:18 -0500)
56 files changed:
debian/rules
docs/EDMA3_Driver_Release_Notes.doc
docs/EDMA3_RM_Release_Notes.doc
eclipse/features/com.ti.sdo.edma3_02.11.12/feature.xml [moved from eclipse/features/com.ti.sdo.edma3_02.11.10/feature.xml with 75% similarity]
eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/Copy of toc_cdoc.xml [moved from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.10/Copy of toc_cdoc.xml with 100% similarity]
eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/META-INF/MANIFEST.MF [moved from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.10/META-INF/MANIFEST.MF with 69% similarity]
eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/plugin.xml [moved from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.10/plugin.xml with 83% similarity]
eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/toc_cdoc.xml [moved from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.10/toc_cdoc.xml with 98% similarity]
eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/toc_top.xml [moved from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.10/toc_top.xml with 93% similarity]
examples/edma3_driver/evmtda2xx/dsp_timer.c [new file with mode: 0644]
examples/edma3_driver/evmtda2xx/makefile
examples/edma3_driver/evmtda2xx/rtsc_config/custom_config.bld
examples/edma3_driver/evmtda2xx/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg
examples/edma3_driver/evmtda2xx/rtsc_config/platform.xs
examples/edma3_driver/evmtda2xx_EVE/Readme.txt [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_EVE/eve_mmu.c [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_EVE/makefile [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_EVE/rtsc_config/app_mem_seg_placement.cfg [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_EVE/rtsc_config/custom_config.bld [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_EVE/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_EVE/rtsc_config/mem_segment_definition.xs [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_EVE/rtsc_config/platform.xs [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_EVE/sample_app/linker.cmd [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_M4/makefile
examples/edma3_driver/evmtda2xx_M4/rtsc_config/platform.xs
examples/edma3_driver/evmtda2xx_M4/sample_app/linker.cmd
examples/edma3_user_space_driver/evmC66AK2E/evmC66AK2ESample.c [new file with mode: 0644]
examples/edma3_user_space_driver/evmC66AK2E/makefile [new file with mode: 0755]
examples/edma3_user_space_driver/evmTCI6630K2L/evmTCI6630K2LSample.c [new file with mode: 0644]
examples/edma3_user_space_driver/evmTCI6630K2L/makefile [new file with mode: 0755]
makerules/common.mk
makerules/env.mk
makerules/platform.mk
makerules/rules_GCC_a15.mk
makerules/rules_arp32.mk [new file with mode: 0644]
package.xdc
packages/component.mk
packages/makefile
packages/ti/sdo/edma3/drv/docs/EDMA3_Driver_Datasheet.doc
packages/ti/sdo/edma3/drv/docs/EDMA3_Driver_User_Guide.doc
packages/ti/sdo/edma3/drv/package.xdc
packages/ti/sdo/edma3/drv/package.xs
packages/ti/sdo/edma3/drv/sample/makefile
packages/ti/sdo/edma3/drv/sample/package.xdc
packages/ti/sdo/edma3/drv/sample/package.xs
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_int_reg.c
packages/ti/sdo/edma3/rm/docs/EDMA3_RM_Datasheet.doc
packages/ti/sdo/edma3/rm/docs/EDMA3_RM_User_Guide.doc
packages/ti/sdo/edma3/rm/package.xdc
packages/ti/sdo/edma3/rm/package.xs
packages/ti/sdo/edma3/rm/sample/package.xdc
packages/ti/sdo/edma3/rm/sample/package.xs
release_notes_edma3_lld.html
software-manifest.doc

index d7bb410beb7ae7c6f854ebf41f79dc01b2678c1e..21dd5d2b49065ea6b8e2dab3575ab8e01ae0b841 100755 (executable)
@@ -10,9 +10,9 @@
 export DH_VERBOSE=1
 export ROOTDIR=$(PWD)
 export INTERNAL_SW_ROOT=$(ROOTDIR)
-export CC=gcc
-export AR=ar
-export LNK=gcc
+export CROSSCC=gcc
+export CROSSAR=ar
+export CROSSLNK=gcc
 %:
        dh $@ 
 
index 05f9569a2807d15037b9e269db40433e217ee344..28ce15f29f7d3c676e478d57cb4c529e42c9f1d9 100755 (executable)
Binary files a/docs/EDMA3_Driver_Release_Notes.doc and b/docs/EDMA3_Driver_Release_Notes.doc differ
index d1892a03a3ff8056e54e4d7ff68d8b48b28bb7c9..80f4a1fc01e52fe734247e92e21e657a25cc20f6 100755 (executable)
Binary files a/docs/EDMA3_RM_Release_Notes.doc and b/docs/EDMA3_RM_Release_Notes.doc differ
similarity index 75%
rename from eclipse/features/com.ti.sdo.edma3_02.11.10/feature.xml
rename to eclipse/features/com.ti.sdo.edma3_02.11.12/feature.xml
index 6854e0ca9961282905034b89ffc17ae34c4fb0cc..33ca3cbd88edd13e1d90499afc0acb253d715f5d 100644 (file)
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <feature
-      id="com.ti.sdo.edma3_02.11.10"
+      id="com.ti.sdo.edma3_02.11.12"
       label="EDMA3"
-      version="02.11.10"
+      version="02.11.12"
       provider-name="Texas Instruments">
 
    <description url="http://ti.com">
@@ -18,8 +18,8 @@
    </license>
 
    <plugin
-        id="com.ti.sdo.edma3.rtscRegistry_02.11.10"
-        version="02.11.10"
+        id="com.ti.sdo.edma3.rtscRegistry_02.11.12"
+        version="02.11.12"
         unpack="false" />
 
    <!-- ADD PLUGINS HERE -->
similarity index 69%
rename from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.10/META-INF/MANIFEST.MF
rename to eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/META-INF/MANIFEST.MF
index dc43eebfa733fb0fef39acf22e5cb7dcbba98dbe..8873f0f8780b282fe4914472752731d75a66c44c 100644 (file)
@@ -1,8 +1,8 @@
 Manifest-Version: 1.0
 Bundle-ManifestVersion: 2
-Bundle-Name: EDMA3 LLD 02.11.10 Help
-Bundle-SymbolicName: com.ti.sdo.edma3.rtscRegistry_02.11.10;singleton:=true
-Bundle-Version: 02.11.10
+Bundle-Name: EDMA3 LLD 02.11.12 Help
+Bundle-SymbolicName: com.ti.sdo.edma3.rtscRegistry_02.11.12;singleton:=true
+Bundle-Version: 02.11.12
 Bundle-Activator: org.eclipse.rtsc.xdctools.ui.CCSActivator
 Bundle-Vendor: Texas Instruments
 Require-Bundle: org.eclipse.ui,
similarity index 83%
rename from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.10/plugin.xml
rename to eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/plugin.xml
index 5d3de169f74f6e2c412bd524a799948ea56a39c2..4df4c7422e28ef7ebe525b5db1aef1faaadeb8e1 100644 (file)
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="utf-8"?>
 <?eclipse version="3.2"?>
-<plugin name="EDMA3 LLD 02.11.10"
-        id="com.ti.sdo.edma3.rtscRegistry_02.11.10"
-        version="02.11.10"
+<plugin name="EDMA3 LLD 02.11.12"
+        id="com.ti.sdo.edma3.rtscRegistry_02.11.12"
+        version="02.11.12"
         provider-name="Texas Instruments">
   <extension point="org.eclipse.help.toc">
     <toc file="toc_top.xml"
     <docs location="../../../" />
     <info installLocation="../../../"
           productName="EDMA3 Driver"
-          versionNumber="02.11.10"
+          versionNumber="02.11.12"
           templateRepositoryPath="../../../packages"
           templateModule="ti.sdo.edma3.templates.Edma3Template"></info>
   </extension>
   <extension point="org.eclipse.rtsc.xdctools.managedbuild.core.rtscProductTypes">
     <productType id="com.ti.sdo.edma3"
                  name="EDMA3 Low Level Driver"
-                 folderPrefix="edma3_lld_02_11_10_09"
+                 folderPrefix="edma3_lld_02_11_11_12"
                  rootMacroName="EDMA3_LLD_INSTALL_DIR" />
   </extension>
   <extension point="org.eclipse.rtsc.xdctools.managedbuild.core.rtscProducts">
     <product productTypeId="com.ti.sdo.edma3"
-             version="02.11.10" />
+             version="02.11.12" />
   </extension>
 </plugin>
similarity index 98%
rename from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.10/toc_cdoc.xml
rename to eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/toc_cdoc.xml
index 187f16051e96def151a9664a2679619331ab2704..8f6476097f615dbe088b638e6904ced201443a17 100644 (file)
@@ -9,4 +9,4 @@
     <topic class="toc-id" label="EDMA3 Resource Manager" href="packages/ti/sdo/edma3/rm/docs/html/index.html"
             title="EDMA3 Resource Manager">
     </topic>
-</toc>
\ No newline at end of file
+</toc>
similarity index 93%
rename from eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.10/toc_top.xml
rename to eclipse/plugins/com.ti.sdo.edma3.rtscRegistry_02.11.12/toc_top.xml
index 72635698feeca43065ef20d0b3553d217c25bb21..041b0a225c1a495b7a76fb6a37b5f1a69a974104 100644 (file)
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8"?>
 <?NLS TYPE="org.eclipse.help.toc"?>
-<toc label="EDMA3 Low Level Driver 02.11.10 Help">
+<toc label="EDMA3 Low Level Driver 02.11.12 Help">
   <topic label="Release Notes"
          href="release_notes_edma3_lld.html" />
   <topic label="EDMA3 Driver User Guide"
diff --git a/examples/edma3_driver/evmtda2xx/dsp_timer.c b/examples/edma3_driver/evmtda2xx/dsp_timer.c
new file mode 100644 (file)
index 0000000..e4d2e5b
--- /dev/null
@@ -0,0 +1,50 @@
+/*\r
+ * dsp_timer.c\r
+ *\r
+ * This file contains the test / demo code to demonstrate the EDMA3 driver\r
+ * functionality on DSP/BIOS 6.\r
+ *\r
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ *  Redistribution and use in source and binary forms, with or without\r
+ *  modification, are permitted provided that the following conditions\r
+ *  are met:\r
+ *\r
+ *    Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ *    Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the\r
+ *    distribution.\r
+ *\r
+ *    Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#include <ti/sysbios/knl/Clock.h>\r
+\r
+/*\r
+ * mainDsp1TimerTick()   Enable Timer Tick.\r
+ * The DSP timer does not run when\r
+ * the host (A15) is halted because of the emulation suspend signal.\r
+ */\r
+void mainDsp1TimerTick(UArg arg)\r
+{\r
+    Clock_tick();\r
+}\r
index 7a22edc10b98167ad957f61313d16aa69c626f67..7f7dbec90f261d03e359d470272d6dde6aa1ac0d 100644 (file)
@@ -17,12 +17,12 @@ XDC_CFG_FILE_c6xdsp = rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg
 
 CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld
 
-PLATFORM_XDC_CUSTOM = ti.platforms.simVayu:DSP_1
+PLATFORM_XDC_CUSTOM = ti.platforms.evmDRA7XX:DSP_1
 
 # Common source files and CFLAGS across all platforms and cores
 SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \
               dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \
-              qdma_link_test.c
+              qdma_link_test.c dsp_timer.c
 CFLAGS_LOCAL_COMMON = -DBUILD_TDA2XX_DSP
 
 # Core/SoC/platform specific source files and CFLAGS
index ba44d33045257d4523b64b3dc676ba0c6fef12e5..75b856a15ae74c3f27431fdd8ff3d7603aea121e 100644 (file)
  */
 
 /* load the required modules for the configuration */
-var C64P = xdc.useModule('ti.targets.C64P');
-var C64Pe = xdc.useModule('ti.targets.C64P_big_endian');
-var C674 = xdc.useModule('ti.targets.C674');
-var C64P_ELF = xdc.useModule('ti.targets.elf.C64P');
-var C64Pe_ELF = xdc.useModule('ti.targets.elf.C64P_big_endian');
-var C674_ELF = xdc.useModule('ti.targets.elf.C674');
-var C66 = xdc.useModule('ti.targets.elf.C66');
+
+var platform_xs = xdc.loadCapsule("platform.xs");
+
+/**********************************c66******************************/
+var C66_ELF = xdc.useModule('ti.targets.elf.C66');
+
+C66_ELF.rootDir = java.lang.System.getenv("CGTOOLS_ELF");
+
+C66_ELF.ccOpts.suffix += " -mi10 -mo --symdebug:none -O3";
+
+/* linker options */
+
+C66_ELF.lnkOpts.suffix += " --zero_init=off ";
+C66_ELF.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";
+
+C66_ELF.platforms = ["ti.platforms.evmDRA7XX:DSP_1"];
+
+C66_ELF.platform = C66_ELF.platforms[0];
+/**********************************c66******************************/
+
+/**********************************c66******************************/
 var C66e = xdc.useModule('ti.targets.elf.C66_big_endian');
-var Arm = xdc.useModule('ti.targets.arm.elf.Arm9');
-var cortexA8 = xdc.useModule('ti.targets.arm.elf.A8F');
-//var C64T_ELF = xdc.useModule('ti.targets.elf.C64T');
-var M3 = xdc.useModule('ti.targets.arm.elf.M3');
-
-/* compiler paths for the CCS4.0                   */
-var cgtools = java.lang.System.getenv("CGTOOLS");
-var cgtools_elf = java.lang.System.getenv("CGTOOLS_ELF");
-var armcgtools = java.lang.System.getenv("TMS470_CGTOOLS");
-
-C64P.rootDir = cgtools;
-C64Pe.rootDir = cgtools;
-C674.rootDir = cgtools;
-C64P_ELF.rootDir = cgtools_elf;
-//C64T_ELF.rootDir = cgtools_elf;
-C64Pe_ELF.rootDir = cgtools_elf;
-C674_ELF.rootDir = cgtools_elf;
-C66.rootDir = cgtools_elf;
-C66e.rootDir = cgtools_elf;
-Arm.rootDir = armcgtools;
-cortexA8.rootDir = armcgtools;
-M3.rootDir = armcgtools;
-
-/**********************************c674******************************/
-
-/* compiler options                                */
-C64P.ccOpts.suffix += " -mi10 -mo ";
-C64Pe.ccOpts.suffix += " -mi10 -mo -me ";
-C674.ccOpts.suffix += " -mi10 -mo ";
-C64P_ELF.ccOpts.suffix += " -mi10 -mo ";
-//C64T_ELF.ccOpts.suffix += " -mi10 -mo ";
-C64Pe_ELF.ccOpts.suffix += " -mi10 -mo -me ";
-C674_ELF.ccOpts.suffix += " -mi10 -mo ";
-C66.ccOpts.suffix += " -mi10 -mo ";
-C66e.ccOpts.suffix += " -mi10 -mo -me ";
-Arm.ccOpts.suffix += " ";
-cortexA8.ccOpts.suffix += "";
-M3.ccOpts.suffix += "";
-
-/* set default platform and list of all interested platforms */
-C64P.platforms = [
-                     "ti.platforms.evm6472",
-                     "ti.platforms.evmTCI6486",
-                 ];
-C64Pe.platforms = [
-                     "ti.platforms.evm6472",
-                     "ti.platforms.evmTCI6486",
-                 ];
-C674.platforms = [
-                     "ti.platforms.evmDA830",
-                     "ti.platforms.evm6748",
-                     "ti.platforms.evmOMAPL138",
-                     "ti.platforms.simDM8168",
-                     "ti.platforms.evmDM8168",
-                     "ti.platforms.evmDM8148",
-                 ];
-C64P_ELF.platforms = [
-                     "ti.platforms.evm6472",
-                     "ti.platforms.evmTCI6486",
-                 ];
-//C64T_ELF.platforms = [
-//                     "ti.platforms.sdp4430",
-//                 ];
-C64Pe_ELF.platforms = [
-                     "ti.platforms.evm6472",
-                     "ti.platforms.evmTCI6486",
-                 ];
-C674_ELF.platforms = [
-                     "ti.platforms.evmDA830",
-                     "ti.platforms.evm6748",
-                     "ti.platforms.evmOMAPL138",
-                     "ti.platforms.simDM8168",
-                     "ti.platforms.evmDM8168",
-                     "ti.platforms.evmDM8148",
-                 ];
-C66.platforms = [
-                     "ti.platforms.simTCI6608",
-                     "ti.platforms.simTCI6616",
-                     "ti.platforms.simTCI6614",
-                     "ti.platforms.simC6657",
-                     "ti.platforms.simKepler",
-                     "ti.platforms.evm6670",
-                     "ti.platforms.evm6678",
-                     "ti.platforms.evmTCI6614",
-                     "ti.platforms.evm6657",
-                     "ti.platforms.evmTCI6638K2K",
-                 ];
-C66e.platforms = [
-                     "ti.platforms.simTCI6608",
-                     "ti.platforms.simTCI6616",
-                     "ti.platforms.simTCI6614",
-                     "ti.platforms.simC6657",
-                     "ti.platforms.simKepler",
-                     "ti.platforms.evm6670",
-                     "ti.platforms.evm6678",
-                     "ti.platforms.evmTCI6614",
-                     "ti.platforms.evm6657",
-                     "ti.platforms.evmTCI6638K2K",
-                 ];
-Arm.platforms = [
-                     "ti.platforms.evmOMAPL138",
-                 ];
-
-cortexA8.platforms = [
-                         "ti.platforms.evmDM8148",
-                     ];
-M3.platforms = [
-                     "ti.platforms.evmTI816X",
-                 ];
-
-/* select the default platform */
-C64P.platform = C64P.platforms[0];
-C64Pe.platform = C64Pe.platforms[0];
-C674.platform = C674.platforms[0];
-C64P_ELF.platform = C64P_ELF.platforms[0];
-//C64T_ELF.platform = C64T_ELF.platforms[0];
-C64Pe_ELF.platform = C64Pe_ELF.platforms[0];
-C674_ELF.platform = C674_ELF.platforms[0];
-C66.platform = C66.platforms[0];
+
+C66e.rootDir = java.lang.System.getenv("CGTOOLS_ELF");
+
+C66e.ccOpts.suffix += " -mi10 -mo -me --symdebug:none -O3";
+
+/* linker options */
+
+C66e.lnkOpts.suffix += " --zero_init=off ";
+C66e.lnkOpts.suffix += " --dynamic --retain=_Ipc_ResetVector";
+
+C66e.platforms = ["ti.platforms.evmDRA7XX:DSP_1"];
+
 C66e.platform = C66e.platforms[0];
-Arm.platform = Arm.platforms[0];
-cortexA8.platform = cortexA8.platforms[0];
-M3.platform = M3.platforms[0];
+/**********************************c66******************************/
+
 
 /* list interested targets in Build.targets array  */
 Build.targets = [
-                  //C64T_ELF,
-                    //C64,
-                    C64P,
-                    C64Pe,
-                    //C67P,
-                    C674,
-                    C64P_ELF,
-                    C64Pe_ELF,
-                    C674_ELF,
-                    C66,
-                    C66e,
-                    Arm,
-                    cortexA8,
-                    M3,
-                  //Win32,
+                    C66_ELF,
+                    C66e
                 ];
-
-var platform_xs = xdc.loadCapsule("platform.xs");
\ No newline at end of file
index 68d843e96dfa9da3ae66d872b845435ce898f3a5..238112412095d5cc245b5c6b2e287b9ceb6695c7 100644 (file)
@@ -1,15 +1,13 @@
 /*use modules*/
 var Task = xdc.useModule ("ti.sysbios.knl.Task");
-var BIOS      = xdc.useModule ("ti.sysbios.BIOS");
-var ECM       = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
-var C64_Hwi   = xdc.useModule ("ti.sysbios.family.c64p.Hwi");
-var Startup   = xdc.useModule ("xdc.runtime.Startup");
-var System    = xdc.useModule ("xdc.runtime.System");
-var Log       = xdc.useModule ("xdc.runtime.Log");
+var BIOS = xdc.useModule ("ti.sysbios.BIOS");
+var ECM = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
 var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
-var Cache = xdc.useModule('ti.sysbios.hal.Cache');
-var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
+var Startup = xdc.useModule ("xdc.runtime.Startup");
+var System = xdc.useModule ("xdc.runtime.System");
+var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
+var halCache = xdc.useModule('ti.sysbios.hal.Cache');
+var InitXbar = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");
 
 ECM.eventGroupHwiNum[0] = 7;
 ECM.eventGroupHwiNum[1] = 8;
@@ -19,8 +17,37 @@ ECM.eventGroupHwiNum[3] = 10;
 /* USE EDMA3 Sample App */
 //xdc.loadPackage('ti.sdo.edma3.drv.sample');
 
-Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
-Timer.timerSettings[0].intNum = 14;
+halCache.CacheProxy = Cache;
+
+/***********************************************
+ *          CLOCK Module Configuraion          *
+ ***********************************************/
+var Clock = xdc.useModule("ti.sysbios.knl.Clock");
+Clock.tickMode = Clock.TickMode_PERIODIC;
+Clock.tickSource = Clock.TickSource_USER;
+
+/* allocate timer 5 to DSP1 */
+var TimerSupport = xdc.useModule('ti.sysbios.family.shared.vayu.TimerSupport');
+TimerSupport.availMask = 0x0020;
+
+/***********************************************
+*           Timer Module Configuraion         *
+***********************************************/
+/* Turn off the timer frequency check. The DSP timer does not run when
+ * the host is halted because of the emulation suspend signal.
+ */
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+
+Timer.intFreq.hi = 0;
+/* system clock runs at 38.4 MHz */
+Timer.intFreq.lo = 38400000;
+
+var timerParams = new Timer.Params();
+timerParams.period = 1000;
+timerParams.twer.ovf_wup_ena = 1;
+timerParams.tiocpCfg.emufree = 1;
+
+Timer.create(5, '&mainDsp1TimerTick', timerParams);
 
 var segPlacement = xdc.loadCapsule("app_mem_seg_placement.cfg");
 segPlacement.init();
index 8ca214377f237fbb59c20d6d0211fd558be60559..3a2cac7c04726a61a541d530dbfa95b30d71ee77 100644 (file)
@@ -13,7 +13,7 @@ var Build = xdc.useModule('xdc.bld.BuildEnvironment');
 
 var MemSegDefine = xdc.loadCapsule("mem_segment_definition.xs");
 
-Build.platformTable["ti.platforms.simVayu:IPU_1_0"] =
+Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_0"] =
 {      
        externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_0(),
        codeMemory:"CODE_CORE_IPU1_0",
@@ -21,7 +21,7 @@ Build.platformTable["ti.platforms.simVayu:IPU_1_0"] =
        stackMemory:"PRIVATE_DATA_CORE_IPU1_0"
 };
 
-Build.platformTable["ti.platforms.simVayu:IPU_1_1"] =
+Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_1"] =
 {      
        externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_1(),
        codeMemory:"CODE_CORE_IPU1_1",
@@ -29,7 +29,7 @@ Build.platformTable["ti.platforms.simVayu:IPU_1_1"] =
        stackMemory:"PRIVATE_DATA_CORE_IPU1_1"
 };
 
-Build.platformTable["ti.platforms.simVayu:DSP_1"] =
+Build.platformTable["ti.platforms.evmDRA7XX:DSP_1"] =
 {
     externalMemoryMap: MemSegDefine.getMemSegmentDefinitionDSP_1(),
     codeMemory:"CODE_CORE_DSP1",
@@ -37,7 +37,7 @@ Build.platformTable["ti.platforms.simVayu:DSP_1"] =
     stackMemory:"PRIVATE_DATA_CORE_DSP1"
 };
 
-Build.platformTable["ti.platforms.simVayu:Cortex_A15"] =
+Build.platformTable["ti.platforms.evmDRA7XX:Cortex_A15"] =
 {
     externalMemoryMap: MemSegDefine.getMemSegmentDefinitionHOST(),
     codeMemory:"CODE_CORE_HOST",
diff --git a/examples/edma3_driver/evmtda2xx_EVE/Readme.txt b/examples/edma3_driver/evmtda2xx_EVE/Readme.txt
new file mode 100644 (file)
index 0000000..5384500
--- /dev/null
@@ -0,0 +1,10 @@
+===================================================================================\r
+Running standalone example on EVE core, it is required to configure EVE mmu setting.\r
+For this gels6 is mandatory CCS_CSP_ADAS_S28_ES1.0_NDA_TRM_vA_gels6 which configures\r
+default EVE mmu setting or Customer has to configure following address mapping.\r
+\r
+EVE MMU0 TLB entry 1: 0x00000000 --> 0x40500000  : 4K Page size\r
+EVE MMU0 TLB entry 2: 0x4A000000 --> 0x4A000000  : 1M Page size\r
+EVE MMU0 TLB entry 3: 0x81000000 --> 0x81000000  : 16M Page size\r
+EVE MMU0 TLB entry 4: 0x40000000 --> 0x40000000  : 16M Page size\r
+===================================================================================
\ No newline at end of file
diff --git a/examples/edma3_driver/evmtda2xx_EVE/eve_mmu.c b/examples/edma3_driver/evmtda2xx_EVE/eve_mmu.c
new file mode 100644 (file)
index 0000000..fc8d8f2
--- /dev/null
@@ -0,0 +1,75 @@
+/*\r
+ * eve_mmu.c\r
+ *\r
+ * This file contains the test / demo code to demonstrate the EDMA3 driver\r
+ * functionality on DSP/BIOS 6.\r
+ *\r
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ *  Redistribution and use in source and binary forms, with or without\r
+ *  modification, are permitted provided that the following conditions\r
+ *  are met:\r
+ *\r
+ *    Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ *    Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the\r
+ *    distribution.\r
+ *\r
+ *    Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+/******************************************************************************\r
+*                             Macro Declarations                              *\r
+******************************************************************************/\r
+#define WR_MEM_32(addr, data)    *(unsigned int*)(addr) =(unsigned int)(data)\r
+#define RD_MEM_32(addr)          *(unsigned int*)(addr)\r
+\r
+#define MMU_BASE 0x40081000 /* EVE's view */\r
+/* #define MMU_BASE 0x42081000 */   /* MPU's view */\r
+#define TESLASS_MMU__MMU_CNTL    ( MMU_BASE + 0x44 )\r
+#define TESLASS_MMU__MMU_CAM     ( MMU_BASE + 0x58 )\r
+#define TESLASS_MMU__MMU_RAM     ( MMU_BASE + 0x5c )\r
+#define TESLASS_MMU__MMU_LOCK    ( MMU_BASE + 0x50 )\r
+#define TESLASS_MMU__MMU_LD_TLB  ( MMU_BASE + 0x54 )\r
+\r
+#define PHY_ADDR1   0x4A000000\r
+#define VIRT_ADDR1  0x4A000000\r
+\r
+/*\r
+ * eve1MmuConfig() This function does EVE MMU settings. This function is\r
+ * called from Reset Module which is defined in configuration file. \r
+ */\r
+void eveMmuConfig(void)\r
+{\r
+    /* ------------------------------------------------------------------------------------------------------- */\r
+    WR_MEM_32(TESLASS_MMU__MMU_CAM, 0x0000000c | (VIRT_ADDR1 & 0xFFFFE000));\r
+    WR_MEM_32(TESLASS_MMU__MMU_RAM, 0x000001c0 | (PHY_ADDR1  & 0xFFFFE000));\r
+\r
+    /* tlbEntry is bits 8:4\r
+    #define TESLASS_MMU__MMU_LOCK__CURRENTVICTIM          BITFIELD(8, 4) */\r
+    WR_MEM_32(TESLASS_MMU__MMU_LOCK, ((RD_MEM_32(TESLASS_MMU__MMU_LOCK)) & 0xFFFFFE0F) | ( 11 << 4 ));\r
+    WR_MEM_32(TESLASS_MMU__MMU_LD_TLB, 1 );\r
+    /* ------------------------------------------------------------------------------------------------------- */\r
+\r
+    /*Enable MMU*/\r
+    WR_MEM_32(TESLASS_MMU__MMU_CNTL, ((RD_MEM_32(TESLASS_MMU__MMU_CNTL)) & 0xFFFFFFFD) | 0x2);\r
+}\r
diff --git a/examples/edma3_driver/evmtda2xx_EVE/makefile b/examples/edma3_driver/evmtda2xx_EVE/makefile
new file mode 100644 (file)
index 0000000..07c5c87
--- /dev/null
@@ -0,0 +1,40 @@
+# Makefile for edma3 lld app\r
+\r
+APP_NAME = edma3_drv_tda2xx_sample\r
+\r
+SRCDIR = ../src .\r
+INCDIR = ../src\r
+\r
+# List all the external components/interfaces, whose interface header files \r
+#  need to be included for this component\r
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld\r
+\r
+# List all the components required by the application\r
+COMP_LIST_eve = edma3_lld_drv edma3_lld_rm\r
+\r
+# XDC CFG File\r
+XDC_CFG_FILE_eve = rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg\r
+\r
+CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld\r
+\r
+PLATFORM_XDC_CUSTOM = ti.platforms.evmDRA7XX:EVE_1\r
+\r
+# Common source files and CFLAGS across all platforms and cores\r
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \\r
+              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \\r
+              qdma_link_test.c eve_mmu.c\r
+\r
+CFLAGS_LOCAL_COMMON = -DBUILD_TDA2XX_EVE\r
+\r
+# Core/SoC/platform specific source files and CFLAGS\r
+# Example: \r
+#   SRCS_<core/SoC/platform-name> = \r
+#   CFLAGS_LOCAL_<core/SoC/platform-name> =\r
+\r
+# Include common make files\r
+include $(ROOTDIR)/makerules/common.mk\r
+\r
+# OBJs and libraries are built by using rule defined in rules_<target>.mk \r
+#     and need not be explicitly specified here\r
+\r
+# Nothing beyond this point\r
diff --git a/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/app_mem_seg_placement.cfg b/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/app_mem_seg_placement.cfg
new file mode 100644 (file)
index 0000000..d048e95
--- /dev/null
@@ -0,0 +1,49 @@
+/*******************************************************************************\r
+ *                                                                             *\r
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *\r
+ *                        ALL RIGHTS RESERVED                                  *\r
+ *                                                                             *\r
+ ******************************************************************************/\r
+\r
+/*\r
+ *   @file  app_mem_seg_placement.cfg\r
+ *\r
+ *   @brief \r
+ */\r
+\r
+function init()\r
+{\r
+    Program.sectMap[".inthandler"]              = "CODE_CORE_EVE";\r
+    Program.sectMap[".text"]                    = "CODE_CORE_EVE";\r
+    Program.sectMap[".stack"]                   = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".bss:taskStackSection"]    = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".bss"]                     = "PRIVATE_DATA_CORE_EVE";\r
+    //Program.sectMap[".bss"]                     = "DMEM";\r
+    Program.sectMap[".cinit"]                   = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".init_array"]              = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".const"]                   = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".data"]                    = "PRIVATE_DATA_CORE_EVE";\r
+    //Program.sectMap[".data"]                    = "DMEM";\r
+    Program.sectMap[".switch"]                  = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".sysmem"]                  = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".far"]                     = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".args"]                    = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".cio"]                     = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".fardata"]                 = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".rodata"]                  = "PRIVATE_DATA_CORE_EVE";\r
+    //Program.sectMap[".rodata"]                  = "DMEM";\r
+    Program.sectMap[".sysmem"]                  = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".sysmem"]                  = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".my_sect_iram"]            = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".my_sect_ddr"]             = "PRIVATE_DATA_CORE_EVE";\r
+    Program.sectMap[".vecs"]                    = "OCMC3"; //"EVE_1_VECS"; \r
+   /* Program.sectMap[".imemha"]                  = "IBUFHA";\r
+    Program.sectMap[".imemhb"]                  = "IBUFHB";\r
+    Program.sectMap[".imemla"]                  = "IBUFLA";\r
+    Program.sectMap[".imemlb"]                  = "IBUFLB";\r
+    Program.sectMap[".wmem"]                    = "WBUF";\r
+    Program.sectMap[".vcop_parameter_block"]    = "WBUF";\r
+    Program.sectMap["Cdata"]                    = "WBUF";\r
+    Program.sectMap["Udata"]                    = "WBUF";\r
+    */\r
+}\r
diff --git a/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/custom_config.bld b/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/custom_config.bld
new file mode 100644 (file)
index 0000000..45763ac
--- /dev/null
@@ -0,0 +1,6 @@
+/*\r
+ *  ======== config.bld ========\r
+ *  Sample Build configuration script\r
+ */\r
+\r
+var platform_xs = xdc.loadCapsule("platform.xs");
\ No newline at end of file
diff --git a/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg b/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/edma3_drv_bios6_tda2xx_st_sample.cfg
new file mode 100644 (file)
index 0000000..09f7b8f
--- /dev/null
@@ -0,0 +1,24 @@
+/*use modules*/\r
+var Task = xdc.useModule ("ti.sysbios.knl.Task");\r
+var BIOS      = xdc.useModule ("ti.sysbios.BIOS");\r
+var Startup   = xdc.useModule ("xdc.runtime.Startup");\r
+var System    = xdc.useModule ("xdc.runtime.System");\r
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');\r
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');\r
+var Cache       = xdc.useModule('ti.sysbios.family.arp32.Cache');\r
+var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");\r
+var Cache = xdc.useModule('ti.sysbios.family.arp32.Cache');\r
+var halCache = xdc.useModule('ti.sysbios.hal.Cache');\r
+var Reset = xdc.useModule('xdc.runtime.Reset');\r
+\r
+Reset.fxns[Reset.fxns.length++] = "&eveMmuConfig";\r
+\r
+halCache.CacheProxy = Cache;\r
+\r
+//Program.heap = 0x5000;\r
+\r
+/* USE EDMA3 Sample App */\r
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');\r
+\r
+var segPlacement = xdc.loadCapsule("app_mem_seg_placement.cfg");\r
+segPlacement.init();\r
diff --git a/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/mem_segment_definition.xs b/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/mem_segment_definition.xs
new file mode 100644 (file)
index 0000000..0e8c649
--- /dev/null
@@ -0,0 +1,311 @@
+/*******************************************************************************\r
+ *                                                                             *\r
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *\r
+ *                        ALL RIGHTS RESERVED                                  *\r
+ *                                                                             *\r
+ ******************************************************************************/\r
+\r
+/*\r
+ *  ======== mem_segment_definition.xs ========\r
+ */\r
+\r
+\r
+function getMemSegmentDefinitionIPU_1_0()\r
+{\r
+    var memory = new Array();\r
+\r
+    memory[0] = ["CODE_CORE_IPU1_0",\r
+    {\r
+          name: "CODE_CORE_IPU1_0",\r
+          base: 0x84000000,\r
+          len:  0x01000000,\r
+          space: "code",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[1] = ["PRIVATE_DATA_CORE_IPU1_0",\r
+    {\r
+          name: "PRIVATE_DATA_CORE_IPU1_0",\r
+          base: 0x85000000,\r
+          len:  0x01800000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[2] = ["HDVPSS_DESCRIPTOR_NON_CACHED",\r
+    {\r
+          name: "HDVPSS_DESCRIPTOR_NON_CACHED",\r
+          base: 0xA1800000,\r
+          len:  0x00800000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[3] = ["SHARED_MEM",\r
+    {\r
+          name: "SHARED_MEM",\r
+          base: 0xA2000000,\r
+          len:  0x01000000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[4] = ["SHARED_FRAME_BUFFER",\r
+    {\r
+          name: "SHARED_FRAME_BUFFER",\r
+          base: 0x8A000000,\r
+          len:  0x04000000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[5] = ["SHARED_CTRL",\r
+    {\r
+          name: "SHARED_CTRL",\r
+          base: 0xA0000000,\r
+          len:  0x01000000,\r
+          space: "code/data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[6] = ["SHARED_LOG_MEM",\r
+    {\r
+          name: "SHARED_LOG_MEM",\r
+          base: 0xA1000000,\r
+          len:  0x00700000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+    \r
+    return (memory);\r
+}\r
+\r
+function getMemSegmentDefinitionIPU_1_1()\r
+{\r
+    var memory = new Array();\r
+\r
+    memory[0] = ["CODE_CORE_IPU1_1",\r
+    {\r
+          name: "CODE_CORE_IPU1_1",\r
+          base: 0x86800000,\r
+          len:  0x01000000,\r
+          space: "code",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[1] = ["PRIVATE_DATA_CORE_IPU1_1",\r
+    {\r
+          name: "PRIVATE_DATA_CORE_IPU1_1",\r
+          base: 0x87800000,\r
+          len:  0x01800000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[2] = ["SHARED_MEM",\r
+    {\r
+          name: "SHARED_MEM",\r
+          base: 0xA2000000,\r
+          len:  0x01000000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[3] = ["SHARED_FRAME_BUFFER",\r
+    {\r
+          name: "SHARED_FRAME_BUFFER",\r
+          base: 0x8A000000,\r
+          len:  0x04000000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[4] = ["SHARED_CTRL",\r
+    {\r
+          name: "SHARED_CTRL",\r
+          base: 0xA0000000,\r
+          len:  0x01000000,\r
+          space: "code/data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[5] = ["SHARED_LOG_MEM",\r
+    {\r
+          name: "SHARED_LOG_MEM",\r
+          base: 0xA1000000,\r
+          len:  0x00700000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+    \r
+    return (memory);\r
+}\r
+\r
+function getMemSegmentDefinitionDSP_1()\r
+{\r
+    var memory = new Array();\r
+\r
+    memory[0] = ["CODE_CORE_DSP1",\r
+    {\r
+          name: "CODE_CORE_DSP1",\r
+          base: 0x83100000,\r
+          len:  0x00700000,\r
+          space: "code",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[1] = ["PRIVATE_DATA_CORE_DSP1",\r
+    {\r
+          name: "PRIVATE_DATA_CORE_DSP1",\r
+          base: 0x83800000,\r
+          len:  0x00800000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[2] = ["SHARED_MEM",\r
+    {\r
+          name: "SHARED_MEM",\r
+          base: 0xA2000000,\r
+          len:  0x01000000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[3] = ["SHARED_FRAME_BUFFER",\r
+    {\r
+          name: "SHARED_FRAME_BUFFER",\r
+          base: 0x8A000000,\r
+          len:  0x04000000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[4] = ["SHARED_CTRL",\r
+    {\r
+          name: "SHARED_CTRL",\r
+          base: 0xA0000000,\r
+          len:  0x01000000,\r
+          space: "code/data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[5] = ["SHARED_LOG_MEM",\r
+    {\r
+          name: "SHARED_LOG_MEM",\r
+          base: 0xA1000000,\r
+          len:  0x00700000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+    \r
+    return (memory);\r
+}\r
+\r
+function getMemSegmentDefinitionHOST()\r
+{\r
+    var memory = new Array();\r
+\r
+    memory[8] = ["CODE_CORE_HOST",\r
+    {\r
+          name: "CODE_CORE_HOST",\r
+          base: 0x89000000,\r
+          len:  0x00800000,\r
+          space: "code",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[9] = ["PRIVATE_DATA_CORE_HOST",\r
+    {\r
+          name: "PRIVATE_DATA_CORE_HOST",\r
+          base: 0x89800000,\r
+          len:  0x00800000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[10] = ["SHARED_MEM",\r
+    {\r
+          name: "SHARED_MEM",\r
+          base: 0xA2000000,\r
+          len:  0x01000000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[11] = ["SHARED_FRAME_BUFFER",\r
+    {\r
+          name: "SHARED_FRAME_BUFFER",\r
+          base: 0x8A000000,\r
+          len:  0x04000000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[12] = ["SHARED_CTRL",\r
+    {\r
+          name: "SHARED_CTRL",\r
+          base: 0xA0000000,\r
+          len:  0x01000000,\r
+          space: "code/data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[13] = ["SHARED_LOG_MEM",\r
+    {\r
+          name: "SHARED_LOG_MEM",\r
+          base: 0xA1000000,\r
+          len:  0x00700000,\r
+          space: "data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    return (memory);\r
+}\r
+\r
+function getMemSegmentDefinitionEVE()\r
+{\r
+    var memory = new Array();\r
+\r
+    memory[0] = ["EVE_1_VECS",\r
+    {\r
+          name: "EVE_1_VECS",\r
+          base: 0x81000000,\r
+          len:  0x00000100,\r
+          space: "code/data",\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[1] = ["CODE_CORE_EVE",\r
+    {\r
+          name: "CODE_CORE_EVE",\r
+          base: 0x81000100,\r
+          len:  0x0004FF00,\r
+          space: "code",\r
+          page: 1,\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[2] = ["PRIVATE_DATA_CORE_EVE",\r
+    {\r
+          name: "PRIVATE_DATA_CORE_EVE",\r
+          base: 0x81050000,\r
+          len:  0x00400000,\r
+          space: "data",\r
+          page: 1,\r
+          access: "RWX"\r
+    }];\r
+\r
+    memory[3] = ["OCMC3",\r
+    {\r
+          name: "OCMC3",\r
+          base: 0x40500000,\r
+          len:  0x00001000,\r
+          space: "data",\r
+          page: 1,\r
+          access: "RWX"\r
+    }];\r
+\r
+    return (memory);\r
+}\r
+\r
diff --git a/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/platform.xs b/examples/edma3_driver/evmtda2xx_EVE/rtsc_config/platform.xs
new file mode 100644 (file)
index 0000000..18f0831
--- /dev/null
@@ -0,0 +1,54 @@
+/*******************************************************************************\r
+ *                                                                             *\r
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com/      *\r
+ *                        ALL RIGHTS RESERVED                                  *\r
+ *                                                                             *\r
+ ******************************************************************************/\r
+\r
+/*\r
+ *  ======== platform.xs ========\r
+ */\r
+\r
+var Build = xdc.useModule('xdc.bld.BuildEnvironment'); \r
+\r
+var MemSegDefine = xdc.loadCapsule("mem_segment_definition.xs");\r
+\r
+Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_0"] =\r
+{      \r
+       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_0(),\r
+       codeMemory:"CODE_CORE_IPU1_0",\r
+       dataMemory:"PRIVATE_DATA_CORE_IPU1_0",\r
+       stackMemory:"PRIVATE_DATA_CORE_IPU1_0"\r
+};\r
+\r
+Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_1"] =\r
+{      \r
+       externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_1(),\r
+       codeMemory:"CODE_CORE_IPU1_1",\r
+       dataMemory:"PRIVATE_DATA_CORE_IPU1_1",\r
+       stackMemory:"PRIVATE_DATA_CORE_IPU1_1"\r
+};\r
+\r
+Build.platformTable["ti.platforms.evmDRA7XX:DSP_1"] =\r
+{\r
+    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionDSP_1(),\r
+    codeMemory:"CODE_CORE_DSP1",\r
+    dataMemory:"PRIVATE_DATA_CORE_DSP1",\r
+    stackMemory:"PRIVATE_DATA_CORE_DSP1"\r
+};\r
+\r
+Build.platformTable["ti.platforms.evmDRA7XX:Cortex_A15"] =\r
+{\r
+    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionHOST(),\r
+    codeMemory:"CODE_CORE_HOST",\r
+    dataMemory:"PRIVATE_DATA_CORE_HOST",\r
+    stackMemory:"PRIVATE_DATA_CORE_HOST"\r
+};\r
+\r
+Build.platformTable["ti.platforms.evmDRA7XX:EVE_1"] =\r
+{\r
+    externalMemoryMap: MemSegDefine.getMemSegmentDefinitionEVE(),\r
+    codeMemory:"CODE_CORE_EVE",\r
+    dataMemory:"PRIVATE_DATA_CORE_EVE",\r
+    stackMemory:"PRIVATE_DATA_CORE_EVE"\r
+};\r
diff --git a/examples/edma3_driver/evmtda2xx_EVE/sample_app/linker.cmd b/examples/edma3_driver/evmtda2xx_EVE/sample_app/linker.cmd
new file mode 100644 (file)
index 0000000..990cc10
--- /dev/null
@@ -0,0 +1,5 @@
+SECTIONS\r
+{\r
+//    .my_sect_iram > EXT_RAM\r
+//    .my_sect_ddr  > EXT_RAM\r
+}\r
index 1dd4798f1cb1c97b9fbafb051ea3fd23e959231b..8386b5f8a3e0f0426685f86599e18dd50f5dda2f 100644 (file)
@@ -19,11 +19,11 @@ COMP_LIST_m4 = edma3_lld_drv edma3_lld_rm
 ifeq ($(IPUCORE),1)\r
 XDC_CFG_FILE_m4 = rtsc_config/edma3_drv_bios6_tda2xx_m4_c1_st_sample.cfg\r
 CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld\r
-PLATFORM_XDC_CUSTOM = ti.platforms.simVayu:IPU_1_1\r
+PLATFORM_XDC_CUSTOM = ti.platforms.evmDRA7XX:IPU_1_1\r
 else\r
 XDC_CFG_FILE_m4 = rtsc_config/edma3_drv_bios6_tda2xx_m4_c0_st_sample.cfg\r
 CONFIG_BLD_XDC_CUSTOM = rtsc_config/custom_config.bld\r
-PLATFORM_XDC_CUSTOM = ti.platforms.simVayu:IPU_1_0\r
+PLATFORM_XDC_CUSTOM = ti.platforms.evmDRA7XX:IPU_1_0\r
 endif\r
 \r
 \r
index 8ca214377f237fbb59c20d6d0211fd558be60559..3a2cac7c04726a61a541d530dbfa95b30d71ee77 100644 (file)
@@ -13,7 +13,7 @@ var Build = xdc.useModule('xdc.bld.BuildEnvironment');
 
 var MemSegDefine = xdc.loadCapsule("mem_segment_definition.xs");
 
-Build.platformTable["ti.platforms.simVayu:IPU_1_0"] =
+Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_0"] =
 {      
        externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_0(),
        codeMemory:"CODE_CORE_IPU1_0",
@@ -21,7 +21,7 @@ Build.platformTable["ti.platforms.simVayu:IPU_1_0"] =
        stackMemory:"PRIVATE_DATA_CORE_IPU1_0"
 };
 
-Build.platformTable["ti.platforms.simVayu:IPU_1_1"] =
+Build.platformTable["ti.platforms.evmDRA7XX:IPU_1_1"] =
 {      
        externalMemoryMap: MemSegDefine.getMemSegmentDefinitionIPU_1_1(),
        codeMemory:"CODE_CORE_IPU1_1",
@@ -29,7 +29,7 @@ Build.platformTable["ti.platforms.simVayu:IPU_1_1"] =
        stackMemory:"PRIVATE_DATA_CORE_IPU1_1"
 };
 
-Build.platformTable["ti.platforms.simVayu:DSP_1"] =
+Build.platformTable["ti.platforms.evmDRA7XX:DSP_1"] =
 {
     externalMemoryMap: MemSegDefine.getMemSegmentDefinitionDSP_1(),
     codeMemory:"CODE_CORE_DSP1",
@@ -37,7 +37,7 @@ Build.platformTable["ti.platforms.simVayu:DSP_1"] =
     stackMemory:"PRIVATE_DATA_CORE_DSP1"
 };
 
-Build.platformTable["ti.platforms.simVayu:Cortex_A15"] =
+Build.platformTable["ti.platforms.evmDRA7XX:Cortex_A15"] =
 {
     externalMemoryMap: MemSegDefine.getMemSegmentDefinitionHOST(),
     codeMemory:"CODE_CORE_HOST",
index 046689c50b5f8d8549698878b3ac38a78aa6b578..c9d96b00f1c51717a0fa39f1b850051a2a42f25e 100644 (file)
@@ -1,8 +1,3 @@
-MEMORY\r
-{\r
-    OCMC_RAM : org = 0x40300000, len = 0x10000\r
-}\r
-\r
 SECTIONS\r
 {\r
 //    .my_sect_iram > EXT_RAM\r
diff --git a/examples/edma3_user_space_driver/evmC66AK2E/evmC66AK2ESample.c b/examples/edma3_user_space_driver/evmC66AK2E/evmC66AK2ESample.c
new file mode 100644 (file)
index 0000000..8c7a8c3
--- /dev/null
@@ -0,0 +1,2979 @@
+/*
+ * sample_c66ak2e_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2012-2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES                    5u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                                       1u
+//const unsigned int numDsps = NUM_DSPS;
+
+#define CGEM_REG_START                  (0x01800000)
+
+
+//extern cregister volatile unsigned int DNUM;
+#define DNUM 0
+
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
+
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+       {
+       volatile unsigned int *addr;
+       unsigned int core_no;
+
+    /* Identify the core number */
+    addr = (unsigned int *)(CGEM_REG_START+0x40000);
+    core_no = ((*addr) & 0x000F0000)>>16;
+
+       return core_no;
+       }
+
+signed char*  getGlobalAddr(signed char* addr)
+{
+    if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+    {
+        return (addr); /* The address is already a global address */
+    }
+
+    return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
+/** Whether global configuration required for EDMA3 or not.
+ * This configuration should be done only once for the EDMA3 hardware by
+ * any one of the masters (i.e. DSPs).
+ * It can be changed depending on the use-case.
+ */
+unsigned int gblCfgReqdArray [NUM_DSPS] = {
+                                                                       0,      /* DSP#0 is Master, will do the global init */
+                                                                       };
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+       {
+       return gblCfgReqdArray[dspNum];
+       }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL,NULL,NULL};
+
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u, 2u, 2u};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u, 2u, 2u};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt. Completion interrupts for all the shadow regions and all the
+ * EDMA3 controllers are captured since it is a multi-DSP platform.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+                                                                                                       {
+                                                                                                       38u, 39u, 40u, 41u,
+                                                                                                       42u, 43u, 44u, 45u,
+                                                                                                       },
+                                                                                                       {
+                                                                                                       8u, 9u, 10u, 11u,
+                                                                                                       12u, 13u, 14u, 15u,
+                                                                                                       },
+                                                                                                       {
+                                                                                                       24u, 25u, 26u, 27u,
+                                                                                                       28u, 29u, 30u, 31u,
+                                                                                                       },
+                                                                                                       {
+                                                                                                       225u, 226u, 227u, 228u,
+                                                                                                       229u, 230u, 231u, 232u,
+                                                                                                       },
+                                                                                                       {
+                                                                                                       212u, 213u, 214u, 215u,
+                                                                                                       216u, 217u, 218u, 219u,
+                                                                                                       },
+                                                                                               };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u, 220u, 207u};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] =    {
+                                                                                                       {
+                                                                                                       34u, 35u, 0u, 0u,
+                                                                                                       0u, 0u, 0u, 0u,
+                                                                                                       },
+                                                                                                       {
+                                                                                                       2u, 3u, 4u, 5u,
+                                                                                                       0u, 0u, 0u, 0u,
+                                                                                                       },
+                                                                                                       {
+                                                                                                       18u, 19u, 20u, 21u,
+                                                                                                       0u, 0u, 0u, 0u,
+                                                                                                       },
+                                                                                                       {
+                                                                                                       222u, 223u, 0u, 0u,
+                                                                                                       0u, 0u, 0u, 0u,
+                                                                                                       },
+                                                                                                       {
+                                                                                                       209u, 210u, 0u, 0u,
+                                                                                                       0u, 0u, 0u, 0u,
+                                                                                                       },
+                                                                                               };
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+       {
+               {
+               /* EDMA3 INSTANCE# 0 */
+               /** Total number of DMA Channels supported by the EDMA3 Controller */
+               64u,
+               /** Total number of QDMA Channels supported by the EDMA3 Controller */
+               8u,
+               /** Total number of TCCs supported by the EDMA3 Controller */
+               64u,
+               /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+               512u,
+               /** Total number of Event Queues in the EDMA3 Controller */
+               2u,
+               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+               2u,
+               /** Number of Regions on this EDMA3 controller */
+               8u,
+
+               /**
+                * \brief Channel mapping existence
+                * A value of 0 (No channel mapping) implies that there is fixed association
+                * for a channel number to a parameter entry number or, in other words,
+                * PaRAM entry n corresponds to channel n.
+                */
+               1u,
+
+               /** Existence of memory protection feature */
+               1u,
+
+               /** Global Register Region of CC Registers */
+               (void *)0x02700000u,
+               /** Transfer Controller (TC) Registers */
+               {
+               (void *)0x02760000u,
+               (void *)0x02768000u,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL
+               },
+               /** Interrupt no. for Transfer Completion */
+               38u,
+               /** Interrupt no. for CC Error */
+               32u,
+               /** Interrupt no. for TCs Error */
+               {
+               34u,
+               35u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               },
+
+               /**
+                * \brief EDMA3 TC priority setting
+                *
+                * User can program the priority of the Event Queues
+                * at a system-wide level.  This means that the user can set the
+                * priority of an IO initiated by either of the TCs (Transfer Controllers)
+                * relative to IO initiated by the other bus masters on the
+                * device (ARM, DSP, USB, etc)
+                */
+               {
+               0u,
+               1u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+               /**
+                * \brief To Configure the Threshold level of number of events
+                * that can be queued up in the Event queues. EDMA3CC error register
+                * (CCERR) will indicate whether or not at any instant of time the
+                * number of events queued up in any of the event queues exceeds
+                * or equals the threshold/watermark value that is set
+                * in the queue watermark threshold register (QWMTHRA).
+                */
+               {
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief To Configure the Default Burst Size (DBS) of TCs.
+                * An optimally-sized command is defined by the transfer controller
+                * default burst size (DBS). Different TCs can have different
+                * DBS values. It is defined in Bytes.
+                */
+               {
+               128u,
+               128u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief Mapping from each DMA channel to a Parameter RAM set,
+                * if it exists, otherwise of no use.
+                */
+               {
+               EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+               },
+
+                /**
+                 * \brief Mapping from each DMA channel to a TCC. This specific
+                 * TCC code will be returned when the transfer is completed
+                 * on the mapped channel.
+                 */
+               {
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+               },
+
+               /**
+                * \brief Mapping of DMA channels to Hardware Events from
+                * various peripherals, which use EDMA for data transfer.
+                * All channels need not be mapped, some can be free also.
+                */
+               {
+               0xFFFFFFFFu,
+               0x00000000u
+               }
+               },
+
+               {
+               /* EDMA3 INSTANCE# 1 */
+               /** Total number of DMA Channels supported by the EDMA3 Controller */
+               64u,
+               /** Total number of QDMA Channels supported by the EDMA3 Controller */
+               8u,
+               /** Total number of TCCs supported by the EDMA3 Controller */
+               64u,
+               /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+               512u,
+               /** Total number of Event Queues in the EDMA3 Controller */
+               4u,
+               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+               4u,
+               /** Number of Regions on this EDMA3 controller */
+               8u,
+
+               /**
+                * \brief Channel mapping existence
+                * A value of 0 (No channel mapping) implies that there is fixed association
+                * for a channel number to a parameter entry number or, in other words,
+                * PaRAM entry n corresponds to channel n.
+                */
+               1u,
+
+               /** Existence of memory protection feature */
+               1u,
+
+               /** Global Register Region of CC Registers */
+               (void *)0x02720000u,
+               /** Transfer Controller (TC) Registers */
+               {
+               (void *)0x02770000u,
+               (void *)0x02778000u,
+               (void *)0x02780000u,
+               (void *)0x02788000u,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL
+               },
+               /** Interrupt no. for Transfer Completion */
+               8u,
+               /** Interrupt no. for CC Error */
+               0u,
+               /** Interrupt no. for TCs Error */
+               {
+               2u,
+               3u,
+               4u,
+               5u,
+               0u,
+               0u,
+               0u,
+               0u,
+               },
+
+               /**
+                * \brief EDMA3 TC priority setting
+                *
+                * User can program the priority of the Event Queues
+                * at a system-wide level.  This means that the user can set the
+                * priority of an IO initiated by either of the TCs (Transfer Controllers)
+                * relative to IO initiated by the other bus masters on the
+                * device (ARM, DSP, USB, etc)
+                */
+               {
+               0u,
+               1u,
+               2u,
+               3u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+               /**
+                * \brief To Configure the Threshold level of number of events
+                * that can be queued up in the Event queues. EDMA3CC error register
+                * (CCERR) will indicate whether or not at any instant of time the
+                * number of events queued up in any of the event queues exceeds
+                * or equals the threshold/watermark value that is set
+                * in the queue watermark threshold register (QWMTHRA).
+                */
+               {
+               16u,
+               16u,
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief To Configure the Default Burst Size (DBS) of TCs.
+                * An optimally-sized command is defined by the transfer controller
+                * default burst size (DBS). Different TCs can have different
+                * DBS values. It is defined in Bytes.
+                */
+               {
+               128u,
+               128u,
+               128u,
+               128u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief Mapping from each DMA channel to a Parameter RAM set,
+                * if it exists, otherwise of no use.
+                */
+               {
+               EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+               },
+
+                /**
+                 * \brief Mapping from each DMA channel to a TCC. This specific
+                 * TCC code will be returned when the transfer is completed
+                 * on the mapped channel.
+                 */
+               {
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+               },
+
+               /**
+                * \brief Mapping of DMA channels to Hardware Events from
+                * various peripherals, which use EDMA for data transfer.
+                * All channels need not be mapped, some can be free also.
+                */
+               {
+               0xFFFFFFFFu,
+               0x00000000u
+               }
+               },
+
+               {
+               /* EDMA3 INSTANCE# 2 */
+               /** Total number of DMA Channels supported by the EDMA3 Controller */
+               64u,
+               /** Total number of QDMA Channels supported by the EDMA3 Controller */
+               8u,
+               /** Total number of TCCs supported by the EDMA3 Controller */
+               64u,
+               /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+               512u,
+               /** Total number of Event Queues in the EDMA3 Controller */
+               4u,
+               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+               4u,
+               /** Number of Regions on this EDMA3 controller */
+               8u,
+
+               /**
+                * \brief Channel mapping existence
+                * A value of 0 (No channel mapping) implies that there is fixed association
+                * for a channel number to a parameter entry number or, in other words,
+                * PaRAM entry n corresponds to channel n.
+                */
+               1u,
+
+               /** Existence of memory protection feature */
+               1u,
+
+               /** Global Register Region of CC Registers */
+               (void *)0x02740000u,
+               /** Transfer Controller (TC) Registers */
+               {
+               (void *)0x02790000u,
+               (void *)0x02798000u,
+               (void *)0x027A0000u,
+               (void *)0x027A8000u,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL
+               },
+               /** Interrupt no. for Transfer Completion */
+               24u,
+               /** Interrupt no. for CC Error */
+               16u,
+               /** Interrupt no. for TCs Error */
+               {
+               18u,
+               19u,
+               20u,
+               21u,
+               0u,
+               0u,
+               0u,
+               0u,
+               },
+
+               /**
+                * \brief EDMA3 TC priority setting
+                *
+                * User can program the priority of the Event Queues
+                * at a system-wide level.  This means that the user can set the
+                * priority of an IO initiated by either of the TCs (Transfer Controllers)
+                * relative to IO initiated by the other bus masters on the
+                * device (ARM, DSP, USB, etc)
+                */
+               {
+               0u,
+               1u,
+               2u,
+               3u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+               /**
+                * \brief To Configure the Threshold level of number of events
+                * that can be queued up in the Event queues. EDMA3CC error register
+                * (CCERR) will indicate whether or not at any instant of time the
+                * number of events queued up in any of the event queues exceeds
+                * or equals the threshold/watermark value that is set
+                * in the queue watermark threshold register (QWMTHRA).
+                */
+               {
+               16u,
+               16u,
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief To Configure the Default Burst Size (DBS) of TCs.
+                * An optimally-sized command is defined by the transfer controller
+                * default burst size (DBS). Different TCs can have different
+                * DBS values. It is defined in Bytes.
+                */
+               {
+               128u,
+               128u,
+               128u,
+               128u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief Mapping from each DMA channel to a Parameter RAM set,
+                * if it exists, otherwise of no use.
+                */
+               {
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+               },
+
+                /**
+                 * \brief Mapping from each DMA channel to a TCC. This specific
+                 * TCC code will be returned when the transfer is completed
+                 * on the mapped channel.
+                 */
+               {
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+               },
+
+               /**
+                * \brief Mapping of DMA channels to Hardware Events from
+                * various peripherals, which use EDMA for data transfer.
+                * All channels need not be mapped, some can be free also.
+                */
+               {
+               0xFFFFFFFFu,
+               0x00000000u
+               }
+               },
+
+               {
+               /* EDMA3 INSTANCE# 3 */
+               /** Total number of DMA Channels supported by the EDMA3 Controller */
+               64u,
+               /** Total number of QDMA Channels supported by the EDMA3 Controller */
+               8u,
+               /** Total number of TCCs supported by the EDMA3 Controller */
+               64u,
+               /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+               512u,
+               /** Total number of Event Queues in the EDMA3 Controller */
+               2u,
+               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+               2u,
+               /** Number of Regions on this EDMA3 controller */
+               8u,
+
+               /**
+                * \brief Channel mapping existence
+                * A value of 0 (No channel mapping) implies that there is fixed association
+                * for a channel number to a parameter entry number or, in other words,
+                * PaRAM entry n corresponds to channel n.
+                */
+               1u,
+
+               /** Existence of memory protection feature */
+               1u,
+
+               /** Global Register Region of CC Registers */
+               (void *)0x02728000u,
+               /** Transfer Controller (TC) Registers */
+               {
+               (void *)0x027B0000u,
+               (void *)0x027B8000u,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL
+               },
+               /** Interrupt no. for Transfer Completion */
+               225u,
+               /** Interrupt no. for CC Error */
+               220u,
+               /** Interrupt no. for TCs Error */
+               {
+               222u,
+               223u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               },
+
+               /**
+                * \brief EDMA3 TC priority setting
+                *
+                * User can program the priority of the Event Queues
+                * at a system-wide level.  This means that the user can set the
+                * priority of an IO initiated by either of the TCs (Transfer Controllers)
+                * relative to IO initiated by the other bus masters on the
+                * device (ARM, DSP, USB, etc)
+                */
+               {
+               0u,
+               1u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+               /**
+                * \brief To Configure the Threshold level of number of events
+                * that can be queued up in the Event queues. EDMA3CC error register
+                * (CCERR) will indicate whether or not at any instant of time the
+                * number of events queued up in any of the event queues exceeds
+                * or equals the threshold/watermark value that is set
+                * in the queue watermark threshold register (QWMTHRA).
+                */
+               {
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief To Configure the Default Burst Size (DBS) of TCs.
+                * An optimally-sized command is defined by the transfer controller
+                * default burst size (DBS). Different TCs can have different
+                * DBS values. It is defined in Bytes.
+                */
+               {
+               128u,
+               128u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief Mapping from each DMA channel to a Parameter RAM set,
+                * if it exists, otherwise of no use.
+                */
+               {
+               EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+               },
+
+                /**
+                 * \brief Mapping from each DMA channel to a TCC. This specific
+                 * TCC code will be returned when the transfer is completed
+                 * on the mapped channel.
+                 */
+               {
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+               },
+
+               /**
+                * \brief Mapping of DMA channels to Hardware Events from
+                * various peripherals, which use EDMA for data transfer.
+                * All channels need not be mapped, some can be free also.
+                */
+               {
+               0xFFFFFFFFu,
+               0x00000000u
+               }
+               },
+
+               {
+               /* EDMA3 INSTANCE# 4 */
+               /** Total number of DMA Channels supported by the EDMA3 Controller */
+               64u,
+               /** Total number of QDMA Channels supported by the EDMA3 Controller */
+               8u,
+               /** Total number of TCCs supported by the EDMA3 Controller */
+               64u,
+               /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+               512u,
+               /** Total number of Event Queues in the EDMA3 Controller */
+               2u,
+               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+               2u,
+               /** Number of Regions on this EDMA3 controller */
+               8u,
+
+               /**
+                * \brief Channel mapping existence
+                * A value of 0 (No channel mapping) implies that there is fixed association
+                * for a channel number to a parameter entry number or, in other words,
+                * PaRAM entry n corresponds to channel n.
+                */
+               1u,
+
+               /** Existence of memory protection feature */
+               1u,
+
+               /** Global Register Region of CC Registers */
+               (void *)0x02708000u,
+               /** Transfer Controller (TC) Registers */
+               {
+               (void *)0x027B8400u,
+               (void *)0x027B8800u,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL
+               },
+               /** Interrupt no. for Transfer Completion */
+               212u,
+               /** Interrupt no. for CC Error */
+               207u,
+               /** Interrupt no. for TCs Error */
+               {
+               209u,
+               210u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               },
+
+               /**
+                * \brief EDMA3 TC priority setting
+                *
+                * User can program the priority of the Event Queues
+                * at a system-wide level.  This means that the user can set the
+                * priority of an IO initiated by either of the TCs (Transfer Controllers)
+                * relative to IO initiated by the other bus masters on the
+                * device (ARM, DSP, USB, etc)
+                */
+               {
+               0u,
+               1u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+               /**
+                * \brief To Configure the Threshold level of number of events
+                * that can be queued up in the Event queues. EDMA3CC error register
+                * (CCERR) will indicate whether or not at any instant of time the
+                * number of events queued up in any of the event queues exceeds
+                * or equals the threshold/watermark value that is set
+                * in the queue watermark threshold register (QWMTHRA).
+                */
+               {
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief To Configure the Default Burst Size (DBS) of TCs.
+                * An optimally-sized command is defined by the transfer controller
+                * default burst size (DBS). Different TCs can have different
+                * DBS values. It is defined in Bytes.
+                */
+               {
+               128u,
+               128u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief Mapping from each DMA channel to a Parameter RAM set,
+                * if it exists, otherwise of no use.
+                */
+               {
+               EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+               },
+
+                /**
+                 * \brief Mapping from each DMA channel to a TCC. This specific
+                 * TCC code will be returned when the transfer is completed
+                 * on the mapped channel.
+                 */
+               {
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+               },
+
+               /**
+                * \brief Mapping of DMA channels to Hardware Events from
+                * various peripherals, which use EDMA for data transfer.
+                * All channels need not be mapped, some can be free also.
+                */
+               {
+               0xFFFFFFFFu,
+               0x00000000u
+               }
+               },
+       };
+
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+       {
+               /* EDMA3 INSTANCE# 0 */
+               {
+                       /* Resources owned/reserved by region 0 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x000000FFu, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000001u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x000000FFu, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 1 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x0000FF00u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000002u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x0000FF00u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 2 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00FF0000u, 0x0000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000004u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00FF0000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 3 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFF000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000008u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFF000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 4 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x000000FFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000010u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x000000FFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 5 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x0000FF00u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000020u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x0000FF00u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 6 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00FF0000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000040u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00FF0000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0xFF000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000080u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0xFF000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+               },
+
+               /* EDMA3 INSTANCE# 1 */
+               {
+                       /* Resources owned/reserved by region 0 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x000000FFu, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000001u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x000000FFu, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 1 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x0000FF00u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000002u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x0000FF00u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 2 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00FF0000u, 0x0000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000004u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00FF0000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 3 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFF000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000008u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFF000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 4 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x000000FFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000010u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x000000FFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 5 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x0000FF00u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000020u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x0000FF00u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 6 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00FF0000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000040u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00FF0000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0xFF000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000080u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0xFF000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+               },
+
+               /* EDMA3 INSTANCE# 2 */
+               {
+                       /* Resources owned/reserved by region 0 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x000000FFu, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000001u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x000000FFu, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 1 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x0000FF00u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000002u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x0000FF00u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 2 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00FF0000u, 0x0000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000004u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00FF0000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 3 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFF000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000008u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFF000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 4 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x000000FFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000010u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x000000FFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 5 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x0000FF00u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000020u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x0000FF00u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 6 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00FF0000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000040u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00FF0000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0xFF000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000080u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0xFF000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+               },
+
+               /* EDMA3 INSTANCE# 3 */
+               {
+                       /* Resources owned/reserved by region 0 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x000000FFu, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000001u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x000000FFu, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 1 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x0000FF00u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000002u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x0000FF00u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 2 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00FF0000u, 0x0000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000004u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00FF0000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 3 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFF000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000008u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFF000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 4 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x000000FFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000010u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x000000FFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 5 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x0000FF00u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000020u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x0000FF00u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 6 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00FF0000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000040u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00FF0000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0xFF000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000080u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0xFF000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+               },
+
+               /* EDMA3 INSTANCE# 4 */
+               {
+                       /* Resources owned/reserved by region 0 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x000000FFu, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000001u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x000000FFu, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 1 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x0000FF00u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000002u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x0000FF00u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 2 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00FF0000u, 0x0000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000004u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00FF0000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 3 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFF000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000008u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFF000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 4 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x000000FFu},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000010u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x000000FFu},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 5 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0xFF000000u, 0xFFFFFFFFu,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x0000FF00u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000020u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x0000FF00u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 6 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00FF0000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000040u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00FF0000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 7 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0xFFFFFF00u, 0xFFFFFFFFu},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0xFF000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000080u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0xFF000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+               },
+       };
+
+/* End of File */
diff --git a/examples/edma3_user_space_driver/evmC66AK2E/makefile b/examples/edma3_user_space_driver/evmC66AK2E/makefile
new file mode 100755 (executable)
index 0000000..23dab4d
--- /dev/null
@@ -0,0 +1,30 @@
+# Makefile for edma3 lld app
+
+APP_NAME = edma3_drv_c66ak2e_a15_sample
+
+SRCDIR = ../src ./
+INCDIR = ../src
+
+# List all the external components/interfaces, whose interface header files 
+#  need to be included for this component
+INCLUDE_EXERNAL_INTERFACES = edma3_lld
+
+# List all the components required by the application
+COMP_LIST_a15 = edma3_lld_drv edma3_lld_rm
+
+XDC_CFG_FILE_a15 = 
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON = main.c evmC66AK2ESample.c
+CFLAGS_LOCAL_COMMON = 
+
+# Libraries and Include paths
+EXT_LIB_a15host = $(edma3_lld_drv_PATH)/lib/a15/$(PROFILE_$(CORE))/edma3_lld_drv.aa15fg $(edma3_lld_rm_PATH)/lib/c66ak2e-evm/a15/$(PROFILE_$(CORE))/edma3_lld_rm.aa15fg -lrt -lpthread
+EXT_INCLUDES = -I$(edma3_lld_drv_PATH) -I$(edma3_lld_rm_PATH) -I$(edma3_lld_PATH)/packages
+
+# Include common make files
+include $(ROOTDIR)/makerules/common.mk
+
+# Nothing beyond this point
+
+
diff --git a/examples/edma3_user_space_driver/evmTCI6630K2L/evmTCI6630K2LSample.c b/examples/edma3_user_space_driver/evmTCI6630K2L/evmTCI6630K2LSample.c
new file mode 100644 (file)
index 0000000..11fa6cd
--- /dev/null
@@ -0,0 +1,1845 @@
+/*
+ * sample_tci6630k2l_cfg.c
+ *
+ * Platform specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2012-2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES                    3u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                                       4u
+//const unsigned int numDsps = NUM_DSPS;
+
+#define CGEM_REG_START                  (0x01800000)
+
+
+//extern cregister volatile unsigned int DNUM;
+#define DNUM 0
+
+#define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
+
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+       {
+       volatile unsigned int *addr;
+       unsigned int core_no;
+
+    /* Identify the core number */
+    addr = (unsigned int *)(CGEM_REG_START+0x40000);
+    core_no = ((*addr) & 0x000F0000)>>16;
+
+       return core_no;
+       }
+
+signed char*  getGlobalAddr(signed char* addr)
+{
+    if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
+    {
+        return (addr); /* The address is already a global address */
+    }
+
+    return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
+}
+/** Whether global configuration required for EDMA3 or not.
+ * This configuration should be done only once for the EDMA3 hardware by
+ * any one of the masters (i.e. DSPs).
+ * It can be changed depending on the use-case.
+ */
+unsigned int gblCfgReqdArray [NUM_DSPS] = {
+                                                                       0,      /* DSP#0 is Master, will do the global init */
+                                                                       1,      /* DSP#1 is Slave, will not do the global init  */
+                                                                       1,      /* DSP#2 is Slave, will not do the global init  */
+                                                                       1,      /* DSP#3 is Slave, will not do the global init  */
+                                                                       };
+
+unsigned short isGblConfigRequired(unsigned int dspNum)
+       {
+       return gblCfgReqdArray[dspNum];
+       }
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL,NULL};
+
+
+/* Variable which will be used internally for referring number of Event Queues. */
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/* Variable which will be used internally for referring number of TCs. */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 4u, 4u};
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt. Completion interrupts for all the shadow regions and all the
+ * EDMA3 controllers are captured since it is a multi-DSP platform.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+                                                                                                       {
+                                                                                                       38u, 39u, 40u, 41u,
+                                                                                                       42u, 43u, 44u, 45u,
+                                                                                                       },
+                                                                                                       {
+                                                                                                       8u, 9u, 10u, 11u,
+                                                                                                       12u, 13u, 14u, 15u,
+                                                                                                       },
+                                                                                                       {
+                                                                                                       24u, 25u, 26u, 27u,
+                                                                                                       28u, 29u, 30u, 31u,
+                                                                                                       },
+                                                                                               };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {32u, 0u, 16u};
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] =    {
+                                                                                                       {
+                                                                                                       34u, 35u, 0u, 0u,
+                                                                                                       0u, 0u, 0u, 0u,
+                                                                                                       },
+                                                                                                       {
+                                                                                                       2u, 3u, 4u, 5u,
+                                                                                                       0u, 0u, 0u, 0u,
+                                                                                                       },
+                                                                                                       {
+                                                                                                       18u, 19u, 20u, 21u,
+                                                                                                       0u, 0u, 0u, 0u,
+                                                                                                       },
+                                                                                               };
+
+/* Driver Object Initialization Configuration */
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+       {
+               {
+               /* EDMA3 INSTANCE# 0 */
+               /** Total number of DMA Channels supported by the EDMA3 Controller */
+               64u,
+               /** Total number of QDMA Channels supported by the EDMA3 Controller */
+               8u,
+               /** Total number of TCCs supported by the EDMA3 Controller */
+               64u,
+               /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+               512u,
+               /** Total number of Event Queues in the EDMA3 Controller */
+               2u,
+               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+               2u,
+               /** Number of Regions on this EDMA3 controller */
+               8u,
+
+               /**
+                * \brief Channel mapping existence
+                * A value of 0 (No channel mapping) implies that there is fixed association
+                * for a channel number to a parameter entry number or, in other words,
+                * PaRAM entry n corresponds to channel n.
+                */
+               1u,
+
+               /** Existence of memory protection feature */
+               1u,
+
+               /** Global Register Region of CC Registers */
+               (void *)0x02700000u,
+               /** Transfer Controller (TC) Registers */
+               {
+               (void *)0x02760000u,
+               (void *)0x02768000u,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL
+               },
+               /** Interrupt no. for Transfer Completion */
+               38u,
+               /** Interrupt no. for CC Error */
+               32u,
+               /** Interrupt no. for TCs Error */
+               {
+               34u,
+               35u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               },
+
+               /**
+                * \brief EDMA3 TC priority setting
+                *
+                * User can program the priority of the Event Queues
+                * at a system-wide level.  This means that the user can set the
+                * priority of an IO initiated by either of the TCs (Transfer Controllers)
+                * relative to IO initiated by the other bus masters on the
+                * device (ARM, DSP, USB, etc)
+                */
+               {
+               0u,
+               1u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+               /**
+                * \brief To Configure the Threshold level of number of events
+                * that can be queued up in the Event queues. EDMA3CC error register
+                * (CCERR) will indicate whether or not at any instant of time the
+                * number of events queued up in any of the event queues exceeds
+                * or equals the threshold/watermark value that is set
+                * in the queue watermark threshold register (QWMTHRA).
+                */
+               {
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief To Configure the Default Burst Size (DBS) of TCs.
+                * An optimally-sized command is defined by the transfer controller
+                * default burst size (DBS). Different TCs can have different
+                * DBS values. It is defined in Bytes.
+                */
+               {
+               128u,
+               128u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief Mapping from each DMA channel to a Parameter RAM set,
+                * if it exists, otherwise of no use.
+                */
+               {
+                   EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+               },
+
+                /**
+                 * \brief Mapping from each DMA channel to a TCC. This specific
+                 * TCC code will be returned when the transfer is completed
+                 * on the mapped channel.
+                 */
+               {
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+               },
+
+               /**
+                * \brief Mapping of DMA channels to Hardware Events from
+                * various peripherals, which use EDMA for data transfer.
+                * All channels need not be mapped, some can be free also.
+                */
+               {
+               0xFFFFFFFFu,
+               0x00000000u
+               }
+               },
+
+               {
+               /* EDMA3 INSTANCE# 1 */
+               /** Total number of DMA Channels supported by the EDMA3 Controller */
+               64u,
+               /** Total number of QDMA Channels supported by the EDMA3 Controller */
+               8u,
+               /** Total number of TCCs supported by the EDMA3 Controller */
+               64u,
+               /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+               512u,
+               /** Total number of Event Queues in the EDMA3 Controller */
+               4u,
+               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+               4u,
+               /** Number of Regions on this EDMA3 controller */
+               8u,
+
+               /**
+                * \brief Channel mapping existence
+                * A value of 0 (No channel mapping) implies that there is fixed association
+                * for a channel number to a parameter entry number or, in other words,
+                * PaRAM entry n corresponds to channel n.
+                */
+               1u,
+
+               /** Existence of memory protection feature */
+               1u,
+
+               /** Global Register Region of CC Registers */
+               (void *)0x02720000u,
+               /** Transfer Controller (TC) Registers */
+               {
+               (void *)0x02770000u,
+               (void *)0x02778000u,
+               (void *)0x02780000u,
+               (void *)0x02788000u,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL
+               },
+               /** Interrupt no. for Transfer Completion */
+               8u,
+               /** Interrupt no. for CC Error */
+               0u,
+               /** Interrupt no. for TCs Error */
+               {
+               2u,
+               3u,
+               4u,
+               5u,
+               0u,
+               0u,
+               0u,
+               0u,
+               },
+
+               /**
+                * \brief EDMA3 TC priority setting
+                *
+                * User can program the priority of the Event Queues
+                * at a system-wide level.  This means that the user can set the
+                * priority of an IO initiated by either of the TCs (Transfer Controllers)
+                * relative to IO initiated by the other bus masters on the
+                * device (ARM, DSP, USB, etc)
+                */
+               {
+               0u,
+               1u,
+               2u,
+               3u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+               /**
+                * \brief To Configure the Threshold level of number of events
+                * that can be queued up in the Event queues. EDMA3CC error register
+                * (CCERR) will indicate whether or not at any instant of time the
+                * number of events queued up in any of the event queues exceeds
+                * or equals the threshold/watermark value that is set
+                * in the queue watermark threshold register (QWMTHRA).
+                */
+               {
+               16u,
+               16u,
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief To Configure the Default Burst Size (DBS) of TCs.
+                * An optimally-sized command is defined by the transfer controller
+                * default burst size (DBS). Different TCs can have different
+                * DBS values. It is defined in Bytes.
+                */
+               {
+               128u,
+               128u,
+               128u,
+               128u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief Mapping from each DMA channel to a Parameter RAM set,
+                * if it exists, otherwise of no use.
+                */
+               {
+                   EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+               },
+
+                /**
+                 * \brief Mapping from each DMA channel to a TCC. This specific
+                 * TCC code will be returned when the transfer is completed
+                 * on the mapped channel.
+                 */
+               {
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+               },
+
+               /**
+                * \brief Mapping of DMA channels to Hardware Events from
+                * various peripherals, which use EDMA for data transfer.
+                * All channels need not be mapped, some can be free also.
+                */
+               {
+               0xFFFFFFFFu,
+               0x00000000u
+               }
+               },
+
+               {
+               /* EDMA3 INSTANCE# 2 */
+               /** Total number of DMA Channels supported by the EDMA3 Controller */
+               64u,
+               /** Total number of QDMA Channels supported by the EDMA3 Controller */
+               8u,
+               /** Total number of TCCs supported by the EDMA3 Controller */
+               64u,
+               /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+               512u,
+               /** Total number of Event Queues in the EDMA3 Controller */
+               4u,
+               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+               4u,
+               /** Number of Regions on this EDMA3 controller */
+               8u,
+
+               /**
+                * \brief Channel mapping existence
+                * A value of 0 (No channel mapping) implies that there is fixed association
+                * for a channel number to a parameter entry number or, in other words,
+                * PaRAM entry n corresponds to channel n.
+                */
+               1u,
+
+               /** Existence of memory protection feature */
+               1u,
+
+               /** Global Register Region of CC Registers */
+               (void *)0x02740000u,
+               /** Transfer Controller (TC) Registers */
+               {
+               (void *)0x02790000u,
+               (void *)0x02798000u,
+               (void *)0x027A0000u,
+               (void *)0x027A8000u,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL,
+               (void *)NULL
+               },
+               /** Interrupt no. for Transfer Completion */
+               24u,
+               /** Interrupt no. for CC Error */
+               16u,
+               /** Interrupt no. for TCs Error */
+               {
+               18u,
+               19u,
+               20u,
+               21u,
+               0u,
+               0u,
+               0u,
+               0u,
+               },
+
+               /**
+                * \brief EDMA3 TC priority setting
+                *
+                * User can program the priority of the Event Queues
+                * at a system-wide level.  This means that the user can set the
+                * priority of an IO initiated by either of the TCs (Transfer Controllers)
+                * relative to IO initiated by the other bus masters on the
+                * device (ARM, DSP, USB, etc)
+                */
+               {
+               0u,
+               1u,
+               2u,
+               3u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+               /**
+                * \brief To Configure the Threshold level of number of events
+                * that can be queued up in the Event queues. EDMA3CC error register
+                * (CCERR) will indicate whether or not at any instant of time the
+                * number of events queued up in any of the event queues exceeds
+                * or equals the threshold/watermark value that is set
+                * in the queue watermark threshold register (QWMTHRA).
+                */
+               {
+               16u,
+               16u,
+               16u,
+               16u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief To Configure the Default Burst Size (DBS) of TCs.
+                * An optimally-sized command is defined by the transfer controller
+                * default burst size (DBS). Different TCs can have different
+                * DBS values. It is defined in Bytes.
+                */
+               {
+               128u,
+               128u,
+               128u,
+               128u,
+               0u,
+               0u,
+               0u,
+               0u
+               },
+
+               /**
+                * \brief Mapping from each DMA channel to a Parameter RAM set,
+                * if it exists, otherwise of no use.
+                */
+               {
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+               },
+
+                /**
+                 * \brief Mapping from each DMA channel to a TCC. This specific
+                 * TCC code will be returned when the transfer is completed
+                 * on the mapped channel.
+                 */
+               {
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+               },
+
+               /**
+                * \brief Mapping of DMA channels to Hardware Events from
+                * various peripherals, which use EDMA for data transfer.
+                * All channels need not be mapped, some can be free also.
+                */
+               {
+               0xFFFFFFFFu,
+               0x00000000u
+               }
+               },
+
+       };
+
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+       {
+               /* EDMA3 INSTANCE# 0 */
+               {
+                       /* Resources owned/reserved by region 0 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00FFFFFFu,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x000000FFu, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000001u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x000000FFu, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 1 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0xFF000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x0000FF00u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000002u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x0000FF00u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 2 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0x000000FFu,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00FF0000u, 0x0000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000004u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0x00FF0000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+               /* Resources owned/reserved by region 3 */
+                       {
+                               /* ownPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFF00u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+                               /* ownDmaChannels */
+                               /* 31     0     63    32 */
+                               {0xFF000000u, 0x00000000u},
+
+                               /* ownQdmaChannels */
+                               /* 31     0 */
+                               {0x00000008u},
+
+                               /* ownTccs */
+                               /* 31     0     63    32 */
+                               {0xFF000000u, 0x00000000u},
+
+                               /* resvdPaRAMSets */
+                               /* 31     0     63    32     95    64     127   96 */
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
+                               /* 159  128     191  160     223  192     255  224 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 287  256     319  288     351  320     383  352 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               /* 415  384     447  416     479  448     511  480 */
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+                               /* resvdDmaChannels */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+
+                               /* resvdQdmaChannels */
+                               /* 31     0 */
+                               {0x00000000u},
+
+                               /* resvdTccs */
+                               /* 31     0     63    32 */
+                               {0x00000000u, 0x00000000u},
+                       },
+
+