Added vayu support for M4 DEV_EDMA3_LLD_02_11_07_01_RC01
authorPrasad Konnur <prasad.konnur@ti.com>
Thu, 28 Mar 2013 07:50:03 +0000 (07:50 +0000)
committerPrasad Konnur <prasad.konnur@ti.com>
Thu, 28 Mar 2013 07:50:03 +0000 (07:50 +0000)
M4 Vayu Examples tested on virtio

Signed-off-by: Prasad Konnur <prasad.konnur@ti.com>
21 files changed:
examples/edma3_driver/evmtda2xx_A15/makefile [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_A15/rtsc_config/edma3_drv_bios6_tda2xx_a15_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_A15/sample_app/linker.cmd [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_M4/VayuIPC.gel [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_M4/makefile [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_st_sample.cfg [new file with mode: 0644]
examples/edma3_driver/evmtda2xx_M4/sample_app/linker.cmd [new file with mode: 0644]
examples/edma3_driver/src/sample.h
makerules/platform.mk
makerules/rules_a15.mk [new file with mode: 0644]
makerules/rules_m4.mk [new file with mode: 0644]
packages/component.mk
packages/makefile
packages/ti/sdo/edma3/drv/sample/makefile
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c [new file with mode: 0644]
packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/makefile
packages/ti/sdo/edma3/rm/sample/makefile
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda2xx_arm_int_reg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda2xx_cfg.c [new file with mode: 0644]
packages/ti/sdo/edma3/rm/src/configs/edma3_tda2xx_cfg.c [new file with mode: 0644]

diff --git a/examples/edma3_driver/evmtda2xx_A15/makefile b/examples/edma3_driver/evmtda2xx_A15/makefile
new file mode 100644 (file)
index 0000000..490f693
--- /dev/null
@@ -0,0 +1,35 @@
+# Makefile for edma3 lld app\r
+\r
+APP_NAME = edma3_drv_arm_tda2xx_sample\r
+\r
+SRCDIR = ../src\r
+INCDIR = ../src\r
+\r
+# List all the external components/interfaces, whose interface header files \r
+#  need to be included for this component\r
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld\r
+\r
+# List all the components required by the application\r
+COMP_LIST_a15host = edma3_lld_drv edma3_lld_rm\r
+\r
+# XDC CFG File\r
+XDC_CFG_FILE_a15host = rtsc_config/edma3_drv_bios6_tda2xx_a15_st_sample.cfg\r
+\r
+# Common source files and CFLAGS across all platforms and cores\r
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \\r
+              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \\r
+              qdma_link_test.c\r
+CFLAGS_LOCAL_COMMON = -DBUILD_TDA2XX_MPU\r
+\r
+# Core/SoC/platform specific source files and CFLAGS\r
+# Example: \r
+#   SRCS_<core/SoC/platform-name> = \r
+#   CFLAGS_LOCAL_<core/SoC/platform-name> =\r
+\r
+# Include common make files\r
+include $(ROOTDIR)/makerules/common.mk\r
+\r
+# OBJs and libraries are built by using rule defined in rules_<target>.mk \r
+#     and need not be explicitly specified here\r
+\r
+# Nothing beyond this point\r
diff --git a/examples/edma3_driver/evmtda2xx_A15/rtsc_config/edma3_drv_bios6_tda2xx_a15_st_sample.cfg b/examples/edma3_driver/evmtda2xx_A15/rtsc_config/edma3_drv_bios6_tda2xx_a15_st_sample.cfg
new file mode 100644 (file)
index 0000000..c24c9d9
--- /dev/null
@@ -0,0 +1,52 @@
+/*use modules*/\r
+var Task = xdc.useModule ("ti.sysbios.knl.Task");\r
+var BIOS      = xdc.useModule ("ti.sysbios.BIOS");\r
+var Startup   = xdc.useModule ("xdc.runtime.Startup");\r
+var System    = xdc.useModule ("xdc.runtime.System");\r
+var Log       = xdc.useModule ("xdc.runtime.Log");\r
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');\r
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');\r
+var Program     = xdc.useModule("xdc.cfg.Program");\r
+//var Cache = xdc.useModule('ti.sysbios.hal.Cache');\r
+var Error = xdc.useModule('xdc.runtime.Error');\r
+\r
+/* Heap used when creating semaphore's, TSK's or malloc() ... */\r
+Program.heap            = 0x1000;\r
+\r
+/* ISR/SWI stack        */\r
+Program.stack           = 0x4000;\r
+\r
+Program.sectMap[".cio"] = new Program.SectionSpec();\r
+Program.sectMap[".cio"].loadSegment = "EXT_RAM";\r
+\r
+/* USE EDMA3 Sample App */\r
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');\r
+\r
+/* MMU/Cache related configurations                                           */\r
+\r
+var Cache  = xdc.useModule('ti.sysbios.family.arm.a15.Cache');\r
+var Mmu    = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');\r
+var InitXbar = xdc.useModule('ti.sysbios.hal.vayu.IntXbar');\r
+\r
+\r
+/* Enable the cache                                                           */\r
+Cache.enableCache = false;\r
+\r
+/* Enable the MMU (Required for L1 data caching)                              */\r
+Mmu.enableMMU = true;\r
+\r
+var attrs = new Mmu.DescriptorAttrs();\r
+Mmu.initDescAttrsMeta(attrs);\r
+attrs.type = Mmu.DescriptorType_BLOCK;\r
+attrs.noExecute = true;\r
+attrs.accPerm = 0;       // R/W at PL1\r
+attrs.attrIndx = 2;       // Use MAIR0 Byte2\r
+Mmu.setMAIRMeta(2, 0x04);\r
+Mmu.setSecondLevelDescMeta(0x43200000, 0x43200000, attrs);\r
+//Mmu.setSecondLevelDescMeta(0x43400000, 0x43400000, attrs);\r
+\r
+Task.initStackFlag = false;\r
+Task.checkStackFlag = false;\r
+\r
+Hwi.initStackFlag = false;\r
+Hwi.checkStackFlag = false;
\ No newline at end of file
diff --git a/examples/edma3_driver/evmtda2xx_A15/sample_app/linker.cmd b/examples/edma3_driver/evmtda2xx_A15/sample_app/linker.cmd
new file mode 100644 (file)
index 0000000..20e2983
--- /dev/null
@@ -0,0 +1,5 @@
+SECTIONS\r
+{\r
+    .my_sect_iram > EXT_RAM\r
+    .my_sect_ddr  > EXT_RAM\r
+}\r
diff --git a/examples/edma3_driver/evmtda2xx_M4/VayuIPC.gel b/examples/edma3_driver/evmtda2xx_M4/VayuIPC.gel
new file mode 100644 (file)
index 0000000..bacc15e
--- /dev/null
@@ -0,0 +1,192 @@
+#define BIT_ONE(bit) (1<<bit)
+#define BIT_ZERO     (0)
+
+// translate    - enable AMMU page translation
+#define AMMU_PAGE_TRANSLATE_YES                     BIT_ZERO
+#define AMMU_PAGE_TRANSLATE_NO                      BIT_ONE(0)
+
+// enable       - enable page (0=page not enabled, 1=page enabled) R/W 0x0
+#define AMMU_PAGE_ENABLE_YES                        BIT_ONE(0)
+#define AMMU_PAGE_ENABLE_NO                         BIT_ZERO
+
+// size         - size of page (RTL configurable) R/W 0x0
+//--- LARGE ---
+#define AMMU_LARGE_PAGE_32M                         BIT_ZERO
+#define AMMU_LARGE_PAGE_512M                        BIT_ONE(1)
+
+//--- MEDIUM ---
+#define AMMU_MEDIUM_PAGE_128K                       BIT_ZERO
+#define AMMU_MEDIUM_PAGE_256K                       BIT_ONE(1)
+
+//--- SMALL ---
+#define AMMU_SMALL_PAGE_4K                          BIT_ZERO
+#define AMMU_SMALL_PAGE_16K                         BIT_ONE(1)
+
+// endianism    - endianism (0=big endian, 1=little endian) R/W 0x0
+#define AMMU_ENDIANISM_BIG                          BIT_ZERO
+#define AMMU_ENDIANISM_LITTLE                       BIT_ONE(2)
+
+// volatile     - volatile qualifier, see policy matrix (0=do not follow volatile qualifer, 1=follow volatile qualifier) R/W 0x0
+#define AMMU_VOLATILE_YES                           BIT_ONE(3)
+#define AMMU_VOLATILE_NO                            BIT_ZERO
+
+// execute      - execute only (see read/execute table) R/W 0x0
+#define AMMU_EXECUTE_ONLY_YES                       BIT_ONE(4)
+#define AMMU_EXECUTE_ONLY_NO                        BIT_ZERO
+
+// read         - read only (see read/execute table) R/W 0x0
+#define AMMU_READ_ONLY_YES                          BIT_ONE(5)
+#define AMMU_READ_ONLY_NO                           BIT_ZERO
+
+// preload      - preload region (0=do not preload, 1=preload) R/W 0x0
+#define AMMU_PREFETCH_ENABLE                        BIT_ONE(6)
+#define AMMU_PREFETCH_ENABLE_NO                     BIT_ZERO
+
+// exclusion    - cache exclusion (0=do not send exclusion sideband, 1=send exclusion sideband) R/W 0x0
+#define AMMU_EXCLUSION_SEND                         BIT_ONE(7)
+#define AMMU_EXCLUSION_NOT_SEND                     BIT_ZERO
+
+// coherency    - cache coherent region (0=not coherent, 1=coherent) R/W 0x0
+#define AMMU_COHERENCY_YES                          BIT_ONE(8)
+#define AMMU_COHERENCY_NO                           BIT_ZERO
+
+// L1 cacheable - L1 cache policy (0=non-cacheable, 1=cacheable) R/W 0x0
+#define AMMU_L1_CACHE_POLICY_CACHEABLE              BIT_ONE(16)
+#define AMMU_L1_CACHE_POLICY_NON_CACHEABLE          BIT_ZERO
+
+// L1 posted    - L1 posted policy (0=non-posted 1=posted) R/W 0x0
+#define AMMU_L1_POSTED_POLICY_POSTED                BIT_ONE(17)
+#define AMMU_L1_POSTED_POLICY_NON_POSTED            BIT_ZERO
+
+// L1 allocate  - L1 allocate policy (0=non-allocate 1=allocate) R/W 0x0
+#define AMMU_L1_ALLOCATE_POLICY_ALLOCATE            BIT_ONE(18)
+#define AMMU_L1_ALLOCATE_POLICY_NON_ALLOCATE        BIT_ZERO
+
+// L1 write     - L1 write policy (0=write through, 1=write back) R/W 0x0
+#define AMMU_L1_WRITE_POLICY_WRITE_BACK             BIT_ONE(19)
+#define AMMU_L1_WRITE_POLICY_WRITE_THROUGH          BIT_ZERO
+
+// L2 cacheable - L2 cache policy (0=non-cacheable, 1=cacheable) R/W 0x0
+#define AMMU_L2_CACHE_POLICY_CACHEABLE              BIT_ONE(20)
+#define AMMU_L2_CACHE_POLICY_NON_CACHEABLE          BIT_ZERO
+
+// L2 posted    - L2 posted policy (0=non-posted 1=posted) R/W 0x0
+#define AMMU_L2_POSTED_POLICY_POSTED                BIT_ONE(21)
+#define AMMU_L2_POSTED_POLICY_NON_POSTED            BIT_ZERO
+
+// L2 allocate  - L2 allocate policy (0=non-allocate 1=allocate) R/W 0x0
+#define AMMU_L2_ALLOCATE_POLICY_ALLOCATE            BIT_ONE(22)
+#define AMMU_L2_ALLOCATE_POLICY_NON_ALLOCATE        BIT_ZERO
+
+// L2 write     - L2 write policy (0=write through, 1=write back)
+#define AMMU_L2_WRITE_POLICY_WRITE_BACK             BIT_ONE(23)
+#define AMMU_L2_WRITE_POLICY_WRITE_THROUGH          BIT_ZERO
+
+//preload    - preload page (0=do nothing, preload done, 1=preload) R/W 0x0
+#define AMMU_SMALL_MAINT_PRELOAD_YES                BIT_ONE(0)
+#define AMMU_SMALL_MAINT_PRELOAD_NO                 BIT_ZERO
+
+//lock       - lock page (0=do nothing, lock done, 1=lock) R/W 0x0
+#define AMMU_SMALL_MAINT_LOCK_YES                   BIT_ONE(1)
+#define AMMU_SMALL_MAINT_LOCK_NO                    BIT_ZERO
+
+//clean      - evict page (0=do nothing, clean done, 1=clean) R/W 0x0
+#define AMMU_SMALL_MAINT_CLEAN_YES                   BIT_ONE(2)
+#define AMMU_SMALL_MAINT_CLEAN_NO                    BIT_ZERO
+
+//invalidate - invalidate page (0=do nothing, invalidate done, 1=invalidate) R/W 0x0
+#define AMMU_SMALL_MAINT_INVALIDATE_YES                   BIT_ONE(3)
+#define AMMU_SMALL_MAINT_INVALIDATE_NO                    BIT_ZERO
+
+//interrupt  - generate interrupt when maintenance operation is complete (0=do not generate interrupt, 1=generate interrupt) R/W 0x0
+#define AMMU_SMALL_MAINT_INTERRUPT_YES                   BIT_ONE(4)
+#define AMMU_SMALL_MAINT_INTERRUPT_NO                    BIT_ZERO
+
+//#define AMMU_BASE_ADDRESS 0x55080800
+
+/*Base address to configure AMMU from MPU*/
+//#define AMMU_BASE_ADDRESS 0x58880800
+
+/*Base address to configure AMMU from IPU*/
+#define AMMU_BASE_ADDRESS 0x40000800
+
+// OMAP4
+#define AMMU_LARGE_IDX_ADDR(page_no)   (*((unsigned long*)(AMMU_BASE_ADDRESS + 4*page_no + 0)))
+#define AMMU_LARGE_IDX_XLTE(page_no)   (*((unsigned long*)(AMMU_BASE_ADDRESS + 4*page_no + 0x20)))
+#define AMMU_LARGE_IDX_PLOY(page_no)   (*((unsigned long*)(AMMU_BASE_ADDRESS + 4*page_no + 0x40)))
+
+#define AMMU_MEDIUM_IDX_ADDR(page_no)  (*((unsigned long*)(AMMU_BASE_ADDRESS + 4*page_no + 0x60)))
+#define AMMU_MEDIUM_IDX_XLTE(page_no)  (*((unsigned long*)(AMMU_BASE_ADDRESS + 4*page_no + 0xA0)))
+#define AMMU_MEDIUM_IDX_PLOY(page_no)  (*((unsigned long*)(AMMU_BASE_ADDRESS + 4*page_no + 0xE0)))
+
+#define AMMU_SMALL_IDX_ADDR(page_no)   (*((unsigned long*)(AMMU_BASE_ADDRESS + 4*page_no + 0x120)))
+#define AMMU_SMALL_IDX_XLTE(page_no)   (*((unsigned long*)(AMMU_BASE_ADDRESS + 4*page_no + 0x1A0)))
+#define AMMU_SMALL_IDX_PLOY(page_no)   (*((unsigned long*)(AMMU_BASE_ADDRESS + 4*page_no + 0x220)))
+#define AMMU_SMALL_IDX_MAINT(page_no)  (*((unsigned long*)(AMMU_BASE_ADDRESS + 4*page_no + 0x2A0)))
+
+menuitem "Benelli";
+hotmenu
+program_benelli_AMMU()
+{
+    GEL_TextOut("program_benelli_AMMU() called.\n");
+       
+       // Do not use SMALL page index 0 and 1.
+       AMMU_SMALL_IDX_ADDR(2) = 0x00000000;
+    AMMU_SMALL_IDX_XLTE(2) =  (0x55020000 | AMMU_PAGE_TRANSLATE_YES);
+    AMMU_SMALL_IDX_PLOY(2) = (AMMU_PAGE_ENABLE_YES + AMMU_SMALL_PAGE_4K + AMMU_ENDIANISM_LITTLE);
+
+    AMMU_SMALL_IDX_ADDR(3) = 0x00400000;
+    AMMU_SMALL_IDX_XLTE(3) =  (0x40400000 | AMMU_PAGE_TRANSLATE_YES);
+    AMMU_SMALL_IDX_PLOY(3) = (AMMU_PAGE_ENABLE_YES + AMMU_SMALL_PAGE_4K + AMMU_ENDIANISM_LITTLE);
+       
+       /*OCMC*/
+    AMMU_SMALL_IDX_ADDR(4) = 0x00300000;
+    AMMU_SMALL_IDX_XLTE(4) =  (0x40300000 | AMMU_PAGE_TRANSLATE_YES);
+    AMMU_SMALL_IDX_PLOY(4) = (AMMU_PAGE_ENABLE_YES + AMMU_SMALL_PAGE_4K + AMMU_ENDIANISM_LITTLE);
+
+    AMMU_MEDIUM_IDX_ADDR(0) = 0xA0000000;
+    AMMU_MEDIUM_IDX_XLTE(0) =  (0x43300000 | AMMU_PAGE_TRANSLATE_YES);
+    AMMU_MEDIUM_IDX_PLOY(0) = (AMMU_PAGE_ENABLE_YES + AMMU_MEDIUM_PAGE_128K + AMMU_ENDIANISM_LITTLE);
+       
+       AMMU_LARGE_IDX_ADDR(1) = 0x80000000;
+    AMMU_LARGE_IDX_XLTE(1) =  (0x80000000 | AMMU_PAGE_TRANSLATE_YES);
+    AMMU_LARGE_IDX_PLOY(1) = (AMMU_PAGE_ENABLE_YES + AMMU_LARGE_PAGE_32M + AMMU_ENDIANISM_LITTLE);    
+}
+
+menuitem "IPU";
+hotmenu
+program_IPU_AMMU()
+{
+    GEL_TextOut("programming  IPU1 AMMU to remap 0x0 to 0x55020000...\n");
+    *(unsigned int *)0x40000920=0x0;
+    *(unsigned int *)0x400009A0=0x55020000;
+    *(unsigned int *)0x40000A20=0x3;
+       
+    GEL_TextOut("programming  IPU2 AMMU to remap 0x0 to 0x55020000...\n");
+    *(unsigned int*)0x40000920 = 0x0;
+    *(unsigned int*)0x400009A0 = 0x55020000;
+    *(unsigned int*)0x40000A20 = 0x3;
+
+    AMMU_MEDIUM_IDX_ADDR(0) = 0xA0000000;
+    AMMU_MEDIUM_IDX_XLTE(0) =  (0x43300000 | AMMU_PAGE_TRANSLATE_YES);
+    AMMU_MEDIUM_IDX_PLOY(0) = (AMMU_PAGE_ENABLE_YES + AMMU_MEDIUM_PAGE_128K + AMMU_ENDIANISM_LITTLE);
+}
+
+menuitem "IPU";
+hotmenu
+program_IPU_AMMU_2()
+{
+    GEL_TextOut("programming  IPU1 AMMU to remap 0x0 to 0x55020000...\n");
+    *(unsigned int *)0x58880920=0x0;
+    *(unsigned int *)0x588809A0=0x55020000;
+    *(unsigned int *)0x58880A20=0x3;
+       
+    GEL_TextOut("programming  IPU2 AMMU to remap 0x0 to 0x55020000...\n");
+    *(unsigned int*)0x55080920 = 0x0;
+    *(unsigned int*)0x550809A0 = 0x55020000;
+    *(unsigned int*)0x55080A20 = 0x3;
+       
+       AMMU_MEDIUM_IDX_ADDR(0) = 0xA0000000;
+    AMMU_MEDIUM_IDX_XLTE(0) =  (0x43300000 | AMMU_PAGE_TRANSLATE_YES);
+    AMMU_MEDIUM_IDX_PLOY(0) = (AMMU_PAGE_ENABLE_YES + AMMU_MEDIUM_PAGE_128K + AMMU_ENDIANISM_LITTLE);
+}
diff --git a/examples/edma3_driver/evmtda2xx_M4/makefile b/examples/edma3_driver/evmtda2xx_M4/makefile
new file mode 100644 (file)
index 0000000..9fda959
--- /dev/null
@@ -0,0 +1,35 @@
+# Makefile for edma3 lld app\r
+\r
+APP_NAME = edma3_drv_arm_tda2xx_sample\r
+\r
+SRCDIR = ../src\r
+INCDIR = ../src\r
+\r
+# List all the external components/interfaces, whose interface header files \r
+#  need to be included for this component\r
+INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld\r
+\r
+# List all the components required by the application\r
+COMP_LIST_m4 = edma3_lld_drv edma3_lld_rm\r
+\r
+# XDC CFG File\r
+XDC_CFG_FILE_m4 = rtsc_config/edma3_drv_bios6_tda2xx_m4_st_sample.cfg\r
+\r
+# Common source files and CFLAGS across all platforms and cores\r
+SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \\r
+              dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c      \\r
+              qdma_link_test.c\r
+CFLAGS_LOCAL_COMMON = \r
+\r
+# Core/SoC/platform specific source files and CFLAGS\r
+# Example: \r
+#   SRCS_<core/SoC/platform-name> = \r
+#   CFLAGS_LOCAL_<core/SoC/platform-name> =\r
+\r
+# Include common make files\r
+include $(ROOTDIR)/makerules/common.mk\r
+\r
+# OBJs and libraries are built by using rule defined in rules_<target>.mk \r
+#     and need not be explicitly specified here\r
+\r
+# Nothing beyond this point\r
diff --git a/examples/edma3_driver/evmtda2xx_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_st_sample.cfg b/examples/edma3_driver/evmtda2xx_M4/rtsc_config/edma3_drv_bios6_tda2xx_m4_st_sample.cfg
new file mode 100644 (file)
index 0000000..3a7679e
--- /dev/null
@@ -0,0 +1,61 @@
+/*use modules*/\r
+var Task = xdc.useModule ("ti.sysbios.knl.Task");\r
+var BIOS      = xdc.useModule ("ti.sysbios.BIOS");\r
+var Startup   = xdc.useModule ("xdc.runtime.Startup");\r
+var System    = xdc.useModule ("xdc.runtime.System");\r
+var Log       = xdc.useModule ("xdc.runtime.Log");\r
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');\r
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');\r
+var Cache0 = xdc.useModule('ti.sysbios.hal.Cache');\r
+var Error = xdc.useModule('xdc.runtime.Error');\r
+var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');\r
+var Program     = xdc.useModule("xdc.cfg.Program");\r
+var InitXbar    = xdc.useModule("ti.sysbios.hal.vayu.IntXbar");\r
+\r
+\r
+/* ISR/SWI stack        */\r
+Program.stack           = 0x4000;\r
+\r
+/* Heap used when creating semaphore's, TSK's or malloc() ... */\r
+Program.heap            = 0x15000;\r
+\r
+/* enable print of exception handing info */\r
+HwiM3.enableException = true;\r
+\r
+/* DSP/BIOS expects this to set to 1 */\r
+var Core        = xdc.useModule('ti.sysbios.family.arm.ducati.Core');\r
+Core.id = 0;\r
+\r
+/* USE EDMA3 Sample App */\r
+//xdc.loadPackage('ti.sdo.edma3.drv.sample');\r
+\r
+/* MMU/Cache related configurations                                           */\r
+var Cache1  = xdc.useModule('ti.sysbios.hal.unicache.Cache');\r
+var AMMU    = xdc.useModule('ti.sysbios.hal.ammu.AMMU');\r
+\r
+/* Enable the cache                                                           */\r
+Cache1.enableCache = true;\r
+/*\r
+AMMU.smallPages[2].pageEnabled = AMMU.Enable_YES;\r
+AMMU.smallPages[2].logicalAddress = 0x43300000;\r
+AMMU.smallPages[2].translatedAddress = 0xA0000000;\r
+AMMU.smallPages[2].translationEnabled = AMMU.Enable_YES;\r
+AMMU.smallPages[2].size = AMMU.Small_16K;\r
+AMMU.smallPages[2].volatileQualifier = AMMU.Volatile_FOLLOW; \r
+*/\r
+AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES;\r
+AMMU.mediumPages[1].logicalAddress = 0x43300000;\r
+AMMU.mediumPages[1].translatedAddress = 0xA0000000;\r
+AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES;\r
+AMMU.mediumPages[1].size = AMMU.Medium_256K;\r
+AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;\r
+AMMU.mediumPages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED;\r
+AMMU.mediumPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;\r
+AMMU.mediumPages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;\r
+  \r
+\r
+Task.initStackFlag = false;\r
+Task.checkStackFlag = false;\r
+\r
+Hwi.initStackFlag = false;\r
+Hwi.checkStackFlag = false;\r
diff --git a/examples/edma3_driver/evmtda2xx_M4/sample_app/linker.cmd b/examples/edma3_driver/evmtda2xx_M4/sample_app/linker.cmd
new file mode 100644 (file)
index 0000000..20e2983
--- /dev/null
@@ -0,0 +1,5 @@
+SECTIONS\r
+{\r
+    .my_sect_iram > EXT_RAM\r
+    .my_sect_ddr  > EXT_RAM\r
+}\r
index 8716a0c8378d338375acc1de3e047abc10762d74..74f80b8f77b69e3994a02986ea1688e8e319490b 100644 (file)
@@ -63,8 +63,10 @@ extern "C" {
  */
 #define MAX_BUFFER_SIZE                                (MAX_ACOUNT * MAX_BCOUNT * MAX_CCOUNT)
 
+#ifndef BUILD_TDA2XX_MPU
 /* To enable/disable the cache .*/
 #define EDMA3_ENABLE_DCACHE                 (1u)
+#endif
 
 /* OPT Field specific defines */
 #define OPT_SYNCDIM_SHIFT                   (0x00000002u)
index ed325f1c5a64dfbf7b600a01451dd3d78f4404c9..8b9363cad5564d9c153c35dc803cd18fa1f629cc 100755 (executable)
 # Derive SOC from PLATFORM
 #
 
+# tda2xx (Vayu) Simulator
+ifeq ($(PLATFORM),tda2xx-evm)
+ SOC = tda2xx
+ PLATFORM_XDC = "ti.platforms.simVayu"
+endif
+
 # ti816x (Netra) catalog EVM
 ifeq ($(PLATFORM),ti816x-evm)
  SOC = ti816x
@@ -140,6 +146,16 @@ endif
 
 # Derive Target/ISA from CORE
 
+# m4
+ifeq ($(CORE),m4)
+ ISA = m4
+endif
+
+# a15host
+ifeq ($(CORE),a15host)
+ ISA = a15
+endif
+
 # m3vpss
 ifeq ($(CORE),m3vpss)
  ISA = m3
@@ -215,6 +231,44 @@ endif
 # Derive XDC/ISA specific settings 
 #
 
+ifeq ($(ISA),m4)
+  ifeq ($(FORMAT),ELF)
+    TARGET_XDC = ti.targets.arm.elf.M4
+    FORMAT_EXT = e
+  else
+    TARGET_XDC = ti.targets.arm.M4
+  endif
+  
+  # If ENDIAN is set to "big", set ENDIAN_EXT to "e", that would be used in
+  #    in the filename extension of object/library/executable files
+  ifeq ($(ENDIAN),big)
+    ENDIAN_EXT = e
+  endif
+
+  # Define the file extensions
+  OBJEXT = o$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
+  LIBEXT = a$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
+  EXEEXT = x$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
+  ASMEXT = s$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)
+endif
+
+ifeq ($(ISA),a15)
+  TARGET_XDC = gnu.targets.arm.A15F
+
+  ifeq ($(FORMAT),ELF)
+    FORMAT_EXT = e
+  endif
+  ifeq ($(ENDIAN),big)
+    ENDIAN_EXT = e
+  endif
+
+  # Define the file extensions
+  OBJEXT = o$(FORMAT_EXT)a15f$(ENDIAN_EXT)
+  LIBEXT = a$(FORMAT_EXT)a15f$(ENDIAN_EXT)
+  EXEEXT = x$(FORMAT_EXT)a15f$(ENDIAN_EXT)
+  ASMEXT = s$(FORMAT_EXT)a15f$(ENDIAN_EXT)
+endif
+
 ifeq ($(ISA),m3)
   ifeq ($(FORMAT),ELF)
     TARGET_XDC = ti.targets.arm.elf.M3
diff --git a/makerules/rules_a15.mk b/makerules/rules_a15.mk
new file mode 100644 (file)
index 0000000..1856915
--- /dev/null
@@ -0,0 +1,194 @@
+# Filename: rules_a15.mk\r
+#\r
+# Make rules for A15 - This file has all the common rules and defines required\r
+#                     for Cortex-A15 ISA\r
+#\r
+# This file needs to change when:\r
+#     1. Code generation tool chain changes (This file uses Code Sourcery)\r
+#     2. Internal switches (which are normally not touched) has to change\r
+#     3. XDC specific switches change\r
+#     4. a rule common for A15 ISA has to be added or modified\r
+\r
+# Set compiler/archiver/linker commands and include paths\r
+CODEGEN_INCLUDE = $(CODEGEN_PATH_A15)/arm-none-eabi/include\r
+CC = $(CODEGEN_PATH_A15)/bin/arm-none-eabi-gcc \r
+AR = $(CODEGEN_PATH_A15)/bin/arm-none-eabi-ar\r
+LNK = $(CODEGEN_PATH_A15)/bin/arm-none-eabi-ld\r
+\r
+# XDC Specific defines\r
+ifneq ($(XDC_CFG_FILE_$(CORE)),)\r
+  ifeq ($(PROFILE_$(CORE)),debug)\r
+#    CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)a15f\r
+    CFG_CFILENAMEPART_XDC =pa15fg\r
+  endif\r
+  ifeq ($(PROFILE_$(CORE)),release)\r
+#    CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)a15f\r
+    CFG_CFILENAMEPART_XDC =pa15fg\r
+  endif\r
+  ifeq ($(PROFILE_$(CORE)),whole_program_debug)\r
+    CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)a15f$(ENDIAN_EXT)\r
+    CFG_LNKFILENAMEPART_XDC=_x\r
+  endif\r
+  CFG_CFILE_XDC =$(patsubst %.cfg,%_$(CFG_CFILENAMEPART_XDC).c,$(notdir $(XDC_CFG_FILE_$(CORE))))\r
+  CFG_C_XDC = $(addprefix $(CONFIGURO_DIR)/package/cfg/,$(CFG_CFILE_XDC))\r
+  XDCLNKCMD_FILE =$(patsubst %.c, %$(CFG_LNKFILENAMEPART_XDC)_x.xdl, $(CFG_C_XDC))\r
+# CFG_COBJ_XDC = $(patsubst %.c,%.$(OBJEXT),$(CFG_CFILE_XDC))\r
+  CFG_COBJ_XDC = $(patsubst %.c,%.oa15fg,$(CFG_CFILE_XDC))\r
+#  OBJ_PATHS += $(CFG_COBJ_XDC)\r
+  LNKCMD_FILE = $(CONFIGURO_DIR)/linker.cmd\r
+  SPACE := \r
+  SPACE += \r
+  XDC_GREP_STRING = $(CONFIGURO_DIRNAME)\r
+#  XDC_GREP_STRING = $(subst $(SPACE),\|,$(COMP_LIST_$(CORE)))\r
+#  XDC_GREP_STRING += \|$(CONFIGURO_DIRNAME)\r
+endif\r
+# Internal CFLAGS - normally doesn't change\r
+CFLAGS_INTERNAL = -Wall -Wunknown-pragmas -c -mcpu=cortex-a15 -g -mfpu=neon -mfloat-abi=hard -mabi=aapcs -mapcs-frame  \r
+#-ffunction-sections -fdata-sections\r
+CFLAGS_DIROPTS =\r
+\r
+#LNKFLAGS_INTERNAL = -nostartfiles -static -Wl,--gc-sections\r
+\r
+# CFLAGS based on profile selected\r
+CFLAGS_XDCINTERNAL = -Dxdc_target_name__=A15F -Dxdc_target_types__=gnu/targets/arm/std.h -Dxdc_cfg__header__='$(CONFIGURO_DIR)/package/cfg/$(XDC_CFG_BASE_FILE_NAME)_xem3.h'\r
+# Following 'if...' block is for an application; to add a #define for each\r
+#   component in the build. This is required to know - at compile time - which\r
+#   components are on which core.\r
+ifndef MODULE_NAME\r
+  # Derive list of all packages from each of the components needed by the app\r
+  PKG_LIST_LOCAL = $(foreach COMP,$(COMP_LIST_$(CORE)),$($(COMP)_PKG_LIST))\r
+  \r
+  # Defines for the app and cfg source code to know which components/packages\r
+  # are included in the build for the local CORE...\r
+  CFLAGS_APP_DEFINES = $(foreach PKG,$(PKG_LIST_LOCAL),-D_LOCAL_$(PKG)_)\r
+  CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_LOCAL),-D_BUILD_$(PKG)_)\r
+  \r
+  ifeq ($(CORE),a15host)\r
+    PKG_LIST_REMOTE = $(foreach COMP,$(COMP_LIST_a15host),$($(COMP)_PKG_LIST))\r
+    CFLAGS_APP_DEFINES += -D_LOCAL_CORE_a15host_\r
+  endif\r
+\r
+  # Defines for the app and cfg source code to know which components/packages\r
+  # are included in the build for the remote CORE...\r
+  CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_REMOTE),-D_REMOTE_$(PKG)_)\r
+  CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_REMOTE),-D_BUILD_$(PKG)_)\r
+endif\r
+ifeq ($(PROFILE_$(CORE)), debug)\r
+CFLAGS_INTERNAL += -D_DEBUG_=1\r
+endif\r
+ifeq ($(PROFILE_$(CORE)), release)\r
+ LNKFLAGS_INTERNAL_PROFILE =\r
+endif\r
+\r
+# Assemble CFLAGS from all other CFLAGS definitions\r
+_CFLAGS = $(CFLAGS_INTERNAL) $(CFLAGS_XDCINTERNAL) $(CFLAGS_GLOBAL_$(CORE)) $(CFLAGS_LOCAL_COMMON) $(CFLAGS_LOCAL_$(CORE)) $(CFLAGS_LOCAL_$(PLATFORM)) $(CFLAGS_LOCAL_$(SOC)) $(CFLAGS_APP_DEFINES) $(CFLAGS_COMP_COMMON) $(CFLAGS_GLOBAL_$(PLATFORM))\r
+\r
+# Object file creation\r
+# The second $(CC) compiles the source to generate object\r
+$(OBJ_PATHS): $(OBJDIR)/%.$(OBJEXT): %.c\r
+       $(ECHO) \# Compiling $(PLATFORM):$(CORE):$(PROFILE_$(CORE)):$(APP_NAME)$(MODULE_NAME): $<\r
+       $(CC) -c -MD -MF $@.dep $(_CFLAGS) $(INCLUDES) -o $(OBJDIR)/$(basename $(notdir $<)).$(OBJEXT) $<\r
+\r
+ASMFLAGS =\r
+# Object file creation\r
+$(OBJ_PATHS_ASM): $(OBJDIR)/%.$(OBJEXT): %.asm\r
+       $(ECHO) \# Compiling $(PLATFORM):$(CORE):$(PROFILE_$(CORE)):$(APP_NAME)$(MODULE_NAME): $<\r
+       $(CC) -c -x assembler-with-cpp $(_CFLAGS) $(ASMFLAGS) $(INCLUDES) -o $(OBJDIR)/$(basename $(notdir $<)).$(OBJEXT) $<\r
+\r
+$(PACKAGE_PATHS): $(PACKAGEDIR)/%: %\r
+       $(ECHO) \# Copying $(PACKAGE_NAME)/$($(MODULE_NAME)_RELPATH)/$<\r
+       $(MKDIR) -p $(DEST_ROOT)/package/$(PACKAGE_SELECT)/$(PACKAGE_NAME)/$($(MODULE_NAME)_RELPATH)\r
+       $(CP) --parents -rf $< $(DEST_ROOT)/package/$(PACKAGE_SELECT)/$(PACKAGE_NAME)/$($(MODULE_NAME)_RELPATH)\r
+\r
+# Archive flags - normally doesn't change\r
+ARFLAGS = cr\r
+\r
+# Archive/library file creation\r
+$(LIBDIR)/$(MODULE_NAME).$(LIBEXT) : $(OBJ_PATHS_ASM) $(OBJ_PATHS)\r
+       $(ECHO) \#\r
+       $(ECHO) \# Archiving $(PLATFORM):$(CORE):$(PROFILE_$(CORE)):$(MODULE_NAME)\r
+       $(ECHO) \#\r
+       $(AR) $(ARFLAGS) $@ $(OBJ_PATHS_ASM) $(OBJ_PATHS)\r
+\r
+# Linker options and rules\r
+LNKFLAGS_INTERNAL_COMMON =\r
+\r
+# Assemble Linker flags from all other LNKFLAGS definitions\r
+_LNKFLAGS = $(LNKFLAGS_INTERNAL) $(LNKFLAGS_INTERNAL_COMMON) $(LNKFLAGS_INTERNAL_PROFILE) $(LNKFLAGS_GLOBAL_$(CORE)) $(LNKFLAGS_LOCAL_COMMON) $(LNKFLAGS_LOCAL_$(CORE))\r
+\r
+# Path of the RTS library - normally doesn't change for a given tool-chain\r
+RTSLIB_PATH =\r
+LIB_PATHS += $(EXT_LIB_a15host) $(CODEGEN_PATH_A15)/arm-none-eabi/lib/fpu/libc.a $(CODEGEN_PATH_A15)/arm-none-eabi/lib/fpu/libg.a $(CODEGEN_PATH_A15)/arm-none-eabi/lib/fpu/libm.a $(CODEGEN_PATH_A15)/arm-none-eabi/lib/fpu/librdimon.a $(CODEGEN_PATH_A15)/lib/gcc/arm-none-eabi/4.7.3/fpu/libgcc.a\r
+\r
+\r
+LNK_LIBS = $(addprefix -l,$(LIB_PATHS))\r
+# Linker - to create executable file\r
+\r
+ifeq ($(LOCAL_APP_NAME),)\r
+ EXE_NAME = $(BINDIR)/$(APP_NAME)_$(CORE)_$(PROFILE_$(CORE)).$(EXEEXT)\r
+else\r
+ ifeq ($(PROFILE_$(CORE)),prod_release)\r
+  EXE_NAME = $(BINDIR)/$(LOCAL_APP_NAME).$(EXEEXT)\r
+ else\r
+  EXE_NAME = $(BINDIR)/$(LOCAL_APP_NAME)_$(PROFILE_$(CORE)).$(EXEEXT)\r
+ endif\r
+endif\r
+\r
+$(EXE_NAME) : $(OBJ_PATHS_ASM) $(OBJ_PATHS) $(LIB_PATHS) $(LNKCMD_FILE)  $(CONFIGURO_DIR)/package/cfg/$(CFG_COBJ_XDC)\r
+       $(ECHO) \# Linking into $(EXE_NAME)...\r
+       $(ECHO) \#\r
+       $(LNK) $(_LNKFLAGS) $(OBJ_PATHS_ASM) $(OBJ_PATHS) -T $(LNKCMD_FILE) -Map $@.map $(LIB_PATHS) -o $@ \r
+       $(ECHO) \#\r
+       $(ECHO) \# $@ created.\r
+       $(ECHO) \#\r
+\r
+# XDC specific - assemble XDC-Configuro command\r
+CONFIGURO_CMD = $(xdc_PATH)/xs xdc.tools.configuro --generationOnly -o $(CONFIGURO_DIR) -t $(TARGET_XDC) -p $(PLATFORM_XDC) \\r
+               -r debug -c $(CODEGEN_PATH_A15) -b $(CONFIG_BLD_XDC_$(ISA)) $(XDC_CFG_FILE_NAME)\r
+_XDC_GREP_STRING = \"$(XDC_GREP_STRING)\"\r
+EGREP_CMD = $(EGREP) -ivw $(XDC_GREP_STRING) $(XDCLNKCMD_FILE)\r
+\r
+ifneq ($(DEST_ROOT),)\r
+ DEST_ROOT += /\r
+endif\r
+# Invoke configuro for the rest of the components\r
+#  NOTE: 1. String handling is having issues with various make versions when the \r
+#           cammand is directly tried to be given below. Hence, as a work-around, \r
+#           the command is re-directed to a file (shell or batch file) and then \r
+#           executed\r
+#        2. The linker.cmd file generated, includes the libraries generated by\r
+#           XDC. An egrep to search for these and omit in the .cmd file is added\r
+#           after configuro is done\r
+#$(CFG_CFILE_XDC) : $(XDC_CFG_FILE)\r
+xdc_configuro : $(XDC_CFG_FILE)\r
+       $(ECHO) \# Invoking configuro...\r
+       $(ECHO) -e $(CONFIGURO_CMD) > $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat\r
+ifeq ($(OS),Windows_NT)\r
+       CACLS $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat /E /P Everyone:F\r
+       $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat\r
+else\r
+       $(CHMOD) a+x $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat\r
+       ./$(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat\r
+endif\r
+#      $(CP) $(XDCLNKCMD_FILE) $(LNKCMD_FILE)\r
+#      $(ECHO) @ $(EGREP_CMD) > maketemp_egrep_cmd.bat\r
+#      ./maketemp_egrep_cmd.bat | $(CYGWINPATH)/bin/tail -n+3 > $(LNKCMD_FILE)\r
+#      $(EGREP_CMD) > $(LNKCMD_FILE)\r
+#      $(EGREP) -iv "$(XDC_GREP_STRING)" $(XDCLNKCMD_FILE) > $(LNKCMD_FILE)\r
+       $(ECHO) \# Configuro done!\r
+\r
+$(LNKCMD_FILE) :\r
+#      $(CP) $(XDCLNKCMD_FILE) $(LNKCMD_FILE)\r
+#      $(ECHO) @ $(EGREP_CMD) > maketemp_egrep_cmd.bat\r
+#      ./maketemp_egrep_cmd.bat | $(CYGWINPATH)/bin/tail -n+3 > $(LNKCMD_FILE)\r
+#      $(EGREP_CMD) > $(LNKCMD_FILE)\r
\r
+ifndef MODULE_NAME\r
+$(CONFIGURO_DIR)/package/cfg/$(CFG_COBJ_XDC) : $(CFG_C_XDC)\r
+       $(ECHO) \# Compiling generated $< to $@ ...\r
+       $(CC) $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -o $(CONFIGURO_DIR)/package/cfg/$(CFG_COBJ_XDC) $(CFG_C_XDC)\r
+endif\r
+\r
+# Include dependency make files that were generated by $(CC)\r
+-include $(SRCS:%.c=$(DEPDIR)/%.P)\r
+# Nothing beyond this point\r
diff --git a/makerules/rules_m4.mk b/makerules/rules_m4.mk
new file mode 100644 (file)
index 0000000..a0ef238
--- /dev/null
@@ -0,0 +1,224 @@
+# Filename: rules_m4.mk\r
+#\r
+# Make rules for M4 - This file has all the common rules and defines required\r
+#                     for Cortex-M4 ISA\r
+#\r
+# This file needs to change when:\r
+#     1. Code generation tool chain changes (currently it uses TMS470)\r
+#     2. Internal switches (which are normally not touched) has to change\r
+#     3. XDC specific switches change\r
+#     4. a rule common for M4 ISA has to be added or modified\r
+\r
+# Set compiler/archiver/linker commands and include paths\r
+CODEGEN_INCLUDE = $(CODEGEN_PATH_M4)/include\r
+CC = $(CODEGEN_PATH_M4)/bin/cl470 \r
+AR = $(CODEGEN_PATH_M4)/bin/ar470\r
+LNK = $(CODEGEN_PATH_M4)/bin/lnk470\r
+\r
+# Derive a part of RTS Library name based on ENDIAN: little/big\r
+ifeq ($(ENDIAN),little)\r
+  RTSLIB_ENDIAN = le\r
+else\r
+  RTSLIB_ENDIAN = be\r
+endif\r
+\r
+# Derive compiler switch and part of RTS Library name based on FORMAT: COFF/ELF\r
+ifeq ($(FORMAT),COFF)\r
+  CSWITCH_FORMAT = ti_arm9_abi\r
+  RTSLIB_FORMAT = tiarm9\r
+endif\r
+ifeq ($(FORMAT),ELF)\r
+  CSWITCH_FORMAT = eabi\r
+  RTSLIB_FORMAT = eabi\r
+endif\r
+\r
+# Internal CFLAGS - normally doesn't change\r
+CFLAGS_INTERNAL = -c -qq -pdsw225 --endian=$(ENDIAN) -mv7M4 --float_support=vfplib --abi=$(CSWITCH_FORMAT) -eo.$(OBJEXT) -ea.$(ASMEXT) --symdebug:dwarf --embed_inline_assembly\r
+CFLAGS_DIROPTS = -fr=$(OBJDIR) -fs=$(OBJDIR)\r
+\r
+# XDC Specific defines\r
+ifneq ($(XDC_CFG_FILE_$(CORE)),)\r
+  ifeq ($(PROFILE_$(CORE)),debug)\r
+    CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)$(ISA)\r
+  endif\r
+  ifeq ($(PROFILE_$(CORE)),release)\r
+    CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)$(ISA)\r
+  endif\r
+  ifeq ($(PROFILE_$(CORE)),whole_program_debug)\r
+    CFG_CFILENAMEPART_XDC =p$(FORMAT_EXT)$(ISA)$(ENDIAN_EXT)\r
+#    CFG_LNKFILENAMEPART_XDC=_x\r
+       CFG_LNKFILENAMEPART_XDC=\r
+  endif\r
+  CFG_CFILE_XDC =$(patsubst %.cfg,%_$(CFG_CFILENAMEPART_XDC).c,$(notdir $(XDC_CFG_FILE_$(CORE))))\r
+  CFG_C_XDC = $(addprefix $(CONFIGURO_DIR)/package/cfg/,$(CFG_CFILE_XDC))\r
+  XDCLNKCMD_FILE =$(patsubst %.c, %$(CFG_LNKFILENAMEPART_XDC)_x.xdl, $(CFG_C_XDC))\r
+  CFG_COBJ_XDC = $(patsubst %.c,%.$(OBJEXT),$(CFG_CFILE_XDC))\r
+#  OBJ_PATHS += $(CFG_COBJ_XDC)\r
+  LNKCMD_FILE = $(CONFIGURO_DIR)/linker_mod.cmd\r
+  SPACE := \r
+  SPACE += \r
+  XDC_GREP_STRING = $(CONFIGURO_DIRNAME)\r
+#  XDC_GREP_STRING = $(subst $(SPACE),\|,$(COMP_LIST_$(CORE)))\r
+#  XDC_GREP_STRING += \|$(CONFIGURO_DIRNAME)\r
+endif\r
+\r
+# CFLAGS based on profile selected\r
+ifeq ($(PROFILE_$(CORE)), debug)\r
+ CFLAGS_XDCINTERNAL = -Dxdc_target_name__=M4 -Dxdc_target_types__=ti/targets/arm/elf/std.h -Dxdc_bld__profile_debug -Dxdc_bld__vers_1_0_4_6_1 -D_DEBUG_=1 \r
+ ifndef MODULE_NAME\r
+  CFLAGS_XDCINTERNAL += -Dxdc_cfg__header__='$(CONFIGURO_DIR)/package/cfg/$(XDC_CFG_BASE_FILE_NAME)_xem4.h' \r
+ endif\r
+ LNKFLAGS_INTERNAL_PROFILE = \r
+endif\r
+ifeq ($(PROFILE_$(CORE)), whole_program_debug)\r
+ CFLAGS_XDCINTERNAL = -Dxdc_target_name__=M4 -Dxdc_target_types__=ti/targets/arm/elf/std.h -Dxdc_bld__profile_whole_program_debug -Dxdc_bld__vers_1_0_4_6_1 -ms -oe \r
+ ifndef MODULE_NAME\r
+  CFLAGS_XDCINTERNAL += -Dxdc_cfg__header__='$(CONFIGURO_DIR)/package/cfg/$(XDC_CFG_BASE_FILE_NAME)_xem4.h' \r
+ endif\r
+# LNKFLAGS_INTERNAL_PROFILE = --opt='--endian=$(ENDIAN) -mv7M4 --abi=$(CSWITCH_FORMAT) -qq -pdsw225 $(CFLAGS_GLOBAL_$(CORE)) -oe --symdebug:dwarf -ms -op2 -O3 -k -os --optimize_with_debug --inline_recursion_limit=20' --strict_compatibility=on \r
+ LNKFLAGS_INTERNAL_PROFILE = --strict_compatibility=on \r
\r
+endif\r
+ifeq ($(PROFILE_$(CORE)), release)\r
+ CFLAGS_XDCINTERNAL = -Dxdc_target_name__=M4 -Dxdc_target_types__=ti/targets/arm/elf/std.h -Dxdc_bld__profile_debug -Dxdc_bld__vers_1_0_4_6_1 -O2\r
+ ifndef MODULE_NAME\r
+  CFLAGS_XDCINTERNAL += -Dxdc_cfg__header__='$(CONFIGURO_DIR)/package/cfg/$(XDC_CFG_BASE_FILE_NAME)_xem4.h' \r
+ endif\r
+ LNKFLAGS_INTERNAL_PROFILE = -o2\r
+endif\r
+\r
+# For generic platform define GENERIC in CFLAGS\r
+ifeq ($(PLATFORM),generic)\r
+ CFLAGS_XDCINTERNAL += -DGENERIC\r
+endif\r
+\r
+# Following 'if...' block is for an application; to add a #define for each\r
+#   component in the build. This is required to know - at compile time - which\r
+#   components are on which core.\r
+ifndef MODULE_NAME\r
+  # Derive list of all packages from each of the components needed by the app\r
+  PKG_LIST_M4_LOCAL = $(foreach COMP,$(COMP_LIST_$(CORE)),$($(COMP)_PKG_LIST))\r
+  \r
+  # Defines for the app and cfg source code to know which components/packages\r
+  # are included in the build for the local CORE...\r
+  CFLAGS_APP_DEFINES = $(foreach PKG,$(PKG_LIST_M4_LOCAL),-D_LOCAL_$(PKG)_)\r
+  CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_M4_LOCAL),-D_BUILD_$(PKG)_)\r
+  \r
+  ifeq ($(CORE),m4vpss)\r
+    PKG_LIST_M4_REMOTE = $(foreach COMP,$(COMP_LIST_m4video),$($(COMP)_PKG_LIST))\r
+    CFLAGS_APP_DEFINES += -D_LOCAL_CORE_m4vpss_\r
+  endif\r
+  ifeq ($(CORE),m4video)\r
+    PKG_LIST_M4_REMOTE = $(foreach COMP,$(COMP_LIST_m4vpss),$($(COMP)_PKG_LIST))\r
+    CFLAGS_APP_DEFINES += -D_LOCAL_CORE_m4video_\r
+  endif\r
+  PKG_LIST_A8_REMOTE = $(foreach COMP,$(COMP_LIST_a8host),$($(COMP)_PKG_LIST))\r
+\r
+  # Defines for the app and cfg source code to know which components/packages\r
+  # are included in the build for the remote CORE...\r
+  CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_M4_REMOTE),-D_REMOTE_$(PKG)_)\r
+  CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_M4_REMOTE),-D_BUILD_$(PKG)_)\r
+  CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_A8_REMOTE),-D_REMOTE_$(PKG)_)\r
+  CFLAGS_APP_DEFINES += $(foreach PKG,$(PKG_LIST_A8_REMOTE),-D_BUILD_$(PKG)_)\r
+endif\r
+\r
+# Assemble CFLAGS from all other CFLAGS definitions\r
+_CFLAGS = $(CFLAGS_INTERNAL) $(CFLAGS_GLOBAL_$(CORE)) $(CFLAGS_XDCINTERNAL) $(CFLAGS_LOCAL_COMMON) $(CFLAGS_LOCAL_$(CORE)) $(CFLAGS_LOCAL_$(PLATFORM)) $(CFLAGS_LOCAL_$(SOC)) $(CFLAGS_APP_DEFINES) $(CFLAGS_COMP_COMMON) $(CFLAGS_GLOBAL_$(PLATFORM))\r
+\r
+# Object file creation\r
+# The first $(CC) generates the dependency make files for each of the objects\r
+# The second $(CC) compiles the source to generate object\r
+$(OBJ_PATHS): $(OBJDIR)/%.$(OBJEXT): %.c\r
+       $(ECHO) \# Compiling $< to $@ ...\r
+       $(CC) -ppd=$(DEPFILE).P $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $<\r
+       $(CC) $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $<\r
+\r
+# Archive flags - normally doesn't change\r
+ARFLAGS = rq\r
+\r
+# Archive/library file creation\r
+$(LIBDIR)/$(MODULE_NAME).$(LIBEXT) : $(OBJ_PATHS)\r
+       $(ECHO) \#\r
+       $(ECHO) \# Archiving $(OBJ_PATHS) into $@...\r
+       $(ECHO) \#\r
+       $(AR) $(ARFLAGS) $@ $(OBJ_PATHS)\r
+\r
+# Linker options and rules\r
+LNKFLAGS_INTERNAL_COMMON = -w -q -u _c_int00 --silicon_version=7M4 -c --dynamic \r
+\r
+# Assemble Linker flags from all other LNKFLAGS definitions\r
+_LNKFLAGS = $(LNKFLAGS_INTERNAL_COMMON) $(LNKFLAGS_INTERNAL_PROFILE) $(LNKFLAGS_GLOBAL_$(CORE)) $(LNKFLAGS_LOCAL_COMMON) $(LNKFLAGS_LOCAL_$(CORE)) \r
+\r
+# Path of the RTS library - normally doesn't change for a given tool-chain\r
+RTSLIB_PATH = $(CODEGEN_PATH_M4)/lib/rtsv7M4_T_$(RTSLIB_ENDIAN)_$(RTSLIB_FORMAT).lib\r
+LIB_PATHS += $(RTSLIB_PATH)\r
+\r
+LNK_LIBS = $(addprefix -l,$(LIB_PATHS))\r
+ifeq ($(DEST_ROOT),)\r
+ TMPOBJDIR = .\r
+else\r
+ TMPOBJDIR = $(OBJDIR)\r
+endif\r
+# Linker - to create executable file \r
+$(BINDIR)/$(APP_NAME)_$(CORE)_$(PROFILE_$(CORE)).$(EXEEXT) : $(OBJ_PATHS) $(LIB_PATHS) $(LNKCMD_FILE) $(OBJDIR)/$(CFG_COBJ_XDC)\r
+       $(ECHO) \# Linking into $@\r
+       $(ECHO) \#\r
+       cd $(TMPOBJDIR) && $(LNK) $(_LNKFLAGS) $(OBJ_PATHS) $(OBJDIR)/$(CFG_COBJ_XDC) -l$(LNKCMD_FILE) sample_app/linker.cmd -o $@ -m $@.map $(LNK_LIBS)\r
+       $(ECHO) \#\r
+       $(ECHO) \# $@ created.\r
+       $(ECHO) \#\r
+\r
+# XDC specific - assemble XDC-Configuro command\r
+#CONFIGURO_CMD = $(xdc_PATH)/xs xdc.tools.configuro --generationOnly -o $(CONFIGURO_DIR) -t $(TARGET_XDC) -p $(PLATFORM_XDC) \\r
+#               $(CFGARGS_XDC) -r $(PROFILE_$(CORE)) -b $(CONFIG_BLD_XDC_$(ISA)) $(XDC_CFG_FILE_NAME)\r
+CONFIGURO_CMD = $(xdc_PATH)/xs xdc.tools.configuro --generationOnly -o $(CONFIGURO_DIR) -t $(TARGET_XDC) -p $(PLATFORM_XDC) \\r
+               -r whole_program -c $(CODEGEN_PATH_M4) -b $(CONFIG_BLD_XDC_$(ISA)) $(XDC_CFG_FILE_NAME)                    \r
+_XDC_GREP_STRING = \"$(XDC_GREP_STRING)\"\r
+EGREP_CMD = $(EGREP) -ivw $(XDC_GREP_STRING) $(XDCLNKCMD_FILE)\r
+\r
+ifneq ($(DEST_ROOT),)\r
+ DEST_ROOT += /\r
+endif\r
+# Invoke configuro for the rest of the components\r
+#  NOTE: 1. String handling is having issues with various make versions when the \r
+#           cammand is directly tried to be given below. Hence, as a work-around, \r
+#           the command is re-directed to a file (shell or batch file) and then \r
+#           executed\r
+#        2. The linker.cmd file generated, includes the libraries generated by\r
+#           XDC. An egrep to search for these and omit in the .cmd file is added\r
+#           after configuro is done\r
+#$(CFG_CFILE_XDC) : $(XDC_CFG_FILE)\r
+xdc_configuro : $(XDC_CFG_FILE) $(CONFIGURO_DIR)\r
+       $(ECHO) \# Invoking configuro...\r
+       $(ECHO) -e $(CONFIGURO_CMD) > $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat\r
+ifeq ($(OS),Windows_NT)\r
+       CACLS $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat /E /P Everyone:F\r
+       $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat\r
+else\r
+       $(CHMOD) a+x $(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat\r
+       ./$(DEST_ROOT)maketemp_configuro_cmd_$(CORE).bat\r
+endif\r
+       $(CP) $(XDCLNKCMD_FILE) $(LNKCMD_FILE)\r
+#      $(ECHO) @ $(EGREP_CMD) > maketemp_egrep_cmd.bat\r
+#      ./maketemp_egrep_cmd.bat | $(CYGWINPATH)/bin/tail -n+3 > $(LNKCMD_FILE)\r
+#      $(EGREP_CMD) > $(LNKCMD_FILE)\r
+#      $(EGREP) -iv "$(XDC_GREP_STRING)" $(XDCLNKCMD_FILE) > $(LNKCMD_FILE)\r
+       $(ECHO) \# Configuro done!\r
+\r
+$(LNKCMD_FILE) :\r
+#      $(CP) $(XDCLNKCMD_FILE) $(LNKCMD_FILE)\r
+#      $(ECHO) @ $(EGREP_CMD) > maketemp_egrep_cmd.bat\r
+#      ./maketemp_egrep_cmd.bat | $(CYGWINPATH)/bin/tail -n+3 > $(LNKCMD_FILE)\r
+#      $(EGREP_CMD) > $(LNKCMD_FILE)\r
\r
+ifndef MODULE_NAME\r
+$(OBJDIR)/$(CFG_COBJ_XDC) : $(CFG_C_XDC)\r
+       $(ECHO) \# Compiling generated $< to $@ ...\r
+       $(CC) -ppd=$(DEPFILE).P $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $(CFG_C_XDC)\r
+       $(CC) $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $(CFG_C_XDC)\r
+endif\r
+\r
+# Include dependency make files that were generated by $(CC)\r
+-include $(SRCS:%.c=$(DEPDIR)/%.P)\r
+\r
+# Nothing beyond this point\r
index b02322e59671ffa61ded368882f25801783c37df..8c304a2107abd6762108766c8ca01fd9b66e991c 100755 (executable)
@@ -60,11 +60,11 @@ edma3_lld_EXAMPLES_LIST = edma3_drv_ti816x-evm_m3_example edma3_drv_c6472-evm_64
 
 
 ifeq ($(PLATFORM),)
-PLATFORM = ti816x-evm ti814x-evm c6a811x-evm c6472-evm c6670-evm c6678-evm c6748-evm da830-evm omapl138-evm tci6486-evm tci6608-sim tci6616-sim tci6614-evm tci6614-sim c6657-evm c6657-sim tci6634-evm tci6634-sim
+PLATFORM = tda2xx-evm ti816x-evm ti814x-evm c6a811x-evm c6472-evm c6670-evm c6678-evm c6748-evm da830-evm omapl138-evm tci6486-evm tci6608-sim tci6616-sim tci6614-evm tci6614-sim c6657-evm c6657-sim tci6634-evm tci6634-sim
 endif
 
 ifeq ($(TARGET),)
-TARGET = 674 m3 a8 64p 66
+TARGET = 674 m3 a8 64p 66 m4 a15
 edma3_lld_LIBS_ALL = edma3_lld_rm_generic
 endif
 
@@ -225,4 +225,11 @@ edma3_drv_tci6634-evm_66_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_t
 
 edma3_drv_tci6634-evm_66_be_example_EXAMPLES_RELPATH = examples/edma3_driver/evmTCI6634BE
 edma3_drv_tci6634-evm_66_be_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tci6634-evm_66_be_example_EXAMPLES_RELPATH)
+
+edma3_drv_tda2xx-evm_m4_example_EXAMPLES_RELPATH = examples/edma3_driver/evmtda2xx_M4
+edma3_drv_tda2xx-evm_m4_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tda2xx-evm_m4_example_EXAMPLES_RELPATH)
+
+edma3_drv_tda2xx-evm_a15_example_EXAMPLES_RELPATH = examples/edma3_driver/evmtda2xx_A15
+edma3_drv_tda2xx-evm_a15_example_EXAMPLES_PATH = $(edma3_lld_PATH)/$(edma3_drv_tda2xx-evm_a15_example_EXAMPLES_RELPATH)
+
 # Nothing beyond this point
index de928a16bc9e818e7d84a48efedc817ec88832e8..3a753d6b5d5f4a09aee630bc65b703070e946925 100755 (executable)
@@ -57,6 +57,116 @@ cleanexamples: $(CLEANALL_EXAMPLES)
 #=======================================================================================================================================
 
 
+#=======================================================================================================================================
+#To Build libs For Platform tda2xx-evm Target m4
+edma3_lld_tda2xx-evm_m4_libs: edma3_lld_tda2xx-evm_m4_libs_drv edma3_lld_tda2xx-evm_m4_libs_rm edma3_lld_tda2xx-evm_m4_libs_drvsample edma3_lld_tda2xx-evm_m4_libs_rmsample
+edma3_lld_tda2xx-evm_m4_libs_drv:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making m4:debug:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Making m4:release:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+endif
+edma3_lld_tda2xx-evm_m4_libs_rm:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+endif
+edma3_lld_tda2xx-evm_m4_libs_drvsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+endif
+edma3_lld_tda2xx-evm_m4_libs_rmsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+endif
+
+#To Clean libs For Platform tda2xx-evm Target m4
+edma3_lld_tda2xx-evm_m4_libs_clean: edma3_lld_tda2xx-evm_m4_libs_drv_clean edma3_lld_tda2xx-evm_m4_libs_rm_clean edma3_lld_tda2xx-evm_m4_libs_drvsample_clean edma3_lld_tda2xx-evm_m4_libs_rmsample_clean
+edma3_lld_tda2xx-evm_m4_libs_drv_clean:
+       $(ECHO) \# Cleaning m4:debug:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Cleaning m4:release:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+edma3_lld_tda2xx-evm_m4_libs_rm_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+edma3_lld_tda2xx-evm_m4_libs_drvsample_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+edma3_lld_tda2xx-evm_m4_libs_rmsample_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+
+#=======================================================================================================================================
+#To Build libs For Platform tda2xx-evm Target a15
+edma3_lld_tda2xx-evm_a15_libs: edma3_lld_tda2xx-evm_a15_libs_drv edma3_lld_tda2xx-evm_a15_libs_rm edma3_lld_tda2xx-evm_a15_libs_drvsample edma3_lld_tda2xx-evm_a15_libs_rmsample
+edma3_lld_tda2xx-evm_a15_libs_drv:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making a15:debug:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Making a15:release:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+endif
+edma3_lld_tda2xx-evm_a15_libs_rm:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+endif
+edma3_lld_tda2xx-evm_a15_libs_drvsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+endif
+edma3_lld_tda2xx-evm_a15_libs_rmsample:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Making tda2xx-evm:debug:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Making tda2xx-evm:rel:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+endif
+
+#To Clean libs For Platform tda2xx-evm Target a15
+edma3_lld_tda2xx-evm_a15_libs_clean: edma3_lld_tda2xx-evm_a15_libs_drv_clean edma3_lld_tda2xx-evm_a15_libs_rm_clean edma3_lld_tda2xx-evm_a15_libs_drvsample_clean edma3_lld_tda2xx-evm_a15_libs_rmsample_clean
+edma3_lld_tda2xx-evm_a15_libs_drv_clean:
+       $(ECHO) \# Cleaning a15:debug:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Cleaning a15:release:edma3_lld_drv
+       $(MAKE) -C $(edma3_lld_drv_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+edma3_lld_tda2xx-evm_a15_libs_rm_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm
+       $(MAKE) -C $(edma3_lld_rm_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+edma3_lld_tda2xx-evm_a15_libs_drvsample_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_drv_sample
+       $(MAKE) -C $(edma3_lld_drv_sample_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+edma3_lld_tda2xx-evm_a15_libs_rmsample_clean:
+       $(ECHO) \# Cleaning tda2xx-evm:debug:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Cleaning tda2xx-evm:rel:edma3_lld_rm_sample
+       $(MAKE) -C $(edma3_lld_rm_sample_PATH) clean PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+
 #=======================================================================================================================================
 #To Build libs For Platform ti816x-evm Target 674
 edma3_lld_ti816x-evm_674_libs: edma3_lld_ti816x-evm_674_libs_drv edma3_lld_ti816x-evm_674_libs_rm edma3_lld_ti816x-evm_674_libs_drvsample edma3_lld_ti816x-evm_674_libs_rmsample
@@ -2365,6 +2475,32 @@ ifeq ($(FORMAT),ELF)
        $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=c6a811x-evm CORE=m3vpss PROFILE_m3vpss=release
 endif
 
+edma3_drv_tda2xx-evm_m4_example:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Configuring XDC packages for $@:m4:debug 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Making example $@:debug
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug     
+
+       $(ECHO) \# Configuring XDC packages for $@:m4:release 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+       $(ECHO) \# Making example $@:release
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+endif
+
+edma3_drv_tda2xx-evm_a15_example:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Configuring XDC packages for $@:a15host:debug 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug
+       $(ECHO) \# Making example $@:debug
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=debug   
+
+       $(ECHO) \# Configuring XDC packages for $@:a15host:release 
+       $(MAKE) -C $($@_EXAMPLES_PATH) xdc_configuro PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+       $(ECHO) \# Making example $@:release
+       $(MAKE) -C $($@_EXAMPLES_PATH) PLATFORM=tda2xx-evm CORE=a15host PROFILE_a15host=release
+endif
+
 #=======================================================================================================================================
 #
 # Rule to clean all examples
@@ -2481,6 +2617,14 @@ ifeq ($(FORMAT),ELF)
        $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean  PLATFORM=ti814x-evm CORE=m3video PROFILE_m3video=release
 endif
 
+edma3_drv_tda2xx-evm_m4_example_clean:
+ifeq ($(FORMAT),ELF)
+       $(ECHO) \# Cleaning example $@:debug
+       $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean  PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=debug
+       $(ECHO) \# Cleaning example $@:release
+       $(MAKE) -C $($(subst _clean,,$@)_EXAMPLES_PATH) clean  PLATFORM=tda2xx-evm CORE=m4 PROFILE_m4=release
+endif
+
 edma3_drv_ti816x-evm_m3_example_clean:
 ifeq ($(FORMAT),ELF)
        $(ECHO) \# Cleaning example $@:debug
index 43109db330519753e24936472801b2914c687bfb..cad6f5cf65b060b5069bd5ee3fb385b6424f8e84 100755 (executable)
@@ -46,7 +46,9 @@ CFLAGS_LOCAL_c6a811x-evm = -DBUILD_C6A811X_DSP
 SRCS_c6a811x-evm = sample_c6a811x_cfg.c sample_c6a811x_int_reg.c
 else
 SRCS_omapl138-evm = sample_omapl138_arm_cfg.c sample_omapl138_arm_int_reg.c
+SRCS_tda2xx-evm = sample_tda2xx_cfg.c sample_tda2xx_arm_int_reg.c
 endif
+
 ifeq ($(CORE),a8host)
 CFLAGS_LOCAL_ti816x-evm = -DBUILD_NETRA_A8
 CFLAGS_LOCAL_ti814x-evm = -DBUILD_CENTAURUS_A8
@@ -71,6 +73,12 @@ SRCS_ti816x-evm = sample_ti816x_cfg.c sample_ti816x_arm_int_reg.c
 SRCS_ti814x-evm = sample_ti814x_cfg.c sample_ti814x_arm_int_reg.c
 SRCS_c6a811x-evm = sample_c6a811x_cfg.c sample_c6a811x_arm_int_reg.c
 endif
+ifeq ($(CORE),m4)
+CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_IPU1
+endif
+ifeq ($(CORE),a15host)
+CFLAGS_LOCAL_tda2xx-evm = -DBUILD_TDA2XX_MPU
+endif
 SRCS_c6748-evm = sample_c6748_cfg.c sample_c6748_int_reg.c
 SRCS_da830-evm = sample_da830_cfg.c sample_da830_int_reg.c
 
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_arm_int_reg.c
new file mode 100644 (file)
index 0000000..84dd33f
--- /dev/null
@@ -0,0 +1,372 @@
+/*\r
+ * sample_tda2xx_int_reg.c\r
+ *\r
+ * Platform specific interrupt registration and un-registration routines.\r
+ *\r
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ *  Redistribution and use in source and binary forms, with or without\r
+ *  modification, are permitted provided that the following conditions\r
+ *  are met:\r
+ *\r
+ *    Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ *    Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the\r
+ *    distribution.\r
+ *\r
+ *    Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#include <ti/sysbios/knl/Semaphore.h>\r
+#include <ti/sysbios/hal/Hwi.h>\r
+#include <ti/sysbios/hal/vayu/IntXbar.h>\r
+#include <ti/sysbios/family/arm/a15/Mmu.h>\r
+#include <xdc/runtime/Error.h>\r
+#include <xdc/runtime/System.h>\r
+\r
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>\r
+\r
+/**\r
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user\r
+  * (Not all TC error ISRs need to be registered, register only for the\r
+  * available Transfer Controllers).\r
+  */\r
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(uint32_t arg) =\r
+                                                {\r
+                                                &lisrEdma3TC0ErrHandler0,\r
+                                                &lisrEdma3TC1ErrHandler0,\r
+                                                &lisrEdma3TC2ErrHandler0,\r
+                                                &lisrEdma3TC3ErrHandler0,\r
+                                                &lisrEdma3TC4ErrHandler0,\r
+                                                &lisrEdma3TC5ErrHandler0,\r
+                                                &lisrEdma3TC6ErrHandler0,\r
+                                                &lisrEdma3TC7ErrHandler0,\r
+                                                };\r
+\r
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];\r
+extern unsigned int ccErrorInt[];\r
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];\r
+extern unsigned int numEdma3Tc[];\r
+extern unsigned int ccXferCompIntXbarInstNo[][EDMA3_MAX_REGIONS];\r
+extern unsigned int ccCompEdmaXbarIndex[][EDMA3_MAX_REGIONS];\r
+extern unsigned int ccErrorIntXbarInstNo[];\r
+extern unsigned int ccErrEdmaXbarIndex[];\r
+extern unsigned int tcErrorIntXbarInstNo[][EDMA3_MAX_TC];\r
+extern unsigned int tcErrEdmaXbarIndex[][EDMA3_MAX_TC];\r
+\r
+/**\r
+ * Variables which will be used internally for referring the hardware interrupt\r
+ * for various EDMA3 interrupts.\r
+ */\r
+extern unsigned int hwIntXferComp[];\r
+extern unsigned int hwIntCcErr[];\r
+extern unsigned int hwIntTcErr[];\r
+\r
+extern unsigned int dsp_num;\r
+/* This variable has to be used as an extern */\r
+unsigned int gpp_num = 0;\r
+\r
+Hwi_Handle hwiCCXferCompInt;\r
+Hwi_Handle hwiCCErrInt;\r
+Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];\r
+\r
+/* External Instance Specific Configuration Structure */\r
+extern EDMA3_DRV_GblXbarToChanConfigParams \r
+                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];\r
+\r
+typedef struct  {\r
+    volatile Uint32 DSP_INTMUX[21];\r
+    volatile Uint32 DUCATI_INTMUX[15];\r
+    volatile Uint32 TPCC_EVTMUX[16];\r
+    volatile Uint32 TIMER_EVTCAPT;\r
+    volatile Uint32 GPIO_MUX;\r
+} CSL_IntmuxRegs;\r
+\r
+typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;\r
+\r
+\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)\r
+\r
+\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)\r
+\r
+\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)\r
+\r
+\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)\r
+\r
+\r
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u)\r
+#define EDMA3_NUM_TCC                     (64u)\r
+\r
+/*\r
+ * Forward decleration\r
+ */\r
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
+                 unsigned int *chanNum,\r
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);\r
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
+                                  unsigned int chanNum);\r
+\r
+void Edma3MemProtectionHandler(unsigned int edma3InstanceId);\r
+\r
+/**  To Register the ISRs with the underlying OS, if required. */\r
+void registerEdma3Interrupts (unsigned int edma3Id)\r
+    {\r
+    static UInt32 cookie = 0;\r
+    unsigned int numTc = 0;\r
+       \r
+       IntXbar_connect(ccXferCompIntXbarInstNo[edma3Id][dsp_num], ccCompEdmaXbarIndex[edma3Id][dsp_num]);\r
+       IntXbar_connect(ccErrorIntXbarInstNo[edma3Id], ccErrEdmaXbarIndex[edma3Id]);\r
+       IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][0], tcErrEdmaXbarIndex[edma3Id][0]);\r
+       IntXbar_connect(tcErrorIntXbarInstNo[edma3Id][1], tcErrEdmaXbarIndex[edma3Id][1]);\r
+       \r
+//     *((volatile UInt32 *) 0x4A002544U) = (UInt32) 0xF757FDC0;\r
+\r
+    Hwi_Params hwiParams; \r
+    Error_Block      eb;\r
+\r
+    /* Initialize the Error Block                                             */\r
+    Error_init(&eb);\r
+        \r
+    /* Disabling the global interrupts */\r
+    cookie = Hwi_disable();\r
+\r
+    /* Initialize the HWI parameters with user specified values */\r
+    Hwi_Params_init(&hwiParams);\r
+    \r
+    /* argument for the ISR */\r
+    hwiParams.arg = edma3Id;\r
+       /* set the priority ID     */\r
+       //hwiParams.priority = hwIntXferComp[edma3Id];\r
+    \r
+    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][dsp_num],\r
+                                       (&lisrEdma3ComplHandler0),\r
+                                       (const Hwi_Params *) (&hwiParams),\r
+                                       &eb);\r
+    if (TRUE == Error_check(&eb))\r
+    {\r
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
+    }\r
+#if 0\r
+    /* Initialize the HWI parameters with user specified values */\r
+    Hwi_Params_init(&hwiParams);\r
+    /* argument for the ISR */\r
+    hwiParams.arg = edma3Id;\r
+       /* set the priority ID     */\r
+       //hwiParams.priority = hwIntCcErr[edma3Id];\r
+       \r
+       hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],\r
+                (&lisrEdma3CCErrHandler0),\r
+                (const Hwi_Params *) (&hwiParams),\r
+                &eb);\r
+\r
+    if (TRUE == Error_check(&eb))\r
+    {\r
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
+    }\r
+\r
+    while (numTc < numEdma3Tc[edma3Id])\r
+           {\r
+        /* Initialize the HWI parameters with user specified values */\r
+        Hwi_Params_init(&hwiParams);\r
+        /* argument for the ISR */\r
+        hwiParams.arg = edma3Id;\r
+       /* set the priority ID     */\r
+        //hwiParams.priority = hwIntTcErr[edma3Id];\r
+        \r
+        hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],\r
+                    (ptrEdma3TcIsrHandler[numTc]),\r
+                    (const Hwi_Params *) (&hwiParams),\r
+                    &eb);\r
+        if (TRUE == Error_check(&eb))\r
+        {\r
+            System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
+        }\r
+        numTc++;\r
+       }\r
+#endif\r
+   /**\r
+    * Enabling the HWI_ID.\r
+    * EDMA3 interrupts (transfer completion, CC error etc.)\r
+    * correspond to different ECM events (SoC specific). These ECM events come\r
+    * under ECM block XXX (handling those specific ECM events). Normally, block\r
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this\r
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the\r
+    * API C64_enableIER(), in which the YYY bit is SET.\r
+    */\r
+    Hwi_enableInterrupt(ccErrorInt[edma3Id]);\r
+#if 0\r
+    Hwi_enableInterrupt(ccXferCompInt[edma3Id][dsp_num]);\r
+    numTc = 0;\r
+    while (numTc < numEdma3Tc[edma3Id])\r
+           {\r
+        Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);\r
+        numTc++;\r
+       }\r
+#endif\r
+    /* Restore interrupts */\r
+    Hwi_restore(cookie);\r
+    }\r
+\r
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */\r
+void unregisterEdma3Interrupts (unsigned int edma3Id)\r
+    {\r
+       static UInt32 cookie = 0;\r
+    unsigned int numTc = 0;\r
+\r
+    /* Disabling the global interrupts */\r
+    cookie = Hwi_disable();\r
+\r
+    Hwi_delete(&hwiCCXferCompInt);\r
+    Hwi_delete(&hwiCCErrInt);\r
+    while (numTc < numEdma3Tc[edma3Id])\r
+           {\r
+        Hwi_delete(&hwiTCErrInt[numTc]);\r
+        numTc++;\r
+       }\r
+    /* Restore interrupts */\r
+    Hwi_restore(cookie);\r
+    }\r
+\r
+/**\r
+ * \brief   sampleMapXbarEvtToChan\r
+ *\r
+ * This function reads from the sample configuration structure which specifies \r
+ * cross bar events mapped to DMA channel.\r
+ *\r
+ * \return  EDMA3_DRV_SOK if success, else error code\r
+ */\r
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
+                 unsigned int *chanNum,\r
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)\r
+       {\r
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
+    unsigned int xbarEvtNum = 0;\r
+    int          edmaChanNum = 0;\r
+\r
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&\r
+               (chanNum != NULL) &&\r
+               (edmaGblXbarConfig != NULL))\r
+               {\r
+               xbarEvtNum = eventNum - EDMA3_NUM_TCC;\r
+               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];\r
+               if (edmaChanNum != -1)\r
+                       {\r
+                       *chanNum = edmaChanNum;\r
+                       edma3Result = EDMA3_DRV_SOK;\r
+                       }\r
+               }\r
+       return (edma3Result);\r
+       }\r
+\r
+\r
+/**\r
+ * \brief   sampleConfigScr\r
+ *\r
+ * This function configures control config registers for the cross bar events \r
+ * mapped to the EDMA channel.\r
+ *\r
+ * \return  EDMA3_DRV_SOK if success, else error code\r
+ */\r
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
+                                  unsigned int chanNum)\r
+       {\r
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;\r
+    unsigned int scrChanOffset = 0;\r
+    unsigned int scrRegOffset  = 0;\r
+    unsigned int xBarEvtNum    = 0;\r
+    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00);\r
+\r
+\r
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&\r
+               (chanNum < EDMA3_NUM_TCC))\r
+               {\r
+               scrRegOffset = chanNum / 4;\r
+               scrChanOffset = chanNum - (scrRegOffset * 4);\r
+               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;\r
+               \r
+               switch(scrChanOffset)\r
+                       {\r
+                       case 0:\r
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
+                                       (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);\r
+                               break;\r
+                       case 1:\r
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & \r
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));\r
+                               break;\r
+                       case 2:\r
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & \r
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));\r
+                               break;\r
+                       case 3:\r
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & \r
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));\r
+                               break;\r
+                       default:\r
+                               edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
+                               break;\r
+                       }\r
+               }\r
+       else\r
+               {\r
+               edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
+               }\r
+       return edma3Result;\r
+       }\r
+\r
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, \r
+                                   unsigned int edma3Id)\r
+    {\r
+    EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;\r
+    const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =\r
+                                &(sampleXbarChanInitConfig[edma3Id][dsp_num]);\r
+    if (hEdma != NULL)\r
+        {\r
+        retVal = EDMA3_DRV_initXbarEventMap(hEdma, \r
+                                                                       sampleXbarToChanConfig, \r
+                                                                       &sampleMapXbarEvtToChan, \r
+                                                                       &sampleConfigScr);\r
+        }\r
+    \r
+    return retVal;\r
+    }\r
+\r
+void Edma3MemProtectionHandler(unsigned int edma3InstanceId)\r
+    {\r
+    printf("memory Protection error");\r
+    }\r
diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_tda2xx_cfg.c
new file mode 100644 (file)
index 0000000..54aba28
--- /dev/null
@@ -0,0 +1,999 @@
+/*\r
+ * sample_tda2xx_cfg.c\r
+ *\r
+ * SoC specific EDMA3 hardware related information like number of transfer\r
+ * controllers, various interrupt ids etc. It is used while interrupts\r
+ * enabling / disabling. It needs to be ported for different SoCs.\r
+ *\r
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ *  Redistribution and use in source and binary forms, with or without\r
+ *  modification, are permitted provided that the following conditions\r
+ *  are met:\r
+ *\r
+ *    Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ *    Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the\r
+ *    distribution.\r
+ *\r
+ *    Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#include <ti/sdo/edma3/drv/edma3_drv.h>\r
+\r
+/* Number of EDMA3 controllers present in the system */\r
+#define NUM_EDMA3_INSTANCES         1u\r
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
+\r
+/* Number of DSPs present in the system */\r
+#define NUM_DSPS                    1u\r
+const unsigned int numDsps = NUM_DSPS;\r
+\r
+/* Determine the processor id by reading DNUM register. */\r
+/* Statically allocate the region numbers with cores. */\r
+unsigned short determineProcId()\r
+{\r
+#ifdef BUILD_TDA2XX_MPU\r
+       return 0;\r
+#elif defined BUILD_TDA2XX_DSP\r
+       return 1;\r
+#elif defined BUILD_TDA2XX_IPU0\r
+       return 2;\r
+#elif defined BUILD_TDA2XX_IPU1\r
+       return 3;\r
+#else\r
+       return 4;\r
+#endif\r
+}\r
+\r
+signed char*  getGlobalAddr(signed char* addr)\r
+{\r
+     return (addr); /* The address is already a global address */\r
+}\r
+unsigned short isGblConfigRequired(unsigned int dspNum)\r
+{\r
+    (void) dspNum;\r
+       return 1;\r
+}\r
+\r
+/* Semaphore handles */\r
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
+\r
+/** Number of PaRAM Sets available                                            */\r
+#define EDMA3_NUM_PARAMSET                              (512u)\r
+\r
+/** Number of TCCS available                                                  */\r
+#define EDMA3_NUM_TCC                                   (64u)\r
+\r
+/** Number of DMA Channels available                                          */\r
+#define EDMA3_NUM_DMA_CHANNELS                          (64u)\r
+\r
+/** Number of QDMA Channels available                                         */\r
+#define EDMA3_NUM_QDMA_CHANNELS                         (8u)\r
+\r
+/** Number of Event Queues available                                          */\r
+#define EDMA3_NUM_EVTQUE                                (4u)\r
+\r
+/** Number of Transfer Controllers available                                  */\r
+#define EDMA3_NUM_TC                                    (2u)\r
+\r
+/** Number of Regions                                                         */\r
+#define EDMA3_NUM_REGIONS                               (8u)\r
+\r
+/** Interrupt no. for Transfer Completion */\r
+//#define EDMA3_CC_XFER_COMPLETION_INT_A15                (66u)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_A15                (34u)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_DSP                (34u)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU0               (34u)\r
+#define EDMA3_CC_XFER_COMPLETION_INT_IPU1               (34u)\r
+/** Based on the interrupt number to be mapped define the XBAR instance number */\r
+#define COMPLETION_INT_A15_XBAR_INST_NO                 (29u)\r
+#define COMPLETION_INT_DSP_XBAR_INST_NO                 (3u)\r
+#define COMPLETION_INT_IPU0_XBAR_INST_NO                (12u)\r
+#define COMPLETION_INT_IPU1_XBAR_INST_NO                (12u)\r
+\r
+/** Interrupt no. for CC Error */\r
+//#define EDMA3_CC_ERROR_INT_A15                          (67u)\r
+#define EDMA3_CC_ERROR_INT_A15                          (35u)\r
+#define EDMA3_CC_ERROR_INT_DSP                          (35u)\r
+#define EDMA3_CC_ERROR_INT_IPU0                         (35u)\r
+#define EDMA3_CC_ERROR_INT_IPU1                         (35u)\r
+/** Based on the interrupt number to be mapped define the XBAR instance number */\r
+#define CC_ERROR_INT_A15_XBAR_INST_NO                   (30u)\r
+#define CC_ERROR_INT_DSP_XBAR_INST_NO                   (4u)\r
+#define CC_ERROR_INT_IPU0_XBAR_INST_NO                  (13u)\r
+#define CC_ERROR_INT_IPU1_XBAR_INST_NO                  (13u)\r
+\r
+\r
+/** Interrupt no. for TCs Error */\r
+#define EDMA3_TC0_ERROR_INT_A15                         (36u)\r
+#define EDMA3_TC0_ERROR_INT_DSP                         (36u)\r
+#define EDMA3_TC0_ERROR_INT_IPU0                        (36u)\r
+#define EDMA3_TC0_ERROR_INT_IPU1                        (36u)\r
+#define EDMA3_TC1_ERROR_INT_A15                         (37u)\r
+#define EDMA3_TC1_ERROR_INT_DSP                         (37u)\r
+#define EDMA3_TC1_ERROR_INT_IPU0                        (37u)\r
+#define EDMA3_TC1_ERROR_INT_IPU1                        (37u)\r
+/** Based on the interrupt number to be mapped define the XBAR instance number */\r
+#define TC0_ERROR_INT_A15_XBAR_INST_NO                  (31u)\r
+#define TC0_ERROR_INT_DSP_XBAR_INST_NO                  (5u)\r
+#define TC0_ERROR_INT_IPU0_XBAR_INST_NO                 (14u)\r
+#define TC0_ERROR_INT_IPU1_XBAR_INST_NO                 (14u)\r
+#define TC1_ERROR_INT_A15_XBAR_INST_NO                  (32u)\r
+#define TC1_ERROR_INT_DSP_XBAR_INST_NO                  (6u)\r
+#define TC1_ERROR_INT_IPU0_XBAR_INST_NO                 (15u)\r
+#define TC1_ERROR_INT_IPU1_XBAR_INST_NO                 (15u)\r
+\r
+#ifdef BUILD_TDA2XX_MPU\r
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_A15\r
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_A15\r
+#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_A15_XBAR_INST_NO\r
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_A15\r
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_A15\r
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO\r
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO\r
+\r
+#elif defined BUILD_TDA2XX_DSP\r
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_DSP\r
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_DSP\r
+#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_DSP_XBAR_INST_NO\r
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_DSP\r
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_DSP\r
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_DSP_XBAR_INST_NO\r
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_DSP_XBAR_INST_NO\r
+\r
+#elif defined BUILD_TDA2XX_IPU1\r
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_IPU0\r
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_IPU0\r
+#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_IPU0_XBAR_INST_NO\r
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_IPU0\r
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_IPU0\r
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_IPU0_XBAR_INST_NO\r
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU0_XBAR_INST_NO\r
+\r
+#elif defined BUILD_TDA2XX_IPU2\r
+#define EDMA3_CC_XFER_COMPLETION_INT                    EDMA3_CC_XFER_COMPLETION_INT_IPU1\r
+#define EDMA3_CC_ERROR_INT                              EDMA3_CC_ERROR_INT_IPU1\r
+#define CC_ERROR_INT_XBAR_INST_NO                       CC_ERROR_INT_IPU1_XBAR_INST_NO\r
+#define EDMA3_TC0_ERROR_INT                             EDMA3_TC0_ERROR_INT_IPU1\r
+#define EDMA3_TC1_ERROR_INT                             EDMA3_TC1_ERROR_INT_IPU1\r
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_IPU1_XBAR_INST_NO\r
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_IPU1_XBAR_INST_NO\r
+\r
+#else\r
+#define EDMA3_CC_XFER_COMPLETION_INT                    {0u}\r
+#define EDMA3_CC_ERROR_INT                              {0u}\r
+#define CC_ERROR_INT_XBAR_INST_NO                       {0u}\r
+#define EDMA3_TC0_ERROR_INT                             (0u)\r
+#define EDMA3_TC1_ERROR_INT                             (0u)\r
+#define TC0_ERROR_INT_XBAR_INST_NO                      TC0_ERROR_INT_A15_XBAR_INST_NO\r
+#define TC1_ERROR_INT_XBAR_INST_NO                      TC1_ERROR_INT_A15_XBAR_INST_NO\r
+#endif\r
+\r
+#define EDMA3_TC2_ERROR_INT                             (0u)\r
+#define EDMA3_TC3_ERROR_INT                             (0u)\r
+#define EDMA3_TC4_ERROR_INT                             (0u)\r
+#define EDMA3_TC5_ERROR_INT                             (0u)\r
+#define EDMA3_TC6_ERROR_INT                             (0u)\r
+#define EDMA3_TC7_ERROR_INT                             (0u)\r
+\r
+/** XBAR interrupt source index numbers for EDMA interrupts */\r
+#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368u)\r
+\r
+#define XBAR_EDMA_TPCC_IRQ_ERR                          (359u)\r
+#define XBAR_EDMA_TC0_IRQ_ERR                           (370u)\r
+#define XBAR_EDMA_TC1_IRQ_ERR                           (371u)\r
+\r
+/**\r
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
+ * various peripherals, which use EDMA for data transfer.\r
+ * All channels need not be mapped, some can be free also.\r
+ * 1: Mapped\r
+ * 0: Not mapped\r
+ *\r
+ * This mapping will be used to allocate DMA channels when user passes\r
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
+ * copy). The same mapping is used to allocate the TCC when user passes\r
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
+ *\r
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
+ */\r
+                                                      /* 31     0 */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0x00000000u)  /* TBD */\r
+\r
+\r
+/**\r
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
+ * various peripherals, which use EDMA for data transfer.\r
+ * All channels need not be mapped, some can be free also.\r
+ * 1: Mapped\r
+ * 0: Not mapped\r
+ *\r
+ * This mapping will be used to allocate DMA channels when user passes\r
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
+ * copy). The same mapping is used to allocate the TCC when user passes\r
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
+ *\r
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
+ */\r
+#define EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0x00000000u) /* TBD */\r
+\r
+\r
+/* Variable which will be used internally for referring number of Event Queues*/\r
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {\r
+                                                        EDMA3_NUM_EVTQUE,\r
+                                                    };\r
+\r
+/* Variable which will be used internally for referring number of TCs.        */\r
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {\r
+                                                    EDMA3_NUM_TC,\r
+                                                };\r
+\r
+/**\r
+ * Variable which will be used internally for referring transfer completion\r
+ * interrupt.\r
+ */\r
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+{\r
+    {\r
+        EDMA3_CC_XFER_COMPLETION_INT_A15, EDMA3_CC_XFER_COMPLETION_INT_DSP,\r
+               EDMA3_CC_XFER_COMPLETION_INT_IPU0, EDMA3_CC_XFER_COMPLETION_INT_IPU1,\r
+        0u, 0u, 0u, 0u,\r
+    },\r
+};\r
+/** These are the Xbar instance numbers corresponding to interrupt numbers */\r
+unsigned int ccXferCompIntXbarInstNo[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+{\r
+    {\r
+        COMPLETION_INT_A15_XBAR_INST_NO, COMPLETION_INT_DSP_XBAR_INST_NO,\r
+               COMPLETION_INT_IPU0_XBAR_INST_NO, COMPLETION_INT_IPU1_XBAR_INST_NO,\r
+        0u, 0u, 0u, 0u,\r
+    },\r
+};\r
+\r
+/** These are the Interrupt Crossbar Index For EDMA Completion for different regions */\r
+unsigned int ccCompEdmaXbarIndex[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+{\r
+       {\r
+               XBAR_EDMA_TPCC_IRQ_REGION0, XBAR_EDMA_TPCC_IRQ_REGION1, XBAR_EDMA_TPCC_IRQ_REGION2, XBAR_EDMA_TPCC_IRQ_REGION3,\r
+               XBAR_EDMA_TPCC_IRQ_REGION4, XBAR_EDMA_TPCC_IRQ_REGION5, XBAR_EDMA_TPCC_IRQ_REGION6, XBAR_EDMA_TPCC_IRQ_REGION7,\r
+       }\r
+};\r
+\r
+/**\r
+ * Variable which will be used internally for referring channel controller's\r
+ * error interrupt.\r
+ */\r
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {\r
+                                                    EDMA3_CC_ERROR_INT,\r
+                                               };\r
+unsigned int ccErrorIntXbarInstNo[NUM_EDMA3_INSTANCES] = {\r
+                                                    CC_ERROR_INT_XBAR_INST_NO,\r
+                                               };\r
+unsigned int ccErrEdmaXbarIndex[NUM_EDMA3_INSTANCES] = \r
+{\r
+       XBAR_EDMA_TPCC_IRQ_ERR,\r
+};\r
+\r
+/**\r
+ * Variable which will be used internally for referring transfer controllers'\r
+ * error interrupts.\r
+ */\r
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =\r
+{\r
+   {\r
+       EDMA3_TC0_ERROR_INT, EDMA3_TC1_ERROR_INT,\r
+       EDMA3_TC2_ERROR_INT, EDMA3_TC3_ERROR_INT,\r
+       EDMA3_TC4_ERROR_INT, EDMA3_TC5_ERROR_INT,\r
+       EDMA3_TC6_ERROR_INT, EDMA3_TC7_ERROR_INT,\r
+   }\r
+};\r
+unsigned int tcErrorIntXbarInstNo[NUM_EDMA3_INSTANCES][8] =\r
+{\r
+   {\r
+       TC0_ERROR_INT_XBAR_INST_NO, TC1_ERROR_INT_XBAR_INST_NO,\r
+       0u, 0u,\r
+       0u, 0u,\r
+       0u, 0u,\r
+   }\r
+};\r
+\r
+unsigned int tcErrEdmaXbarIndex[NUM_EDMA3_INSTANCES][8] =\r
+{\r
+   {\r
+       XBAR_EDMA_TC0_IRQ_ERR, XBAR_EDMA_TC0_IRQ_ERR,\r
+          0u, 0u,\r
+       0u, 0u, 0u, 0u,\r
+   }\r
+};\r
+\r
+#if 0\r
+/**\r
+ * Variables which will be used internally for referring the hardware interrupt\r
+ * for various EDMA3 interrupts.\r
+ */\r
+unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {\r
+                                                    EDMA3_HWI_INT_XFER_COMP\r
+                                                  };\r
+\r
+unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {\r
+                                                   EDMA3_HWI_INT_CC_ERR\r
+                                               };\r
+\r
+unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {\r
+                                                     {\r
+                                                        EDMA3_HWI_INT_TC0_ERR,\r
+                                                        EDMA3_HWI_INT_TC1_ERR,\r
+                                                        EDMA3_HWI_INT_TC2_ERR,\r
+                                                        EDMA3_HWI_INT_TC3_ERR\r
+                                                     }\r
+                                               };\r
+#endif\r
+/**\r
+ * \brief Base address as seen from the different cores may be different\r
+ * And is defined based on the core\r
+ */\r
+#ifdef BUILD_TDA2XX_MPU\r
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))\r
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))\r
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))\r
+#elif ((defined BUILD_TDA2XX_IPU0) || (defined BUILD_TDA2XX_IPU1))\r
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0xA0000000))\r
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0xA0100000))\r
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0xA0200000))\r
+#else\r
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x0))\r
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x0))\r
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x0))\r
+#endif\r
+/* Driver Object Initialization Configuration */\r
+EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
+{\r
+    {\r
+        /* EDMA3 INSTANCE# 0 */\r
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
+        EDMA3_NUM_DMA_CHANNELS,\r
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
+        EDMA3_NUM_QDMA_CHANNELS,\r
+        /** Total number of TCCs supported by the EDMA3 Controller            */\r
+        EDMA3_NUM_TCC,\r
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
+        EDMA3_NUM_PARAMSET,\r
+        /** Total number of Event Queues in the EDMA3 Controller              */\r
+        EDMA3_NUM_EVTQUE,\r
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
+        EDMA3_NUM_TC,\r
+        /** Number of Regions on this EDMA3 controller                        */\r
+        EDMA3_NUM_REGIONS,\r
+\r
+        /**\r
+         * \brief Channel mapping existence\r
+         * A value of 0 (No channel mapping) implies that there is fixed association\r
+         * for a channel number to a parameter entry number or, in other words,\r
+         * PaRAM entry n corresponds to channel n.\r
+         */\r
+        1u,\r
+\r
+        /** Existence of memory protection feature */\r
+        0u,\r
+\r
+        /** Global Register Region of CC Registers */\r
+        EDMA3_CC_BASE_ADDR,\r
+        /** Transfer Controller (TC) Registers */\r
+        {\r
+               EDMA3_TC0_BASE_ADDR,\r
+               EDMA3_TC1_BASE_ADDR,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL\r
+        },\r
+        /** Interrupt no. for Transfer Completion */\r
+        EDMA3_CC_XFER_COMPLETION_INT,\r
+        /** Interrupt no. for CC Error */\r
+        EDMA3_CC_ERROR_INT,\r
+        /** Interrupt no. for TCs Error */\r
+        {\r
+            EDMA3_TC0_ERROR_INT,\r
+            EDMA3_TC1_ERROR_INT,\r
+            EDMA3_TC2_ERROR_INT,\r
+            EDMA3_TC3_ERROR_INT,\r
+            EDMA3_TC4_ERROR_INT,\r
+            EDMA3_TC5_ERROR_INT,\r
+            EDMA3_TC6_ERROR_INT,\r
+            EDMA3_TC7_ERROR_INT\r
+        },\r
+\r
+        /**\r
+         * \brief EDMA3 TC priority setting\r
+         *\r
+         * User can program the priority of the Event Queues\r
+         * at a system-wide level.  This means that the user can set the\r
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
+         * relative to IO initiated by the other bus masters on the\r
+         * device (ARM, DSP, USB, etc)\r
+         */\r
+        {\r
+            0u,\r
+            1u,\r
+            2u,\r
+            3u,\r
+            0u,\r
+            0u,\r
+            0u,\r
+            0u\r
+        },\r
+        /**\r
+         * \brief To Configure the Threshold level of number of events\r
+         * that can be queued up in the Event queues. EDMA3CC error register\r
+         * (CCERR) will indicate whether or not at any instant of time the\r
+         * number of events queued up in any of the event queues exceeds\r
+         * or equals the threshold/watermark value that is set\r
+         * in the queue watermark threshold register (QWMTHRA).\r
+         */\r
+        {\r
+            16u,\r
+            16u,\r
+            16u,\r
+            16u,\r
+            0u,\r
+            0u,\r
+            0u,\r
+            0u\r
+        },\r
+\r
+        /**\r
+         * \brief To Configure the Default Burst Size (DBS) of TCs.\r
+         * An optimally-sized command is defined by the transfer controller\r
+         * default burst size (DBS). Different TCs can have different\r
+         * DBS values. It is defined in Bytes.\r
+         */\r
+            {\r
+            16u,\r
+            16u,\r
+            16u,\r
+            16u,\r
+            0u,\r
+            0u,\r
+            0u,\r
+            0u\r
+            },\r
+\r
+        /**\r
+         * \brief Mapping from each DMA channel to a Parameter RAM set,\r
+         * if it exists, otherwise of no use.\r
+         */\r
+            {\r
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
+            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, \r
+            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
+            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
+            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
+            },\r
+\r
+         /**\r
+          * \brief Mapping from each DMA channel to a TCC. This specific\r
+          * TCC code will be returned when the transfer is completed\r
+          * on the mapped channel.\r
+          */\r
+            {\r
+            0u, 1u, 2u, 3u,\r
+            4u, 5u, 6u, 7u,\r
+            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+            12u, 13u, 14u, 15u,\r
+            16u, 17u, 18u, 19u,\r
+            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+            24u, 25u, 26u, 27u,\r
+            28u, 29u, 30u, 31u,\r
+            32u, 33u, 34u, 35u,\r
+            36u, 37u, 38u, 39u,\r
+            40u, 41u, 42u, 43u,\r
+            44u, 45u, 46u, 47u,\r
+            48u, 49u, 50u, 51u,\r
+            52u, 53u, 54u, 55u,\r
+            56u, 57u, 58u, 59u,\r
+            60u, 61u, 62u, 63u\r
+            },\r
+\r
+        /**\r
+         * \brief Mapping of DMA channels to Hardware Events from\r
+         * various peripherals, which use EDMA for data transfer.\r
+         * All channels need not be mapped, some can be free also.\r
+         */\r
+            {\r
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_0,\r
+            EDMA3_DMA_CHANNEL_TO_EVENT_MAPPING_1\r
+            }\r
+        },\r
+};\r
+\r
+/**\r
+ * \brief Resource splitting defines for Own/Reserved DMA/QDMA channels and TCCs\r
+ * For PaRAMs explicit defines are not present but should be replaced in the structure sampleInstInitConfig\r
+ * Default configuration has all resources owned by all cores and none reserved except for first 64 PaRAMs corrosponding to DMA channels\r
+ * Resources to be Split properly by application and rebuild the sample library to avoid resource conflict\r
+ *\r
+ * Only Resources owned by a perticular core are allocated by Driver\r
+ * Reserved resources are not allocated if requested for any available resource\r
+ */\r
\r
+/* Driver Instance Initialization Configuration */\r
+EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+    {\r
+               /* EDMA3 INSTANCE# 0 */\r
+               {\r
+                       /* Resources owned/reserved by region 0 (Associated to any MPU core)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+                       },\r
+\r
+                       /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+           },\r
+    };\r
+\r
+/* Driver Instance Cross bar event to channel map Initialization Configuration */\r
+EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+{\r
+    /* EDMA3 INSTANCE# 0 */\r
+    {\r
+        /* Event to channel map for region 0 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, 26, 27, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 1 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, 26, 27, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 2 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 3 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 4 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 5 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 6 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 7 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+    }\r
+};\r
+\r
+/* End of File */\r
+\r
index 168f0371a3d66bfb105a19b20882deedc7fb2a13..df43c9c1ffec546e4db4a4407eb99e7f82f7bde4 100644 (file)
@@ -50,6 +50,7 @@ SRCS_c6748-evm = edma3_c6748_cfg.c
 SRCS_da830-evm = edma3_da830_cfg.c
 SRCS_omap4-evm = edma3_omap4_cfg.c
 SRCS_ti814x-evm = edma3_ti814x_cfg.c
+SRCS_tda2xx-evm = edma3_tda2xx_cfg.c
 SRCS_ti816x-evm = edma3_ti816x_cfg.c
 SRCS_c6a811x-evm = edma3_c6a811x_cfg.c
 SRCS_ti816x-sim = edma3_ti816x_cfg.c
index a10a264c1d873f6c1219f42ece0fa97d045f183f..129815dbde82d22fb64fce1ef819575e43abaddf 100755 (executable)
@@ -44,6 +44,7 @@ CFLAGS_LOCAL_c6a811x-evm = -DBUILD_C6A811X_DSP
 SRCS_c6a811x-evm = sample_c6a811x_cfg.c sample_c6a811x_int_reg.c
 else
 SRCS_omapl138-evm = sample_omapl138_arm_cfg.c sample_omapl138_arm_int_reg.c
+SRCS_tda2xx-evm = sample_tda2xx_cfg.c sample_tda2xx_arm_int_reg.c
 endif
 ifeq ($(CORE),a8host)
 CFLAGS_LOCAL_c6a811x-evm = -DBUILD_C6A811X_A8
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda2xx_arm_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda2xx_arm_int_reg.c
new file mode 100644 (file)
index 0000000..5d9ce96
--- /dev/null
@@ -0,0 +1,357 @@
+/*\r
+ * sample_ti814x_int_reg.c\r
+ *\r
+ * Platform specific interrupt registration and un-registration routines.\r
+ *\r
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ *  Redistribution and use in source and binary forms, with or without\r
+ *  modification, are permitted provided that the following conditions\r
+ *  are met:\r
+ *\r
+ *    Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ *    Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the\r
+ *    distribution.\r
+ *\r
+ *    Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#include <ti/sysbios/knl/Semaphore.h>\r
+#include <ti/sysbios/hal/Hwi.h>\r
+#include <xdc/runtime/Error.h>\r
+#include <xdc/runtime/System.h>\r
+\r
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>\r
+\r
+/**\r
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user\r
+  * (Not all TC error ISRs need to be registered, register only for the\r
+  * available Transfer Controllers).\r
+  */\r
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =\r
+                                                {\r
+                                                &lisrEdma3TC0ErrHandler0,\r
+                                                &lisrEdma3TC1ErrHandler0,\r
+                                                &lisrEdma3TC2ErrHandler0,\r
+                                                &lisrEdma3TC3ErrHandler0,\r
+                                                &lisrEdma3TC4ErrHandler0,\r
+                                                &lisrEdma3TC5ErrHandler0,\r
+                                                &lisrEdma3TC6ErrHandler0,\r
+                                                &lisrEdma3TC7ErrHandler0,\r
+                                                };\r
+\r
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];\r
+extern unsigned int ccErrorInt[];\r
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];\r
+extern unsigned int numEdma3Tc[];\r
+\r
+/**\r
+ * Variables which will be used internally for referring the hardware interrupt\r
+ * for various EDMA3 interrupts.\r
+ */\r
+extern unsigned int hwIntXferComp[];\r
+extern unsigned int hwIntCcErr[];\r
+extern unsigned int hwIntTcErr[];\r
+\r
+extern unsigned int dsp_num;\r
+/* This variable has to be used as an extern */\r
+unsigned int gpp_num = 0;\r
+\r
+Hwi_Handle hwiCCXferCompInt;\r
+Hwi_Handle hwiCCErrInt;\r
+Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC];\r
+\r
+/* External Instance Specific Configuration Structure */\r
+extern EDMA3_DRV_GblXbarToChanConfigParams \r
+                                                               sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS];\r
+\r
+typedef struct  {\r
+    volatile Uint32 DSP_INTMUX[21];\r
+    volatile Uint32 DUCATI_INTMUX[15];\r
+    volatile Uint32 TPCC_EVTMUX[16];\r
+    volatile Uint32 TIMER_EVTCAPT;\r
+    volatile Uint32 GPIO_MUX;\r
+} CSL_IntmuxRegs;\r
+\r
+typedef volatile CSL_IntmuxRegs     *CSL_IntmuxRegsOvly;\r
+\r
+\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u)\r
+\r
+\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u)\r
+\r
+\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u)\r
+\r
+\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u)\r
+#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u)\r
+\r
+\r
+#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u)\r
+#define EDMA3_NUM_TCC                     (64u)\r
+\r
+/*\r
+ * Forward decleration\r
+ */\r
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
+                 unsigned int *chanNum,\r
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig);\r
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
+                                  unsigned int chanNum);\r
+\r
+void Edma3MemProtectionHandler(unsigned int edma3InstanceId);\r
+\r
+/**  To Register the ISRs with the underlying OS, if required. */\r
+void registerEdma3Interrupts (unsigned int edma3Id)\r
+    {\r
+    static UInt32 cookie = 0;\r
+    unsigned int numTc = 0;\r
+    Hwi_Params hwiParams; \r
+    Error_Block      eb;\r
+\r
+    /* Initialize the Error Block                                             */\r
+    Error_init(&eb);\r
+        \r
+    /* Disabling the global interrupts */\r
+    cookie = Hwi_disable();\r
+\r
+    /* Initialize the HWI parameters with user specified values */\r
+    Hwi_Params_init(&hwiParams);\r
+    \r
+    /* argument for the ISR */\r
+    hwiParams.arg = edma3Id;\r
+       /* set the priority ID     */\r
+       hwiParams.priority = hwIntXferComp[edma3Id];\r
+    \r
+    hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][gpp_num],\r
+                                       (&lisrEdma3ComplHandler0),\r
+                                       (const Hwi_Params *) (&hwiParams),\r
+                                       &eb);\r
+    if (TRUE == Error_check(&eb))\r
+    {\r
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
+    }\r
+\r
+    /* Initialize the HWI parameters with user specified values */\r
+    Hwi_Params_init(&hwiParams);\r
+    /* argument for the ISR */\r
+    hwiParams.arg = edma3Id;\r
+       /* set the priority ID     */\r
+       hwiParams.priority = hwIntCcErr[edma3Id];\r
+       \r
+       hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id],\r
+                (&lisrEdma3CCErrHandler0),\r
+                (const Hwi_Params *) (&hwiParams),\r
+                &eb);\r
+\r
+    if (TRUE == Error_check(&eb))\r
+    {\r
+        System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
+    }\r
+\r
+    while (numTc < numEdma3Tc[edma3Id])\r
+           {\r
+        /* Initialize the HWI parameters with user specified values */\r
+        Hwi_Params_init(&hwiParams);\r
+        /* argument for the ISR */\r
+        hwiParams.arg = edma3Id;\r
+       /* set the priority ID     */\r
+        hwiParams.priority = hwIntTcErr[edma3Id];\r
+        \r
+        hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc],\r
+                    (ptrEdma3TcIsrHandler[numTc]),\r
+                    (const Hwi_Params *) (&hwiParams),\r
+                    &eb);\r
+        if (TRUE == Error_check(&eb))\r
+        {\r
+            System_printf("HWI Create Failed\n",Error_getCode(&eb));\r
+        }\r
+        numTc++;\r
+       }\r
+   /**\r
+    * Enabling the HWI_ID.\r
+    * EDMA3 interrupts (transfer completion, CC error etc.)\r
+    * correspond to different ECM events (SoC specific). These ECM events come\r
+    * under ECM block XXX (handling those specific ECM events). Normally, block\r
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this\r
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the\r
+    * API C64_enableIER(), in which the YYY bit is SET.\r
+    */\r
+    Hwi_enableInterrupt(ccErrorInt[edma3Id]);\r
+#if 0\r
+    Hwi_enableInterrupt(13);\r
+#endif\r
+    Hwi_enableInterrupt(ccXferCompInt[edma3Id][gpp_num]);\r
+    numTc = 0;\r
+    while (numTc < numEdma3Tc[edma3Id])\r
+           {\r
+        Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]);\r
+        numTc++;\r
+       }\r
+\r
+    /* Restore interrupts */\r
+    Hwi_restore(cookie);\r
+    }\r
+\r
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */\r
+void unregisterEdma3Interrupts (unsigned int edma3Id)\r
+    {\r
+       static UInt32 cookie = 0;\r
+    unsigned int numTc = 0;\r
+\r
+    /* Disabling the global interrupts */\r
+    cookie = Hwi_disable();\r
+\r
+    Hwi_delete(&hwiCCXferCompInt);\r
+    Hwi_delete(&hwiCCErrInt);\r
+    while (numTc < numEdma3Tc[edma3Id])\r
+           {\r
+        Hwi_delete(&hwiTCErrInt[numTc]);\r
+        numTc++;\r
+       }\r
+    /* Restore interrupts */\r
+    Hwi_restore(cookie);\r
+    }\r
+\r
+/**\r
+ * \brief   sampleMapXbarEvtToChan\r
+ *\r
+ * This function reads from the sample configuration structure which specifies \r
+ * cross bar events mapped to DMA channel.\r
+ *\r
+ * \return  EDMA3_DRV_SOK if success, else error code\r
+ */\r
+EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum,\r
+                 unsigned int *chanNum,\r
+                 const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig)\r
+       {\r
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
+    unsigned int xbarEvtNum = 0;\r
+    int          edmaChanNum = 0;\r
+\r
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&\r
+               (chanNum != NULL) &&\r
+               (edmaGblXbarConfig != NULL))\r
+               {\r
+               xbarEvtNum = eventNum - EDMA3_NUM_TCC;\r
+               edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum];\r
+               if (edmaChanNum != -1)\r
+                       {\r
+                       *chanNum = edmaChanNum;\r
+                       edma3Result = EDMA3_DRV_SOK;\r
+                       }\r
+               }\r
+       return (edma3Result);\r
+       }\r
+\r
+\r
+/**\r
+ * \brief   sampleConfigScr\r
+ *\r
+ * This function configures control config registers for the cross bar events \r
+ * mapped to the EDMA channel.\r
+ *\r
+ * \return  EDMA3_DRV_SOK if success, else error code\r
+ */\r
+EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum,\r
+                                  unsigned int chanNum)\r
+       {\r
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK;\r
+    unsigned int scrChanOffset = 0;\r
+    unsigned int scrRegOffset  = 0;\r
+    unsigned int xBarEvtNum    = 0;\r
+    CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00);\r
+\r
+\r
+       if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) &&\r
+               (chanNum < EDMA3_NUM_TCC))\r
+               {\r
+               scrRegOffset = chanNum / 4;\r
+               scrChanOffset = chanNum - (scrRegOffset * 4);\r
+               xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1;\r
+               \r
+               switch(scrChanOffset)\r
+                       {\r
+                       case 0:\r
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
+                                       (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK);\r
+                               break;\r
+                       case 1:\r
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & \r
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK));\r
+                               break;\r
+                       case 2:\r
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & \r
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK));\r
+                               break;\r
+                       case 3:\r
+                               scrEvtMux->TPCC_EVTMUX[scrRegOffset] |=\r
+                                       ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & \r
+                                       (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK));\r
+                               break;\r
+                       default:\r
+                               edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
+                               break;\r
+                       }\r
+               }\r
+       else\r
+               {\r
+               edma3Result = EDMA3_DRV_E_INVALID_PARAM;\r
+               }\r
+       return edma3Result;\r
+       }\r
+\r
+EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, \r
+                                   unsigned int edma3Id)\r
+    {\r
+    EDMA3_DRV_Result retVal = EDMA3_DRV_SOK;\r
+    const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig =\r
+                                &(sampleXbarChanInitConfig[edma3Id][dsp_num]);\r
+    if (hEdma != NULL)\r
+        {\r
+        retVal = EDMA3_DRV_initXbarEventMap(hEdma, \r
+                                                                       sampleXbarToChanConfig, \r
+                                                                       &sampleMapXbarEvtToChan, \r
+                                                                       &sampleConfigScr);\r
+        }\r
+    \r
+    return retVal;\r
+    }\r
+\r
+void Edma3MemProtectionHandler(unsigned int edma3InstanceId)\r
+    {\r
+    printf("memory Protection error");\r
+    }\r
diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda2xx_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_tda2xx_cfg.c
new file mode 100644 (file)
index 0000000..1bd77df
--- /dev/null
@@ -0,0 +1,859 @@
+/*\r
+ * sample_omapl138_cfg.c\r
+ *\r
+ * Platform specific EDMA3 hardware related information like number of transfer\r
+ * controllers, various interrupt ids etc. It is used while interrupts\r
+ * enabling / disabling. It needs to be ported for different SoCs.\r
+ *\r
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ *  Redistribution and use in source and binary forms, with or without\r
+ *  modification, are permitted provided that the following conditions\r
+ *  are met:\r
+ *\r
+ *    Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ *    Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the\r
+ *    distribution.\r
+ *\r
+ *    Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#include <ti/sdo/edma3/rm/edma3_rm.h>\r
+\r
+/* Number of EDMA3 controllers present in the system */\r
+#define NUM_EDMA3_INSTANCES         1u\r
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;\r
+\r
+/* Number of DSPs present in the system */\r
+#define NUM_DSPS                    1u\r
+const unsigned int numDsps = NUM_DSPS;\r
+\r
+/* Determine the processor id by reading DNUM register. */\r
+unsigned short determineProcId()\r
+{\r
+#ifdef BUILD_TDA2XX_MPU\r
+       return 0;\r
+#elif defined BUILD_TDA2XX_DSP\r
+       return 1;\r
+#elif defined BUILD_TDA2XX_IPU0\r
+       return 2;\r
+#elif defined BUILD_TDA2XX_IPU1\r
+       return 3;\r
+#else\r
+       return 4;\r
+#endif\r
+}\r
+\r
+signed char*  getGlobalAddr(signed char* addr)\r
+{\r
+     return (addr); /* The address is already a global address */\r
+}\r
+unsigned short isGblConfigRequired(unsigned int dspNum)\r
+{\r
+    (void) dspNum;\r
+\r
+    return 1;\r
+}\r
+\r
+/* Semaphore handles */\r
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};\r
+\r
+/** Number of PaRAM Sets available                                            */\r
+#define EDMA3_NUM_PARAMSET                              (512u)\r
+\r
+/** Number of TCCS available                                                  */\r
+#define EDMA3_NUM_TCC                                   (64u)\r
+\r
+/** Number of DMA Channels available                                          */\r
+#define EDMA3_NUM_DMA_CHANNELS                          (64u)\r
+\r
+/** Number of QDMA Channels available                                         */\r
+#define EDMA3_NUM_QDMA_CHANNELS                         (8u)\r
+\r
+/** Number of Event Queues available                                          */\r
+#define EDMA3_0_NUM_EVTQUE                              (4u)\r
+\r
+/** Number of Transfer Controllers available                                  */\r
+#define EDMA3_0_NUM_TC                                  (4u)\r
+\r
+/** Number of Regions                                                         */\r
+#define EDMA3_0_NUM_REGIONS                             (2u)\r
+\r
+\r
+/** Interrupt no. for Transfer Completion                                     */\r
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (34u)\r
+/** Interrupt no. for CC Error                                                */\r
+#define EDMA3_0_CC_ERROR_INT                            (35u)\r
+/** Interrupt no. for TCs Error                                               */\r
+#define EDMA3_0_TC0_ERROR_INT                           (36u)\r
+#define EDMA3_0_TC1_ERROR_INT                           (37u)\r
+#define EDMA3_0_TC2_ERROR_INT                           (0u)\r
+#define EDMA3_0_TC3_ERROR_INT                           (0u)\r
+#define EDMA3_0_TC4_ERROR_INT                           (0u)\r
+#define EDMA3_0_TC5_ERROR_INT                           (0u)\r
+#define EDMA3_0_TC6_ERROR_INT                           (0u)\r
+#define EDMA3_0_TC7_ERROR_INT                           (0u)\r
+\r
+/**\r
+ * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different\r
+ * ECM events (SoC specific). These ECM events come\r
+ * under ECM block XXX (handling those specific ECM events). Normally, block\r
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events\r
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)\r
+ * is mapped to a specific HWI_INT YYY in the tcf file.\r
+ * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding\r
+ * to transfer completion interrupt.\r
+ * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding\r
+ * to CC error interrupts.\r
+ * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding\r
+ * to TC error interrupts.\r
+ */\r
+/* EDMA 0 */\r
+\r
+#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)\r
+#define EDMA3_0_HWI_INT_CC_ERR                              (7u)\r
+#define EDMA3_0_HWI_INT_TC0_ERR                             (7u)\r
+#define EDMA3_0_HWI_INT_TC1_ERR                             (7u)\r
+#define EDMA3_0_HWI_INT_TC2_ERR                             (7u)\r
+#define EDMA3_0_HWI_INT_TC3_ERR                             (7u)\r
+\r
+\r
+/**\r
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
+ * various peripherals, which use EDMA for data transfer.\r
+ * All channels need not be mapped, some can be free also.\r
+ * 1: Mapped\r
+ * 0: Not mapped\r
+ *\r
+ * This mapping will be used to allocate DMA channels when user passes\r
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
+ * copy). The same mapping is used to allocate the TCC when user passes\r
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
+ *\r
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
+ */\r
+                                                      /* 31     0 */\r
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0x00000000u)  /* TBD */\r
+\r
+\r
+/**\r
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
+ * various peripherals, which use EDMA for data transfer.\r
+ * All channels need not be mapped, some can be free also.\r
+ * 1: Mapped\r
+ * 0: Not mapped\r
+ *\r
+ * This mapping will be used to allocate DMA channels when user passes\r
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
+ * copy). The same mapping is used to allocate the TCC when user passes\r
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
+ *\r
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
+ */\r
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0x00000000u) /* TBD */\r
+\r
+\r
+/* Variable which will be used internally for referring number of Event Queues*/\r
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {\r
+                                                        EDMA3_0_NUM_EVTQUE,\r
+                                                    };\r
+\r
+/* Variable which will be used internally for referring number of TCs.        */\r
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {\r
+                                                    EDMA3_0_NUM_TC,\r
+                                                };\r
+\r
+/**\r
+ * Variable which will be used internally for referring transfer completion\r
+ * interrupt.\r
+ */\r
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+{\r
+    {\r
+        0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,\r
+    },\r
+};\r
+\r
+/**\r
+ * Variable which will be used internally for referring channel controller's\r
+ * error interrupt.\r
+ */\r
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {\r
+                                                    EDMA3_0_CC_ERROR_INT,\r
+                                               };\r
+\r
+/**\r
+ * Variable which will be used internally for referring transfer controllers'\r
+ * error interrupts.\r
+ */\r
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] =\r
+{\r
+   {\r
+       EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,\r
+       EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,\r
+       EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,\r
+       EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,\r
+   }\r
+};\r
+\r
+/**\r
+ * Variables which will be used internally for referring the hardware interrupt\r
+ * for various EDMA3 interrupts.\r
+ */\r
+unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {\r
+                                                    EDMA3_0_HWI_INT_XFER_COMP\r
+                                                  };\r
+\r
+unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {\r
+                                                   EDMA3_0_HWI_INT_CC_ERR\r
+                                               };\r
+\r
+unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {\r
+                                                     {\r
+                                                        EDMA3_0_HWI_INT_TC0_ERR,\r
+                                                        EDMA3_0_HWI_INT_TC1_ERR,\r
+                                                        EDMA3_0_HWI_INT_TC2_ERR,\r
+                                                        EDMA3_0_HWI_INT_TC3_ERR\r
+                                                     }\r
+                                               };\r
+\r
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))\r
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))\r
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))\r
+/* Driver Object Initialization Configuration                                 */\r
+EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =\r
+{\r
+    {\r
+        /* EDMA3 INSTANCE# 0 */\r
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */\r
+        EDMA3_NUM_DMA_CHANNELS,\r
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */\r
+        EDMA3_NUM_QDMA_CHANNELS,\r
+        /** Total number of TCCs supported by the EDMA3 Controller            */\r
+        EDMA3_NUM_TCC,\r
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */\r
+        EDMA3_NUM_PARAMSET,\r
+        /** Total number of Event Queues in the EDMA3 Controller              */\r
+        EDMA3_0_NUM_EVTQUE,\r
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/\r
+        EDMA3_0_NUM_TC,\r
+        /** Number of Regions on this EDMA3 controller                        */\r
+        EDMA3_0_NUM_REGIONS,\r
+\r
+        /**\r
+         * \brief Channel mapping existence\r
+         * A value of 0 (No channel mapping) implies that there is fixed association\r
+         * for a channel number to a parameter entry number or, in other words,\r
+         * PaRAM entry n corresponds to channel n.\r
+         */\r
+        1u,\r
+\r
+        /** Existence of memory protection feature */\r
+        0u,\r
+\r
+        /** Global Register Region of CC Registers */\r
+        EDMA3_CC_BASE_ADDR,\r
+        /** Transfer Controller (TC) Registers */\r
+        {\r
+               EDMA3_TC0_BASE_ADDR,\r
+               EDMA3_TC1_BASE_ADDR,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL\r
+        },\r
+        /** Interrupt no. for Transfer Completion */\r
+        EDMA3_0_CC_XFER_COMPLETION_INT,\r
+        /** Interrupt no. for CC Error */\r
+        EDMA3_0_CC_ERROR_INT,\r
+        /** Interrupt no. for TCs Error */\r
+        {\r
+            EDMA3_0_TC0_ERROR_INT,\r
+            EDMA3_0_TC1_ERROR_INT,\r
+            EDMA3_0_TC2_ERROR_INT,\r
+            EDMA3_0_TC3_ERROR_INT,\r
+            EDMA3_0_TC4_ERROR_INT,\r
+            EDMA3_0_TC5_ERROR_INT,\r
+            EDMA3_0_TC6_ERROR_INT,\r
+            EDMA3_0_TC7_ERROR_INT\r
+        },\r
+\r
+        /**\r
+         * \brief EDMA3 TC priority setting\r
+         *\r
+         * User can program the priority of the Event Queues\r
+         * at a system-wide level.  This means that the user can set the\r
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
+         * relative to IO initiated by the other bus masters on the\r
+         * device (ARM, DSP, USB, etc)\r
+         */\r
+        {\r
+            0u,\r
+            1u,\r
+            2u,\r
+            3u,\r
+            0u,\r
+            0u,\r
+            0u,\r
+            0u\r
+        },\r
+        /**\r
+         * \brief To Configure the Threshold level of number of events\r
+         * that can be queued up in the Event queues. EDMA3CC error register\r
+         * (CCERR) will indicate whether or not at any instant of time the\r
+         * number of events queued up in any of the event queues exceeds\r
+         * or equals the threshold/watermark value that is set\r
+         * in the queue watermark threshold register (QWMTHRA).\r
+         */\r
+        {\r
+            16u,\r
+            16u,\r
+            16u,\r
+            16u,\r
+            0u,\r
+            0u,\r
+            0u,\r
+            0u\r
+        },\r
+\r
+        /**\r
+         * \brief To Configure the Default Burst Size (DBS) of TCs.\r
+         * An optimally-sized command is defined by the transfer controller\r
+         * default burst size (DBS). Different TCs can have different\r
+         * DBS values. It is defined in Bytes.\r
+         */\r
+            {\r
+            16u,\r
+            16u,\r
+            0u,\r
+            0u,\r
+            0u,\r
+            0u,\r
+            0u,\r
+            0u\r
+            },\r
+\r
+        /**\r
+         * \brief Mapping from each DMA channel to a Parameter RAM set,\r
+         * if it exists, otherwise of no use.\r
+         */\r
+            {\r
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
+            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, \r
+            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
+            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
+            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
+            },\r
+\r
+         /**\r
+          * \brief Mapping from each DMA channel to a TCC. This specific\r
+          * TCC code will be returned when the transfer is completed\r
+          * on the mapped channel.\r
+          */\r
+            {\r
+            0u, 1u, 2u, 3u,\r
+            4u, 5u, 6u, 7u,\r
+            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+            12u, 13u, 14u, 15u,\r
+            16u, 17u, 18u, 19u,\r
+            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+            24u, 25u, 26u, 27u,\r
+            28u, 29u, 30u, 31u,\r
+            32u, 33u, 34u, 35u,\r
+            36u, 37u, 38u, 39u,\r
+            40u, 41u, 42u, 43u,\r
+            44u, 45u, 46u, 47u,\r
+            48u, 49u, 50u, 51u,\r
+            52u, 53u, 54u, 55u,\r
+            56u, 57u, 58u, 59u,\r
+            60u, 61u, 62u, 63u\r
+            },\r
+\r
+        /**\r
+         * \brief Mapping of DMA channels to Hardware Events from\r
+         * various peripherals, which use EDMA for data transfer.\r
+         * All channels need not be mapped, some can be free also.\r
+         */\r
+            {\r
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,\r
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1\r
+            }\r
+        },\r
+\r
+};\r
+\r
+\r
+/* Driver Instance Initialization Configuration */\r
+EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+{\r
+    /* EDMA3 INSTANCE# 0 */\r
+               {\r
+                       /* Resources owned/reserved by region 0 (Associated to any MPU core)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+                       },\r
+\r
+                       /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+        },\r
+    },\r
+};\r
+\r
+/* Driver Instance Cross bar event to channel map Initialization Configuration */\r
+EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+{\r
+    /* EDMA3 INSTANCE# 0 */\r
+    {\r
+        /* Event to channel map for region 0 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 1 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, 26, 27, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 2 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 3 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 4 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 5 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 6 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 7 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+    }\r
+};\r
+\r
+/* End of File */\r
+\r
diff --git a/packages/ti/sdo/edma3/rm/src/configs/edma3_tda2xx_cfg.c b/packages/ti/sdo/edma3/rm/src/configs/edma3_tda2xx_cfg.c
new file mode 100644 (file)
index 0000000..e2d7cea
--- /dev/null
@@ -0,0 +1,755 @@
+/*\r
+ * edma3_tda2xx_cfg.c\r
+ *\r
+ * EDMA3 Driver Adaptation Configuration File (Soc Specific) for OMAPL138.\r
+ *\r
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ *\r
+ *  Redistribution and use in source and binary forms, with or without\r
+ *  modification, are permitted provided that the following conditions\r
+ *  are met:\r
+ *\r
+ *    Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ *\r
+ *    Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the\r
+ *    distribution.\r
+ *\r
+ *    Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
+ *\r
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#include <ti/sdo/edma3/rm/edma3_rm.h>\r
+\r
+#define NUM_SHADOW_REGIONS                      (8u)\r
+\r
+/* Number of EDMA3 controllers present in the system */\r
+#define NUM_EDMA3_INSTANCES         1u\r
+\r
+/** Number of PaRAM Sets available                                            */\r
+#define EDMA3_NUM_PARAMSET                              (512u)\r
+\r
+/** Number of TCCS available                                                  */\r
+#define EDMA3_NUM_TCC                                   (64u)\r
+\r
+/** Number of DMA Channels available                                          */\r
+#define EDMA3_NUM_DMA_CHANNELS                          (64u)\r
+\r
+/** Number of QDMA Channels available                                         */\r
+#define EDMA3_NUM_QDMA_CHANNELS                         (8u)\r
+\r
+/** Number of Event Queues available                                          */\r
+#define EDMA3_0_NUM_EVTQUE                              (4u)\r
+\r
+/** Number of Transfer Controllers available                                  */\r
+#define EDMA3_0_NUM_TC                                  (4u)\r
+\r
+/** Number of Regions                                                         */\r
+#define EDMA3_0_NUM_REGIONS                             (2u)\r
+\r
+/** Interrupt no. for Transfer Completion                                     */\r
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (34u)\r
+/** Interrupt no. for CC Error                                                */\r
+#define EDMA3_0_CC_ERROR_INT                            (35u)\r
+/** Interrupt no. for TCs Error                                               */\r
+#define EDMA3_0_TC0_ERROR_INT                           (36u)\r
+#define EDMA3_0_TC1_ERROR_INT                           (37u)\r
+#define EDMA3_0_TC2_ERROR_INT                           (0u)\r
+#define EDMA3_0_TC3_ERROR_INT                           (0u)\r
+#define EDMA3_0_TC4_ERROR_INT                           (0u)\r
+#define EDMA3_0_TC5_ERROR_INT                           (0u)\r
+#define EDMA3_0_TC6_ERROR_INT                           (0u)\r
+#define EDMA3_0_TC7_ERROR_INT                           (0u)\r
+\r
+/** XBAR interrupt source index numbers for EDMA interrupts */\r
+#define XBAR_EDMA_TPCC_IRQ_REGION0                      (361u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION1                      (362u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION2                      (363u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION3                      (364u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION4                      (365u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION5                      (366u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION6                      (367u)\r
+#define XBAR_EDMA_TPCC_IRQ_REGION7                      (368u)\r
+\r
+#define XBAR_EDMA_TPCC_IRQ_ERR                          (359u)\r
+#define XBAR_EDMA_TC0_IRQ_ERR                           (370u)\r
+#define XBAR_EDMA_TC1_IRQ_ERR                           (371u)\r
+\r
+/**\r
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from\r
+ * various peripherals, which use EDMA for data transfer.\r
+ * All channels need not be mapped, some can be free also.\r
+ * 1: Mapped\r
+ * 0: Not mapped\r
+ *\r
+ * This mapping will be used to allocate DMA channels when user passes\r
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
+ * copy). The same mapping is used to allocate the TCC when user passes\r
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
+ *\r
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
+ */\r
+                                                /* 31     0 */\r
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0_0        (0x00000000u)\r
+\r
+\r
+/**\r
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from\r
+ * various peripherals, which use EDMA for data transfer.\r
+ * All channels need not be mapped, some can be free also.\r
+ * 1: Mapped\r
+ * 0: Not mapped\r
+ *\r
+ * This mapping will be used to allocate DMA channels when user passes\r
+ * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory\r
+ * copy). The same mapping is used to allocate the TCC when user passes\r
+ * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy).\r
+ *\r
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.\r
+ */\r
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0_1        (0x00000000u)\r
+\r
+\r
+\r
+\r
+/**\r
+ * \brief Base address as seen from the different cores may be different\r
+ * And is defined based on the core\r
+ */\r
+#define EDMA3_CC_BASE_ADDR                          ((void *)(0x43300000))\r
+#define EDMA3_TC0_BASE_ADDR                         ((void *)(0x43400000))\r
+#define EDMA3_TC1_BASE_ADDR                         ((void *)(0x43500000))\r
+EDMA3_RM_GblConfigParams edma3GblCfgParams [EDMA3_MAX_EDMA3_INSTANCES] =\r
+{\r
+    /* EDMA3 INSTANCE# 0 */\r
+    {\r
+    /** Total number of DMA Channels supported by the EDMA3 Controller */\r
+    EDMA3_NUM_DMA_CHANNELS,\r
+    /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
+    EDMA3_NUM_QDMA_CHANNELS,\r
+    /** Total number of TCCs supported by the EDMA3 Controller */\r
+    EDMA3_NUM_TCC,\r
+    /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
+    EDMA3_NUM_PARAMSET,\r
+    /** Total number of Event Queues in the EDMA3 Controller */\r
+    EDMA3_0_NUM_EVTQUE,\r
+    /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
+    EDMA3_0_NUM_TC,\r
+    /** Number of Regions on this EDMA3 controller */\r
+    EDMA3_0_NUM_REGIONS,\r
+\r
+    /**\r
+     * \brief Channel mapping existence\r
+     * A value of 0 (No channel mapping) implies that there is fixed association\r
+     * for a channel number to a parameter entry number or, in other words,\r
+     * PaRAM entry n corresponds to channel n.\r
+     */\r
+    0u,\r
+\r
+    /** Existence of memory protection feature */\r
+    0u,\r
+\r
+        /** Global Register Region of CC Registers */\r
+        EDMA3_CC_BASE_ADDR,\r
+        /** Transfer Controller (TC) Registers */\r
+        {\r
+               EDMA3_TC0_BASE_ADDR,\r
+               EDMA3_TC1_BASE_ADDR,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL,\r
+            (void *)NULL\r
+        },\r
+    /** Interrupt no. for Transfer Completion */\r
+    EDMA3_0_CC_XFER_COMPLETION_INT,\r
+    /** Interrupt no. for CC Error */\r
+    EDMA3_0_CC_ERROR_INT,\r
+    /** Interrupt no. for TCs Error */\r
+        {\r
+        EDMA3_0_TC0_ERROR_INT,\r
+        EDMA3_0_TC1_ERROR_INT,\r
+        EDMA3_0_TC2_ERROR_INT,\r
+        EDMA3_0_TC3_ERROR_INT,\r
+        EDMA3_0_TC4_ERROR_INT,\r
+        EDMA3_0_TC5_ERROR_INT,\r
+        EDMA3_0_TC6_ERROR_INT,\r
+        EDMA3_0_TC7_ERROR_INT\r
+        },\r
+\r
+   /**\r
+     * \brief EDMA3 TC priority setting\r
+     *\r
+     * User can program the priority of the Event Queues\r
+     * at a system-wide level.  This means that the user can set the\r
+     * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
+     * relative to IO initiated by the other bus masters on the\r
+     * device (ARM, DSP, USB, etc)\r
+     */\r
+        {\r
+        0u,\r
+        1u,\r
+        2u,\r
+        3u,\r
+        0u,\r
+        0u,\r
+        0u,\r
+        0u\r
+        },\r
+    /**\r
+     * \brief To Configure the Threshold level of number of events\r
+     * that can be queued up in the Event queues. EDMA3CC error register\r
+     * (CCERR) will indicate whether or not at any instant of time the\r
+     * number of events queued up in any of the event queues exceeds\r
+     * or equals the threshold/watermark value that is set\r
+     * in the queue watermark threshold register (QWMTHRA).\r
+     */\r
+        {\r
+        16u,\r
+        16u,\r
+        16u,\r
+        16u,\r
+        0u,\r
+        0u,\r
+        0u,\r
+        0u\r
+        },\r
+\r
+    /**\r
+     * \brief To Configure the Default Burst Size (DBS) of TCs.\r
+     * An optimally-sized command is defined by the transfer controller\r
+     * default burst size (DBS). Different TCs can have different\r
+     * DBS values. It is defined in Bytes.\r
+     */\r
+        {\r
+        16u,\r
+        16u,\r
+        16u,\r
+        16u,\r
+        0u,\r
+        0u,\r
+        0u,\r
+        0u\r
+        },\r
+\r
+    /**\r
+     * \brief Mapping from each DMA channel to a Parameter RAM set,\r
+     * if it exists, otherwise of no use.\r
+     */\r
+        {\r
+        0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
+        8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
+        16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
+        24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
+            32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, \r
+            40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,\r
+            48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,\r
+            56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u\r
+        },\r
+\r
+     /**\r
+      * \brief Mapping from each DMA channel to a TCC. This specific\r
+      * TCC code will be returned when the transfer is completed\r
+      * on the mapped channel.\r
+      */\r
+        {\r
+        0u, 1u, 2u, 3u,\r
+        4u, 5u, 6u, 7u,\r
+        8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+        12u, 13u, 14u, 15u,\r
+        16u, 17u, 18u, 19u,\r
+        20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+        24u, 25u, 26u, 27u,\r
+        28u, 29u, 30u, 31u,\r
+            32u, 33u, 34u, 35u,\r
+            36u, 37u, 38u, 39u,\r
+            40u, 41u, 42u, 43u,\r
+            44u, 45u, 46u, 47u,\r
+            48u, 49u, 50u, 51u,\r
+            52u, 53u, 54u, 55u,\r
+            56u, 57u, 58u, 59u,\r
+            60u, 61u, 62u, 63u\r
+        },\r
+\r
+    /**\r
+     * \brief Mapping of DMA channels to Hardware Events from\r
+     * various peripherals, which use EDMA for data transfer.\r
+     * All channels need not be mapped, some can be free also.\r
+     */\r
+        {\r
+        DMA_CHANNEL_TO_EVENT_MAPPING_0_0,\r
+        DMA_CHANNEL_TO_EVENT_MAPPING_0_1\r
+        }\r
+    },\r
+};\r
+\r
+\r
+/* Default RM Instance Initialization Configuration */\r
+EDMA3_RM_InstanceInitConfig defInstInitConfig [EDMA3_MAX_EDMA3_INSTANCES][NUM_SHADOW_REGIONS] =\r
+{\r
+        /* EDMA3 INSTANCE# 0 */\r
+        {\r
+                       /* Resources owned/reserved by region 0 (Associated to any MPU core)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+                       },\r
+\r
+                       /* Resources owned/reserved by region 1 (Associated to any DSP core) */\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 2 (Associated to any IPU0 core)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 3 (Associated to any IPU1 core)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x000000FFu},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00u, 0x00u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 4 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 5 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 6 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+\r
+               /* Resources owned/reserved by region 7 (Not Associated to any core supported)*/\r
+                       {\r
+                               /* ownPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* ownDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* ownQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* ownTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdPaRAMSets */\r
+                               /* 31     0     63    32     95    64     127   96 */\r
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 159  128     191  160     223  192     255  224 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 287  256     319  288     351  320     383  352 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,\r
+                               /* 415  384     447  416     479  448     511  480 */\r
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdDmaChannels */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+\r
+                               /* resvdQdmaChannels */\r
+                               /* 31     0 */\r
+                               {0x00000000u},\r
+\r
+                               /* resvdTccs */\r
+                               /* 31     0     63    32 */\r
+                               {0x00000000u, 0x00000000u},\r
+                       },\r
+        },\r
+};\r
+\r
+/* Driver Instance Cross bar event to channel map Initialization Configuration */\r
+EDMA3_RM_GblXbarToChanConfigParams defXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =\r
+{\r
+    /* EDMA3 INSTANCE# 0 */\r
+    {\r
+        /* Event to channel map for region 0 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 1 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 2 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 3 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 4 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 5 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 6 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+        /* Event to channel map for region 7 */\r
+        {\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1, -1,\r
+            -1, -1, -1, -1, -1, -1, -1\r
+        },\r
+    }\r
+};\r
+\r
+/* End of File */\r
+\r
+\r
+\r