From: Sundaram Raju Date: Wed, 2 Feb 2011 08:45:17 +0000 (+0530) Subject: Added support for Cortex A8 on evmTI814x X-Git-Tag: DEV_EDMA3_LLD_02_11_00_01_RC04~14 X-Git-Url: https://git.ti.com/gitweb?p=keystone-rtos%2Fedma3_lld.git;a=commitdiff_plain;h=aaaebbf09e64f386fed9c739eeab0b455e8c0946 Added support for Cortex A8 on evmTI814x - Added configuration for Cortex A8 on both DRV and RM Sample libraries - Added example sample application evmTI814x_ARM Signed-off-by: Sundaram Raju --- diff --git a/examples/edma3_driver/evmTI814x_ARM/makefile b/examples/edma3_driver/evmTI814x_ARM/makefile new file mode 100755 index 0000000..b481701 --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/makefile @@ -0,0 +1,35 @@ +# Makefile for edma3 lld app + +APP_NAME = edma3_drv_arm_ti814x_sample + +SRCDIR = ../src +INCDIR = ../src + +# List all the external components/interfaces, whose interface header files +# need to be included for this component +INCLUDE_EXERNAL_INTERFACES = bios xdc edma3_lld + +# List all the components required by the application +COMP_LIST_a8host = edma3_lld_drv edma3_lld_rm + +# XDC CFG File +XDC_CFG_FILE_a8host = rtsc_config/edma3_drv_bios6_ti814x_arm_st_sample.cfg + +# Common source files and CFLAGS across all platforms and cores +SRCS_COMMON = common.c dma_misc_test.c dma_test.c qdma_test.c dma_chain_test.c \ + dma_ping_pong_test.c main.c dma_link_test.c dma_poll_test.c \ + qdma_link_test.c +CFLAGS_LOCAL_COMMON = + +# Core/SoC/platform specific source files and CFLAGS +# Example: +# SRCS_ = +# CFLAGS_LOCAL_ = + +# Include common make files +include $(ROOTDIR)/makerules/common.mk + +# OBJs and libraries are built by using rule defined in rules_.mk +# and need not be explicitly specified here + +# Nothing beyond this point diff --git a/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.ccsproject b/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.ccsproject new file mode 100755 index 0000000..35502dc --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.ccsproject @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.cdtbuild b/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.cdtbuild new file mode 100755 index 0000000..59e15ca --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.cdtbuild @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + + + diff --git a/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.cdtproject b/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.cdtproject new file mode 100755 index 0000000..5421014 --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.cdtproject @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.project b/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.project new file mode 100755 index 0000000..dee5692 --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.project @@ -0,0 +1,24 @@ + + + edma_drv_bios6_arm_ti814x_st_sample_configuration + + + ti.sdo.edma3.drv + ti.sdo.edma3.drv.sample + ti.sdo.edma3.rm + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + + org.eclipse.rtsc.xdctools.buildDefinitions.XDC.xdcNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + com.ti.ccstudio.managedbuild.core.ccsNature + + diff --git a/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.settings/org.eclipse.cdt.core.prefs new file mode 100755 index 0000000..d0bf1ae --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,3 @@ +#Thu Aug 13 11:05:45 IST 2009 +eclipse.preferences.version=1 +indexerId=org.eclipse.cdt.core.nullindexer diff --git a/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100755 index 0000000..e423b5e --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/rtsc_config/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,28 @@ +#Mon Jan 24 19:41:13 IST 2011 +com.ti.ccstudio.buildDefinitions.C6000.Default.1041023276/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.1041023276/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Default.1164666266/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.1164666266/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Default.1800299584/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.1800299584/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Default.1879506303/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.1879506303/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Default.31004543/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.31004543/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Default.359282260/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.359282260/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Default.497143829/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.497143829/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Default.507384710/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.507384710/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.TMS470.Default.1173147605/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.TMS470.Default.1173147605/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.TMS470.Default.1406052921/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.TMS470.Default.1406052921/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.TMS470.Default.1497482439/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.TMS470.Default.1497482439/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.TMS470.Default.2019945117/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.TMS470.Default.2019945117/internalBuilder/ignoreErr=true +eclipse.preferences.version=1 +environment/project=\r\n\r\n +environment/project/com.ti.ccstudio.buildDefinitions.TMS470.Default.1173147605=\r\n\r\n diff --git a/examples/edma3_driver/evmTI814x_ARM/rtsc_config/edma3_drv_bios6_ti814x_arm_st_sample.cfg b/examples/edma3_driver/evmTI814x_ARM/rtsc_config/edma3_drv_bios6_ti814x_arm_st_sample.cfg new file mode 100755 index 0000000..3e39f09 --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/rtsc_config/edma3_drv_bios6_ti814x_arm_st_sample.cfg @@ -0,0 +1,70 @@ +/*use modules*/ +var Task = xdc.useModule ("ti.sysbios.knl.Task"); +var BIOS = xdc.useModule ("ti.sysbios.BIOS"); +var Startup = xdc.useModule ("xdc.runtime.Startup"); +var System = xdc.useModule ("xdc.runtime.System"); +var Log = xdc.useModule ("xdc.runtime.Log"); +var Hwi = xdc.useModule('ti.sysbios.hal.Hwi'); +var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore'); +var Cache = xdc.useModule('ti.sysbios.hal.Cache'); +var Error = xdc.useModule('xdc.runtime.Error'); + + +/* USE EDMA3 Sample App */ +//xdc.loadPackage('ti.sdo.edma3.drv.sample'); + +/* MMU/Cache related configurations */ + +var Cache = xdc.useModule('ti.sysbios.family.arm.a8.Cache'); +var Mmu = xdc.useModule('ti.sysbios.family.arm.a8.Mmu'); + + +/* Enable the cache */ +Cache.enableCache = true; + +/* Enable the MMU (Required for L1 data caching) */ +Mmu.enableMMU = true; + +/* descriptor attribute structure */ +var attrs = +{ + type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor + bufferable : true, // bufferable + cacheable : true, // cacheable + imp : 1, // implementation defined + domain : 0, // domain between 0-15 + accPerm : 3, // read/write permission +}; + +/* configure the L3 - peripheral memory range */ +for (var i= 0x48000000; i < 0x48FFFFFF; i = i + 0x100000) +{ + attrs.bufferable = false; + attrs.cacheable = false; + Mmu.setFirstLevelDescMeta(i, i, attrs); +} + +/* configure the L4 - peripheral memory range */ +for (var i= 0x4A000000; i < 0x4AFFFFFF; i = i + 0x100000) +{ + attrs.bufferable = false; + attrs.cacheable = false; + Mmu.setFirstLevelDescMeta(i, i, attrs); +} + +/* configure the EDMA - TPTC memory range */ +for (var i= 0x49800000; i < 0x49BFFFFF; i = i + 0x100000) +{ + attrs.bufferable = false; + attrs.cacheable = false; + Mmu.setFirstLevelDescMeta(i, i, attrs); +} + +/* configure the EDMA - TPCC memory range */ +for (var i= 0x49000000; i < 0x490FFFFF; i = i + 0x100000) +{ + attrs.bufferable = false; + attrs.cacheable = false; + Mmu.setFirstLevelDescMeta(i, i, attrs); +} + diff --git a/examples/edma3_driver/evmTI814x_ARM/sample_app/.ccsproject b/examples/edma3_driver/evmTI814x_ARM/sample_app/.ccsproject new file mode 100755 index 0000000..35502dc --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/sample_app/.ccsproject @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/examples/edma3_driver/evmTI814x_ARM/sample_app/.cdtbuild b/examples/edma3_driver/evmTI814x_ARM/sample_app/.cdtbuild new file mode 100755 index 0000000..e6f3f71 --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/sample_app/.cdtbuild @@ -0,0 +1,130 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/edma3_driver/evmTI814x_ARM/sample_app/.cdtproject b/examples/edma3_driver/evmTI814x_ARM/sample_app/.cdtproject new file mode 100755 index 0000000..13bbd87 --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/sample_app/.cdtproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/examples/edma3_driver/evmTI814x_ARM/sample_app/.project b/examples/edma3_driver/evmTI814x_ARM/sample_app/.project new file mode 100755 index 0000000..d5d58b6 --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/sample_app/.project @@ -0,0 +1,73 @@ + + + edma_drv_bios6_arm_ti814x_st_sample + + + edma_drv_bios6_arm_ti814x_st_sample_configuration + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + com.ti.ccstudio.managedbuild.core.ccsNature + + + + dma_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_test.c + + + dma_poll_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_poll_test.c + + + main.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/main.c + + + dma_misc_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_misc_test.c + + + qdma_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_test.c + + + dma_link_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_link_test.c + + + dma_ping_pong_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_ping_pong_test.c + + + qdma_link_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/qdma_link_test.c + + + common.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/common.c + + + dma_chain_test.c + 1 + EDMA3LLD_BIOS6_INSTALLDIR/examples/edma3_driver/src/dma_chain_test.c + + + diff --git a/examples/edma3_driver/evmTI814x_ARM/sample_app/.settings/org.eclipse.cdt.core.prefs b/examples/edma3_driver/evmTI814x_ARM/sample_app/.settings/org.eclipse.cdt.core.prefs new file mode 100755 index 0000000..d0bf1ae --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/sample_app/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,3 @@ +#Thu Aug 13 11:05:45 IST 2009 +eclipse.preferences.version=1 +indexerId=org.eclipse.cdt.core.nullindexer diff --git a/examples/edma3_driver/evmTI814x_ARM/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/examples/edma3_driver/evmTI814x_ARM/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100755 index 0000000..0e9849f --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/sample_app/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,34 @@ +#Mon Jan 24 19:45:03 IST 2011 +com.ti.ccstudio.buildDefinitions.C6000.Default.1041023276/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.1041023276/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Default.1164666266/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.1164666266/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Default.1800299584/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.1800299584/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Default.1879506303/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.1879506303/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Default.31004543/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.31004543/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Default.359282260/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.359282260/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Default.497143829/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.497143829/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Default.507384710/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Default.507384710/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.TMS470.Debug.1514122377/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.TMS470.Debug.1514122377/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.TMS470.Debug.2132888941/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.TMS470.Debug.2132888941/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.TMS470.Debug.266155286/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.TMS470.Debug.266155286/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.TMS470.Debug.382821947/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.TMS470.Debug.382821947/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.TMS470.Release.1103754139/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.TMS470.Release.1103754139/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.TMS470.Release.2011776262/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.TMS470.Release.2011776262/internalBuilder/ignoreErr=true +eclipse.preferences.version=1 +environment/project=\r\n\r\n +environment/project/com.ti.ccstudio.buildDefinitions.TMS470.Debug.2132888941=\r\n\r\n +environment/project/com.ti.ccstudio.buildDefinitions.TMS470.Debug.266155286=\r\n\r\n +environment/project/com.ti.ccstudio.buildDefinitions.TMS470.Release.2011776262=\r\n\r\n diff --git a/examples/edma3_driver/evmTI814x_ARM/sample_app/linker.cmd b/examples/edma3_driver/evmTI814x_ARM/sample_app/linker.cmd new file mode 100755 index 0000000..000c07d --- /dev/null +++ b/examples/edma3_driver/evmTI814x_ARM/sample_app/linker.cmd @@ -0,0 +1,5 @@ +SECTIONS +{ + .my_sect_iram > DDR3_RAM + .my_sect_ddr > DDR3_RAM +} diff --git a/packages/config.bld b/packages/config.bld index c4add0d..80ba5fa 100755 --- a/packages/config.bld +++ b/packages/config.bld @@ -10,6 +10,7 @@ var C674 = xdc.useModule('ti.targets.C674'); var C66 = xdc.useModule('ti.targets.elf.C66'); var C66e = xdc.useModule('ti.targets.elf.C66_big_endian'); var Arm = xdc.useModule('ti.targets.arm.elf.Arm9'); +var cortexA8 = xdc.useModule('ti.targets.arm.elf.A8F'); /* compiler paths for the CCS4.0 */ var cgtools = java.lang.System.getenv("CGTOOLS"); @@ -22,6 +23,7 @@ C674.rootDir = cgtools; C66.rootDir = cgtools_elf; C66e.rootDir = cgtools_elf; Arm.rootDir = armcgtools; +cortexA8.rootDir = armcgtools; /**********************************c674******************************/ @@ -32,6 +34,7 @@ C674.ccOpts.suffix += " -mi10 -mo "; C66.ccOpts.suffix += " -mi10 -mo "; C66e.ccOpts.suffix += " -mi10 -mo -me "; Arm.ccOpts.suffix += " "; +cortexA8.ccOpts.suffix += ""; /* set default platform and list of all interested platforms */ @@ -63,6 +66,10 @@ Arm.platforms = [ "ti.platforms.evmOMAPL138", ]; +cortexA8.platforms = [ + "ti.platforms.evmDM8148", + ]; + /* select the default platform */ C64P.platform = C64P.platforms[0]; C64Pe.platform = C64Pe.platforms[0]; @@ -70,6 +77,7 @@ C674.platform = C674.platforms[0]; C66.platform = null; C66e.platform = null; Arm.platform = Arm.platforms[0]; +cortexA8.platform = cortexA8.platforms[0]; /* list interested targets in Build.targets array */ Build.targets = [ @@ -81,5 +89,6 @@ Build.targets = [ C66, C66e, Arm, + cortexA8, //Win32, ]; diff --git a/packages/ti/sdo/edma3/drv/sample/package.bld b/packages/ti/sdo/edma3/drv/sample/package.bld index 403181e..e27ed4f 100755 --- a/packages/ti/sdo/edma3/drv/sample/package.bld +++ b/packages/ti/sdo/edma3/drv/sample/package.bld @@ -62,6 +62,13 @@ var objListOMAPL138 = [ "src/sample_init.c", ]; +var objListTI814X = [ + "src/platforms/sample_ti814x_cfg.c", + "src/platforms/sample_ti814x_int_reg.c", + "src/sample_cs.c", + "src/sample_init.c", +]; + var objListOMAPL138ARM = [ "src/platforms/sample_omapl138_arm_cfg.c", "src/platforms/sample_omapl138_arm_int_reg.c", @@ -69,6 +76,13 @@ var objListOMAPL138ARM = [ "src/sample_arm_init.c", ]; +var objListTI814XARM = [ + "src/platforms/sample_ti814x_arm_cfg.c", + "src/platforms/sample_ti814x_arm_int_reg.c", + "src/sample_arm_cs.c", + "src/sample_arm_init.c", +]; + var objListSimTCI6498 = [ "src/platforms/sample_tci6498_cfg.c", "src/platforms/sample_tci6498_int_reg.c", @@ -104,13 +118,6 @@ var objListEVMTCI6486 = [ "src/sample_init.c", ]; -var objListTI814X = [ - "src/platforms/sample_ti814x_cfg.c", - "src/platforms/sample_ti814x_int_reg.c", - "src/sample_cs.c", - "src/sample_init.c", -]; - /* Platforms supported */ var plat_supported = [ { @@ -151,6 +158,9 @@ var plat_supported = [ }, { platform: 'ti.platforms.evmDM8148', targ : 'C674', objList: objListTI814X, dir : 'ti814x/' + }, + { + platform: 'ti.platforms.evmDM8148', targ : 'A8F', objList: objListTI814XARM, dir : 'ti814x/' } ]; @@ -168,6 +178,7 @@ var chipdefines = [ 'CHIP_TCI6486', 'CHIP_TCI6486', 'CHIP_TI814X', + 'CHIP_TI814X' ]; for each (var targ in Build.targets) @@ -230,6 +241,8 @@ Pkg.otherFiles=[ 'lib/omapl138/Release/ti.sdo.edma3.drv.sample.ae9', 'lib/ti814x/Debug/ti.sdo.edma3.drv.sample.a674', 'lib/ti814x/Release/ti.sdo.edma3.drv.sample.a674', + 'lib/ti814x/Debug/ti.sdo.edma3.drv.sample.aea8f', + 'lib/ti814x/Release/ti.sdo.edma3.drv.sample.aea8f', 'lib/tci6498/Debug/ti.sdo.edma3.drv.sample.a64P', 'lib/tci6498/Debug/ti.sdo.edma3.drv.sample.a64Pe', 'lib/tci6498/Release/ti.sdo.edma3.drv.sample.a64P', @@ -260,6 +273,8 @@ Pkg.otherFiles=[ 'src/platforms/sample_omapl138_arm_int_reg.c', 'src/platforms/sample_ti814x_cfg.c', 'src/platforms/sample_ti814x_int_reg.c', + 'src/platforms/sample_ti814x_arm_cfg.c', + 'src/platforms/sample_ti814x_arm_int_reg.c', 'src/platforms/sample_tci6498_cfg.c', 'src/platforms/sample_tci6498_int_reg.c', 'src/platforms/sample_ti816x_cfg.c', diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_cfg.c new file mode 100755 index 0000000..2f879d3 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_cfg.c @@ -0,0 +1,854 @@ +/* + * sample_ti814x_cfg.c + * + * SoC specific EDMA3 hardware related information like number of transfer + * controllers, various interrupt ids etc. It is used while interrupts + * enabling / disabling. It needs to be ported for different SoCs. + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include + +/* Number of EDMA3 controllers present in the system */ +#define NUM_EDMA3_INSTANCES 1u +const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES; + +/* Number of DSPs present in the system */ +#define NUM_DSPS 0u +const unsigned int numDsps = NUM_DSPS; + +/* Determine the processor id by reading DNUM register. */ +unsigned short determineProcId() +{ + return 0; +} + +unsigned short isGblConfigRequired(unsigned int dspNum) +{ + (void) dspNum; + return 0; +} + +/* Semaphore handles */ +EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL}; + +/** Number of PaRAM Sets available */ +#define EDMA3_NUM_PARAMSET (512u) + +/** Number of TCCS available */ +#define EDMA3_NUM_TCC (64u) + +/** Number of DMA Channels available */ +#define EDMA3_NUM_DMA_CHANNELS (64u) + +/** Number of QDMA Channels available */ +#define EDMA3_NUM_QDMA_CHANNELS (8u) + +/** Number of Event Queues available */ +#define EDMA3_0_NUM_EVTQUE (4u) + +/** Number of Transfer Controllers available */ +#define EDMA3_0_NUM_TC (4u) + +/** Number of Regions */ +#define EDMA3_0_NUM_REGIONS (4u) + + +/** Interrupt no. for Transfer Completion */ +#define EDMA3_0_CC_XFER_COMPLETION_INT (12u) +/** Interrupt no. for CC Error */ +#define EDMA3_0_CC_ERROR_INT (14u) +/** Interrupt no. for TCs Error */ +#define EDMA3_0_TC0_ERROR_INT (112u) +#define EDMA3_0_TC1_ERROR_INT (113u) +#define EDMA3_0_TC2_ERROR_INT (114u) +#define EDMA3_0_TC3_ERROR_INT (115u) +#define EDMA3_0_TC4_ERROR_INT (0u) +#define EDMA3_0_TC5_ERROR_INT (0u) +#define EDMA3_0_TC6_ERROR_INT (0u) +#define EDMA3_0_TC7_ERROR_INT (0u) + +/** + * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different + * ECM events (SoC specific). These ECM events come + * under ECM block XXX (handling those specific ECM events). Normally, block + * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events + * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX) + * is mapped to a specific HWI_INT YYY in the tcf file. + * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding + * to transfer completion interrupt. + * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding + * to CC error interrupts. + * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding + * to TC error interrupts. + */ +/* EDMA 0 */ + +#define EDMA3_0_HWI_INT_XFER_COMP (7u) +#define EDMA3_0_HWI_INT_CC_ERR (7u) +#define EDMA3_0_HWI_INT_TC0_ERR (10u) +#define EDMA3_0_HWI_INT_TC1_ERR (10u) +#define EDMA3_0_HWI_INT_TC2_ERR (10u) +#define EDMA3_0_HWI_INT_TC3_ERR (10u) + + +/** + * \brief Mapping of DMA channels 0-31 to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + * 1: Mapped + * 0: Not mapped + * + * This mapping will be used to allocate DMA channels when user passes + * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory + * copy). The same mapping is used to allocate the TCC when user passes + * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy). + * + * To allocate more DMA channels or TCCs, one has to modify the event mapping. + */ + /* 31 0 */ +#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFCFF3F00u) /* TBD */ + + +/** + * \brief Mapping of DMA channels 32-63 to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + * 1: Mapped + * 0: Not mapped + * + * This mapping will be used to allocate DMA channels when user passes + * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory + * copy). The same mapping is used to allocate the TCC when user passes + * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy). + * + * To allocate more DMA channels or TCCs, one has to modify the event mapping. + */ +/* DMA channels 32-63 DOES NOT exist in omapl138. */ +#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xFF003C00u) /* TBD */ + + +/* Variable which will be used internally for referring number of Event Queues*/ +unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = { + EDMA3_0_NUM_EVTQUE, + }; + +/* Variable which will be used internally for referring number of TCs. */ +unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = { + EDMA3_0_NUM_TC, + }; + +/** + * Variable which will be used internally for referring transfer completion + * interrupt. + */ +unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = +{ + { + EDMA3_0_CC_XFER_COMPLETION_INT, 0, 0u, 0u, 0u, 0u, 0u, 0u, + }, +}; + +/** + * Variable which will be used internally for referring channel controller's + * error interrupt. + */ +unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = { + EDMA3_0_CC_ERROR_INT, + }; + +/** + * Variable which will be used internally for referring transfer controllers' + * error interrupts. + */ +unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = +{ + { + EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT, + EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT, + EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT, + EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT, + } +}; + +/** + * Variables which will be used internally for referring the hardware interrupt + * for various EDMA3 interrupts. + */ +unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = { + EDMA3_0_HWI_INT_XFER_COMP + }; + +unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = { + EDMA3_0_HWI_INT_CC_ERR + }; + +unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = { + { + EDMA3_0_HWI_INT_TC0_ERR, + EDMA3_0_HWI_INT_TC1_ERR, + EDMA3_0_HWI_INT_TC2_ERR, + EDMA3_0_HWI_INT_TC3_ERR + } + }; + +/* Driver Object Initialization Configuration */ +EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = +{ + { + /* EDMA3 INSTANCE# 0 */ + /** Total number of DMA Channels supported by the EDMA3 Controller */ + EDMA3_NUM_DMA_CHANNELS, + /** Total number of QDMA Channels supported by the EDMA3 Controller */ + EDMA3_NUM_QDMA_CHANNELS, + /** Total number of TCCs supported by the EDMA3 Controller */ + EDMA3_NUM_TCC, + /** Total number of PaRAM Sets supported by the EDMA3 Controller */ + EDMA3_NUM_PARAMSET, + /** Total number of Event Queues in the EDMA3 Controller */ + EDMA3_0_NUM_EVTQUE, + /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/ + EDMA3_0_NUM_TC, + /** Number of Regions on this EDMA3 controller */ + EDMA3_0_NUM_REGIONS, + + /** + * \brief Channel mapping existence + * A value of 0 (No channel mapping) implies that there is fixed association + * for a channel number to a parameter entry number or, in other words, + * PaRAM entry n corresponds to channel n. + */ + 1u, + + /** Existence of memory protection feature */ + 0u, + + /** Global Register Region of CC Registers */ + (void *)0x49000000u, + /** Transfer Controller (TC) Registers */ + { + (void *)0x49800000u, + (void *)0x49900000u, + (void *)0x49A00000u, + (void *)0x49B00000u, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL + }, + /** Interrupt no. for Transfer Completion */ + EDMA3_0_CC_XFER_COMPLETION_INT, + /** Interrupt no. for CC Error */ + EDMA3_0_CC_ERROR_INT, + /** Interrupt no. for TCs Error */ + { + EDMA3_0_TC0_ERROR_INT, + EDMA3_0_TC1_ERROR_INT, + EDMA3_0_TC2_ERROR_INT, + EDMA3_0_TC3_ERROR_INT, + EDMA3_0_TC4_ERROR_INT, + EDMA3_0_TC5_ERROR_INT, + EDMA3_0_TC6_ERROR_INT, + EDMA3_0_TC7_ERROR_INT + }, + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + { + 0u, + 1u, + 2u, + 3u, + 0u, + 0u, + 0u, + 0u + }, + /** + * \brief To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + { + 16u, + 16u, + 16u, + 16u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief To Configure the Default Burst Size (DBS) of TCs. + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + { + 16u, + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief Mapping from each DMA channel to a Parameter RAM set, + * if it exists, otherwise of no use. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, + 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, + 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u, + 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u, + 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u + }, + + /** + * \brief Mapping from each DMA channel to a TCC. This specific + * TCC code will be returned when the transfer is completed + * on the mapped channel. + */ + { + 0u, 1u, 2u, 3u, + 4u, 5u, 6u, 7u, + 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, + 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 24u, 25u, 26u, 27u, + 28u, 29u, 30u, 31u, + 32u, 33u, 34u, 35u, + 36u, 37u, 38u, 39u, + 40u, 41u, 42u, 43u, + 44u, 45u, 46u, 47u, + 48u, 49u, 50u, 51u, + 52u, 53u, 54u, 55u, + 56u, 57u, 58u, 59u, + 60u, 61u, 62u, 63u + }, + + /** + * \brief Mapping of DMA channels to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + */ + { + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 + } + }, +}; + + +/* Driver Instance Initialization Configuration */ +EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = +{ + /* EDMA3 INSTANCE# 0 */ + { + /* Resources owned/reserved by region 0 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0xFFFFFFFFu}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0xFFFFFFFFu}, + + /* Resources reserved by Region 1 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 */ + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 */ + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, + }, + /* Resources owned/reserved by region 1 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* Resources reserved by Region 1 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 */ + {0xFF3FF3FFu, + /* 63..32 */ + 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 */ + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, + }, + /* Resources owned/reserved by region 2 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* Resources reserved by Region 1 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 */ + {0xFF3FF3FFu, + /* 63..32 */ + 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 */ + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, + }, + + /* Resources owned/reserved by region 3 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 4 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 5 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 6 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 7 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + } +}; + +/* Driver Instance Cross bar event to channel map Initialization Configuration */ +EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = +{ + /* EDMA3 INSTANCE# 0 */ + { + /* Event to channel map for region 0 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, 26, 27, -1, -1, -1, -1 + }, + /* Event to channel map for region 1 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 + }, + /* Event to channel map for region 2 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 + }, + /* Event to channel map for region 3 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 + }, + /* Event to channel map for region 4 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 + }, + /* Event to channel map for region 5 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 + }, + /* Event to channel map for region 6 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 + }, + /* Event to channel map for region 7 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 + }, + } +}; + +/* End of File */ + diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_int_reg.c new file mode 100755 index 0000000..4bb6a34 --- /dev/null +++ b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_arm_int_reg.c @@ -0,0 +1,357 @@ +/* + * sample_ti814x_int_reg.c + * + * Platform specific interrupt registration and un-registration routines. + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include +#include +#include +#include + +#include + +/** + * EDMA3 TC ISRs which need to be registered with the underlying OS by the user + * (Not all TC error ISRs need to be registered, register only for the + * available Transfer Controllers). + */ +void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) = + { + &lisrEdma3TC0ErrHandler0, + &lisrEdma3TC1ErrHandler0, + &lisrEdma3TC2ErrHandler0, + &lisrEdma3TC3ErrHandler0, + &lisrEdma3TC4ErrHandler0, + &lisrEdma3TC5ErrHandler0, + &lisrEdma3TC6ErrHandler0, + &lisrEdma3TC7ErrHandler0, + }; + +extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS]; +extern unsigned int ccErrorInt[]; +extern unsigned int tcErrorInt[][EDMA3_MAX_TC]; +extern unsigned int numEdma3Tc[]; + +/** + * Variables which will be used internally for referring the hardware interrupt + * for various EDMA3 interrupts. + */ +extern unsigned int hwIntXferComp[]; +extern unsigned int hwIntCcErr[]; +extern unsigned int hwIntTcErr[]; + +extern unsigned int dsp_num; +/* This variable has to be used as an extern */ +unsigned int gpp_num = 0; + +Hwi_Handle hwiCCXferCompInt; +Hwi_Handle hwiCCErrInt; +Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC]; + +/* External Instance Specific Configuration Structure */ +extern EDMA3_DRV_GblXbarToChanConfigParams + sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS]; + +typedef struct { + volatile Uint32 DSP_INTMUX[21]; + volatile Uint32 DUCATI_INTMUX[15]; + volatile Uint32 TPCC_EVTMUX[16]; + volatile Uint32 TIMER_EVTCAPT; + volatile Uint32 GPIO_MUX; +} CSL_IntmuxRegs; + +typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly; + + +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u) + + +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u) + + +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u) + + +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u) + + +#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u) +#define EDMA3_NUM_TCC (64u) + +/* + * Forward decleration + */ +EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum, + unsigned int *chanNum, + const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig); +EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum, + unsigned int chanNum); + +void Edma3MemProtectionHandler(unsigned int edma3InstanceId); + +/** To Register the ISRs with the underlying OS, if required. */ +void registerEdma3Interrupts (unsigned int edma3Id) + { + static UInt32 cookie = 0; + unsigned int numTc = 0; + Hwi_Params hwiParams; + Error_Block eb; + + /* Initialize the Error Block */ + Error_init(&eb); + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Initialize the HWI parameters with user specified values */ + Hwi_Params_init(&hwiParams); + + /* argument for the ISR */ + hwiParams.arg = edma3Id; + /* set the priority ID */ + hwiParams.priority = hwIntXferComp[edma3Id]; + + hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][gpp_num], + (&lisrEdma3ComplHandler0), + (const Hwi_Params *) (&hwiParams), + &eb); + if (TRUE == Error_check(&eb)) + { + System_printf("HWI Create Failed\n",Error_getCode(&eb)); + } + + /* Initialize the HWI parameters with user specified values */ + Hwi_Params_init(&hwiParams); + /* argument for the ISR */ + hwiParams.arg = edma3Id; + /* set the priority ID */ + hwiParams.priority = hwIntCcErr[edma3Id]; + + hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id], + (&lisrEdma3CCErrHandler0), + (const Hwi_Params *) (&hwiParams), + &eb); + + if (TRUE == Error_check(&eb)) + { + System_printf("HWI Create Failed\n",Error_getCode(&eb)); + } + + while (numTc < numEdma3Tc[edma3Id]) + { + /* Initialize the HWI parameters with user specified values */ + Hwi_Params_init(&hwiParams); + /* argument for the ISR */ + hwiParams.arg = edma3Id; + /* set the priority ID */ + hwiParams.priority = hwIntTcErr[edma3Id]; + + hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc], + (ptrEdma3TcIsrHandler[numTc]), + (const Hwi_Params *) (&hwiParams), + &eb); + if (TRUE == Error_check(&eb)) + { + System_printf("HWI Create Failed\n",Error_getCode(&eb)); + } + numTc++; + } + /** + * Enabling the HWI_ID. + * EDMA3 interrupts (transfer completion, CC error etc.) + * correspond to different ECM events (SoC specific). These ECM events come + * under ECM block XXX (handling those specific ECM events). Normally, block + * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events + * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX) + * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this + * mapped HWI_INT YYY, one should use the corresponding bitmask in the + * API C64_enableIER(), in which the YYY bit is SET. + */ + Hwi_enableInterrupt(ccErrorInt[edma3Id]); +#if 0 + Hwi_enableInterrupt(13); +#endif + Hwi_enableInterrupt(ccXferCompInt[edma3Id][gpp_num]); + numTc = 0; + while (numTc < numEdma3Tc[edma3Id]) + { + Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]); + numTc++; + } + + /* Restore interrupts */ + Hwi_restore(cookie); + } + +/** To Unregister the ISRs with the underlying OS, if previously registered. */ +void unregisterEdma3Interrupts (unsigned int edma3Id) + { + static UInt32 cookie = 0; + unsigned int numTc = 0; + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + Hwi_delete(&hwiCCXferCompInt); + Hwi_delete(&hwiCCErrInt); + while (numTc < numEdma3Tc[edma3Id]) + { + Hwi_delete(&hwiTCErrInt[numTc]); + numTc++; + } + /* Restore interrupts */ + Hwi_restore(cookie); + } + +/** + * \brief sampleMapXbarEvtToChan + * + * This function reads from the sample configuration structure which specifies + * cross bar events mapped to DMA channel. + * + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum, + unsigned int *chanNum, + const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig) + { + EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM; + unsigned int xbarEvtNum = 0; + int edmaChanNum = 0; + + if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) && + (chanNum != NULL) && + (edmaGblXbarConfig != NULL)) + { + xbarEvtNum = eventNum - EDMA3_NUM_TCC; + edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum]; + if (edmaChanNum != -1) + { + *chanNum = edmaChanNum; + edma3Result = EDMA3_DRV_SOK; + } + } + return (edma3Result); + } + + +/** + * \brief sampleConfigScr + * + * This function configures control config registers for the cross bar events + * mapped to the EDMA channel. + * + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum, + unsigned int chanNum) + { + EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK; + unsigned int scrChanOffset = 0; + unsigned int scrRegOffset = 0; + unsigned int xBarEvtNum = 0; + CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00); + + + if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) && + (chanNum < EDMA3_NUM_TCC)) + { + scrRegOffset = chanNum / 4; + scrChanOffset = chanNum - (scrRegOffset * 4); + xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1; + + switch(scrChanOffset) + { + case 0: + scrEvtMux->TPCC_EVTMUX[scrRegOffset] |= + (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK); + break; + case 1: + scrEvtMux->TPCC_EVTMUX[scrRegOffset] |= + ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & + (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK)); + break; + case 2: + scrEvtMux->TPCC_EVTMUX[scrRegOffset] |= + ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & + (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK)); + break; + case 3: + scrEvtMux->TPCC_EVTMUX[scrRegOffset] |= + ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & + (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK)); + break; + default: + edma3Result = EDMA3_DRV_E_INVALID_PARAM; + break; + } + } + else + { + edma3Result = EDMA3_DRV_E_INVALID_PARAM; + } + return edma3Result; + } + +EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, + unsigned int edma3Id) + { + EDMA3_DRV_Result retVal = EDMA3_DRV_SOK; + const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig = + &(sampleXbarChanInitConfig[edma3Id][dsp_num]); + if (hEdma != NULL) + { + retVal = EDMA3_DRV_initXbarEventMap(hEdma, + sampleXbarToChanConfig, + &sampleMapXbarEvtToChan, + &sampleConfigScr); + } + + return retVal; + } + +void Edma3MemProtectionHandler(unsigned int edma3InstanceId) + { + printf("memory Protection error"); + } diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c index e24ee12..c066492 100755 --- a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c +++ b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c @@ -139,7 +139,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL}; * To allocate more DMA channels or TCCs, one has to modify the event mapping. */ /* 31 0 */ -#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFFFFFFFFu) /* TBD */ +#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFCFF3F00u) /* TBD */ /** @@ -157,7 +157,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL}; * To allocate more DMA channels or TCCs, one has to modify the event mapping. */ /* DMA channels 32-63 DOES NOT exist in omapl138. */ -#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xFFFFFFFFu) /* TBD */ +#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xFF033C00u) /* TBD */ /* Variable which will be used internally for referring number of Event Queues*/ @@ -250,19 +250,19 @@ EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = * for a channel number to a parameter entry number or, in other words, * PaRAM entry n corresponds to channel n. */ - 0u, + 1u, /** Existence of memory protection feature */ 0u, /** Global Register Region of CC Registers */ - (void *)0x49000000u, + (void *)0x09000000u, /** Transfer Controller (TC) Registers */ { - (void *)0x49800000u, - (void *)0x49900000u, - (void *)0x49A00000u, - (void *)0x49B00000u, + (void *)0x09800000u, + (void *)0x09900000u, + (void *)0x09A00000u, + (void *)0x09B00000u, (void *)NULL, (void *)NULL, (void *)NULL, @@ -400,47 +400,52 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ - {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, /* ownDmaChannels */ /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, + {0xFFFFFFFFu, 0x00000000u}, /* ownQdmaChannels */ /* 31 0 */ - {0x00000000u}, + {0x000000FFu}, /* ownTccs */ /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, + {0xFFFFFFFFu, 0x00000000u}, + /* Resources reserved by Region 1 */ /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ - {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, /* resvdDmaChannels */ - /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, + /* 31 0 */ + {0xFF3FF3FFu, + /* 63..32 */ + 0x00000000u}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ - /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, + /* 31 0 */ + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, }, /* Resources owned/reserved by region 1 */ { @@ -456,7 +461,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX /* ownDmaChannels */ /* 31 0 63 32 */ - {0xFFFFFFFFu, 0x00000000u}, + {0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownQdmaChannels */ /* 31 0 */ @@ -464,12 +469,12 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX /* ownTccs */ /* 31 0 63 32 */ - {0xFFFFFFFFu, 0x00000000u}, + {0xFFFFFFFFu, 0xFFFFFFFFu}, /* Resources reserved by Region 1 */ /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ - {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ @@ -479,9 +484,9 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX /* resvdDmaChannels */ /* 31 0 */ - {0xFF3FF3FFu, + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, /* 63..32 */ - 0x00000000u}, + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, /* resvdQdmaChannels */ /* 31 0 */ @@ -794,7 +799,7 @@ EDMA3_DRV_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1 + -1, 26, 27, -1, -1, -1, -1 }, /* Event to channel map for region 2 */ { diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_int_reg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_int_reg.c index 6dc5cc1..78048fc 100755 --- a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_int_reg.c +++ b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_int_reg.c @@ -109,7 +109,7 @@ typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly; #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u) -#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (64u) +#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (94u) #define EDMA3_NUM_TCC (64u) /* @@ -245,7 +245,7 @@ EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum, unsigned int scrChanOffset = 0; unsigned int scrRegOffset = 0; unsigned int xBarEvtNum = 0; - CSL_IntmuxRegsOvly scrEvtMux = (unsigned int)(0x0); + CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x08140F00); if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) && @@ -263,18 +263,18 @@ EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum, break; case 1: scrEvtMux->TPCC_EVTMUX[scrRegOffset] |= - ((xBarEvtNum < CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & - (~(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK))); + ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & + (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK)); break; case 2: scrEvtMux->TPCC_EVTMUX[scrRegOffset] |= - ((xBarEvtNum < CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & - (~(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK))); + ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & + (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK)); break; case 3: scrEvtMux->TPCC_EVTMUX[scrRegOffset] |= - ((xBarEvtNum < CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & - (~(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK))); + ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & + (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK)); break; default: edma3Result = EDMA3_DRV_E_INVALID_PARAM; diff --git a/packages/ti/sdo/edma3/drv/sample/src/sample_arm_init.c b/packages/ti/sdo/edma3/drv/sample/src/sample_arm_init.c index 139db8d..8375cae 100644 --- a/packages/ti/sdo/edma3/drv/sample/src/sample_arm_init.c +++ b/packages/ti/sdo/edma3/drv/sample/src/sample_arm_init.c @@ -154,6 +154,14 @@ EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode) hEdma = EDMA3_DRV_open (edma3Id, (void *) &initCfg, &edma3Result); } +#if defined (CHIP_TI814X) + { + if(hEdma && (edma3Result == EDMA3_DRV_SOK)) + { + edma3Result = sampleInitXbarEvt(hEdma, edma3Id); + } + } +#endif if(hEdma && (edma3Result == EDMA3_DRV_SOK)) { /** diff --git a/packages/ti/sdo/edma3/rm/sample/package.bld b/packages/ti/sdo/edma3/rm/sample/package.bld index 2bd5a49..0eaf5a4 100755 --- a/packages/ti/sdo/edma3/rm/sample/package.bld +++ b/packages/ti/sdo/edma3/rm/sample/package.bld @@ -68,6 +68,13 @@ var objListTI814X = [ "src/sample_init.c", ]; +var objListTI814XARM = [ + "src/platforms/sample_ti814x_arm_cfg.c", + "src/platforms/sample_ti814x_arm_int_reg.c", + "src/sample_arm_cs.c", + "src/sample_arm_init.c", +]; + var objListOMAPL138ARM = [ "src/platforms/sample_omapl138_arm_cfg.c", "src/platforms/sample_omapl138_arm_int_reg.c", @@ -125,6 +132,7 @@ var chipdefines = [ 'CHIP_TCI6486', 'CHIP_TCI6486', 'CHIP_TI814X', + 'CHIP_TI814x' ]; /* Platforms supported */ @@ -167,6 +175,9 @@ var plat_supported = [ }, { platform: 'ti.platforms.evmDM8148',targ : 'C674', objList: objListTI814X, dir : 'ti814x/' + }, + { + platform: 'ti.platforms.evmDM8148',targ : 'A8F', objList: objListTI814XARM, dir : 'ti814x/' } ]; @@ -230,6 +241,8 @@ Pkg.otherFiles=[ 'lib/omapl138/Release/ti.sdo.edma3.rm.sample.ae9', 'lib/ti814x/Debug/ti.sdo.edma3.rm.sample.a674', 'lib/ti814x/Release/ti.sdo.edma3.rm.sample.a674', + 'lib/ti814x/Debug/ti.sdo.edma3.rm.sample.aea8f', + 'lib/ti814x/Release/ti.sdo.edma3.rm.sample.aea8f', 'lib/tci6498/Debug/ti.sdo.edma3.rm.sample.a64P', 'lib/tci6498/Debug/ti.sdo.edma3.rm.sample.a64Pe', 'lib/tci6498/Release/ti.sdo.edma3.rm.sample.a64P', @@ -261,6 +274,8 @@ Pkg.otherFiles=[ 'src/platforms/sample_omapl138_arm_int_reg.c', 'src/platforms/sample_ti814x_cfg.c', 'src/platforms/sample_ti814x_int_reg.c', + 'src/platforms/sample_ti814x_arm_cfg.c', + 'src/platforms/sample_ti814x_arm_int_reg.c', 'src/platforms/sample_tci6498_cfg.c', 'src/platforms/sample_tci6498_int_reg.c', 'src/platforms/sample_ti816x_cfg.c', diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_arm_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_arm_cfg.c new file mode 100755 index 0000000..5c054d4 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_arm_cfg.c @@ -0,0 +1,854 @@ +/* + * sample_omapl138_cfg.c + * + * Platform specific EDMA3 hardware related information like number of transfer + * controllers, various interrupt ids etc. It is used while interrupts + * enabling / disabling. It needs to be ported for different SoCs. + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include + +/* Number of EDMA3 controllers present in the system */ +#define NUM_EDMA3_INSTANCES 1u +const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES; + +/* Number of DSPs present in the system */ +#define NUM_DSPS 0u +const unsigned int numDsps = NUM_DSPS; + +/* Determine the processor id by reading DNUM register. */ +unsigned short determineProcId() +{ + return 0; +} + +unsigned short isGblConfigRequired(unsigned int dspNum) +{ + (void) dspNum; + return 0; +} + +/* Semaphore handles */ +EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL}; + +/** Number of PaRAM Sets available */ +#define EDMA3_NUM_PARAMSET (512u) + +/** Number of TCCS available */ +#define EDMA3_NUM_TCC (64u) + +/** Number of DMA Channels available */ +#define EDMA3_NUM_DMA_CHANNELS (64u) + +/** Number of QDMA Channels available */ +#define EDMA3_NUM_QDMA_CHANNELS (8u) + +/** Number of Event Queues available */ +#define EDMA3_0_NUM_EVTQUE (4u) + +/** Number of Transfer Controllers available */ +#define EDMA3_0_NUM_TC (4u) + +/** Number of Regions */ +#define EDMA3_0_NUM_REGIONS (4u) + + +/** Interrupt no. for Transfer Completion */ +#define EDMA3_0_CC_XFER_COMPLETION_INT (12u) +/** Interrupt no. for CC Error */ +#define EDMA3_0_CC_ERROR_INT (14u) +/** Interrupt no. for TCs Error */ +#define EDMA3_0_TC0_ERROR_INT (112u) +#define EDMA3_0_TC1_ERROR_INT (113u) +#define EDMA3_0_TC2_ERROR_INT (114u) +#define EDMA3_0_TC3_ERROR_INT (115u) +#define EDMA3_0_TC4_ERROR_INT (0u) +#define EDMA3_0_TC5_ERROR_INT (0u) +#define EDMA3_0_TC6_ERROR_INT (0u) +#define EDMA3_0_TC7_ERROR_INT (0u) + +/** + * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different + * ECM events (SoC specific). These ECM events come + * under ECM block XXX (handling those specific ECM events). Normally, block + * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events + * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX) + * is mapped to a specific HWI_INT YYY in the tcf file. + * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding + * to transfer completion interrupt. + * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding + * to CC error interrupts. + * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding + * to TC error interrupts. + */ +/* EDMA 0 */ + +#define EDMA3_0_HWI_INT_XFER_COMP (7u) +#define EDMA3_0_HWI_INT_CC_ERR (7u) +#define EDMA3_0_HWI_INT_TC0_ERR (10u) +#define EDMA3_0_HWI_INT_TC1_ERR (10u) +#define EDMA3_0_HWI_INT_TC2_ERR (10u) +#define EDMA3_0_HWI_INT_TC3_ERR (10u) + + +/** + * \brief Mapping of DMA channels 0-31 to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + * 1: Mapped + * 0: Not mapped + * + * This mapping will be used to allocate DMA channels when user passes + * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory + * copy). The same mapping is used to allocate the TCC when user passes + * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy). + * + * To allocate more DMA channels or TCCs, one has to modify the event mapping. + */ + /* 31 0 */ +#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFCFF3F00u) /* TBD */ + + +/** + * \brief Mapping of DMA channels 32-63 to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + * 1: Mapped + * 0: Not mapped + * + * This mapping will be used to allocate DMA channels when user passes + * EDMA3_RM_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory + * copy). The same mapping is used to allocate the TCC when user passes + * EDMA3_RM_TCC_ANY as tcc id (for eg to do memory-to-memory copy). + * + * To allocate more DMA channels or TCCs, one has to modify the event mapping. + */ +/* DMA channels 32-63 DOES NOT exist in omapl138. */ +#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xFF003C00u) /* TBD */ + + +/* Variable which will be used internally for referring number of Event Queues*/ +unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = { + EDMA3_0_NUM_EVTQUE, + }; + +/* Variable which will be used internally for referring number of TCs. */ +unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = { + EDMA3_0_NUM_TC, + }; + +/** + * Variable which will be used internally for referring transfer completion + * interrupt. + */ +unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = +{ + { + EDMA3_0_CC_XFER_COMPLETION_INT, 0, 0u, 0u, 0u, 0u, 0u, 0u, + }, +}; + +/** + * Variable which will be used internally for referring channel controller's + * error interrupt. + */ +unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = { + EDMA3_0_CC_ERROR_INT, + }; + +/** + * Variable which will be used internally for referring transfer controllers' + * error interrupts. + */ +unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = +{ + { + EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT, + EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT, + EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT, + EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT, + } +}; + +/** + * Variables which will be used internally for referring the hardware interrupt + * for various EDMA3 interrupts. + */ +unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = { + EDMA3_0_HWI_INT_XFER_COMP + }; + +unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = { + EDMA3_0_HWI_INT_CC_ERR + }; + +unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = { + { + EDMA3_0_HWI_INT_TC0_ERR, + EDMA3_0_HWI_INT_TC1_ERR, + EDMA3_0_HWI_INT_TC2_ERR, + EDMA3_0_HWI_INT_TC3_ERR + } + }; + +/* Driver Object Initialization Configuration */ +EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = +{ + { + /* EDMA3 INSTANCE# 0 */ + /** Total number of DMA Channels supported by the EDMA3 Controller */ + EDMA3_NUM_DMA_CHANNELS, + /** Total number of QDMA Channels supported by the EDMA3 Controller */ + EDMA3_NUM_QDMA_CHANNELS, + /** Total number of TCCs supported by the EDMA3 Controller */ + EDMA3_NUM_TCC, + /** Total number of PaRAM Sets supported by the EDMA3 Controller */ + EDMA3_NUM_PARAMSET, + /** Total number of Event Queues in the EDMA3 Controller */ + EDMA3_0_NUM_EVTQUE, + /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/ + EDMA3_0_NUM_TC, + /** Number of Regions on this EDMA3 controller */ + EDMA3_0_NUM_REGIONS, + + /** + * \brief Channel mapping existence + * A value of 0 (No channel mapping) implies that there is fixed association + * for a channel number to a parameter entry number or, in other words, + * PaRAM entry n corresponds to channel n. + */ + 1u, + + /** Existence of memory protection feature */ + 0u, + + /** Global Register Region of CC Registers */ + (void *)0x49000000u, + /** Transfer Controller (TC) Registers */ + { + (void *)0x49800000u, + (void *)0x49900000u, + (void *)0x49A00000u, + (void *)0x49B00000u, + (void *)NULL, + (void *)NULL, + (void *)NULL, + (void *)NULL + }, + /** Interrupt no. for Transfer Completion */ + EDMA3_0_CC_XFER_COMPLETION_INT, + /** Interrupt no. for CC Error */ + EDMA3_0_CC_ERROR_INT, + /** Interrupt no. for TCs Error */ + { + EDMA3_0_TC0_ERROR_INT, + EDMA3_0_TC1_ERROR_INT, + EDMA3_0_TC2_ERROR_INT, + EDMA3_0_TC3_ERROR_INT, + EDMA3_0_TC4_ERROR_INT, + EDMA3_0_TC5_ERROR_INT, + EDMA3_0_TC6_ERROR_INT, + EDMA3_0_TC7_ERROR_INT + }, + + /** + * \brief EDMA3 TC priority setting + * + * User can program the priority of the Event Queues + * at a system-wide level. This means that the user can set the + * priority of an IO initiated by either of the TCs (Transfer Controllers) + * relative to IO initiated by the other bus masters on the + * device (ARM, DSP, USB, etc) + */ + { + 0u, + 1u, + 2u, + 3u, + 0u, + 0u, + 0u, + 0u + }, + /** + * \brief To Configure the Threshold level of number of events + * that can be queued up in the Event queues. EDMA3CC error register + * (CCERR) will indicate whether or not at any instant of time the + * number of events queued up in any of the event queues exceeds + * or equals the threshold/watermark value that is set + * in the queue watermark threshold register (QWMTHRA). + */ + { + 16u, + 16u, + 16u, + 16u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief To Configure the Default Burst Size (DBS) of TCs. + * An optimally-sized command is defined by the transfer controller + * default burst size (DBS). Different TCs can have different + * DBS values. It is defined in Bytes. + */ + { + 16u, + 16u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u + }, + + /** + * \brief Mapping from each DMA channel to a Parameter RAM set, + * if it exists, otherwise of no use. + */ + { + 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, + 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, + 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u, + 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u, + 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u + }, + + /** + * \brief Mapping from each DMA channel to a TCC. This specific + * TCC code will be returned when the transfer is completed + * on the mapped channel. + */ + { + 0u, 1u, 2u, 3u, + 4u, 5u, 6u, 7u, + 8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 12u, 13u, 14u, 15u, + 16u, 17u, 18u, 19u, + 20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 24u, 25u, 26u, 27u, + 28u, 29u, 30u, 31u, + 32u, 33u, 34u, 35u, + 36u, 37u, 38u, 39u, + 40u, 41u, 42u, 43u, + 44u, 45u, 46u, 47u, + 48u, 49u, 50u, 51u, + 52u, 53u, 54u, 55u, + 56u, 57u, 58u, 59u, + 60u, 61u, 62u, 63u + }, + + /** + * \brief Mapping of DMA channels to Hardware Events from + * various peripherals, which use EDMA for data transfer. + * All channels need not be mapped, some can be free also. + */ + { + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 + } + }, +}; + + +/* Driver Instance Initialization Configuration */ +EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = +{ + /* EDMA3 INSTANCE# 0 */ + { + /* Resources owned/reserved by region 0 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0xFFFFFFFFu}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0xFFFFFFFFu}, + + /* Resources reserved by Region 1 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 */ + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 */ + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, + }, + /* Resources owned/reserved by region 1 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* Resources reserved by Region 1 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 */ + {0xFF3FF3FFu, + /* 63..32 */ + 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 */ + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, + }, + /* Resources owned/reserved by region 2 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x000000FFu}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0xFFFFFFFFu, 0x00000000u}, + + /* Resources reserved by Region 1 */ + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, + + /* resvdDmaChannels */ + /* 31 0 */ + {0xFF3FF3FFu, + /* 63..32 */ + 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 */ + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, + }, + + /* Resources owned/reserved by region 3 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 4 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 5 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 6 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + + /* Resources owned/reserved by region 7 */ + { + /* ownPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* ownDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* ownQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* ownTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdPaRAMSets */ + /* 31 0 63 32 95 64 127 96 */ + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 159 128 191 160 223 192 255 224 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + + /* resvdDmaChannels */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + + /* resvdQdmaChannels */ + /* 31 0 */ + {0x00000000u}, + + /* resvdTccs */ + /* 31 0 63 32 */ + {0x00000000u, 0x00000000u}, + }, + }, +}; + +/* Driver Instance Cross bar event to channel map Initialization Configuration */ +EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = +{ + /* EDMA3 INSTANCE# 0 */ + { + /* Event to channel map for region 0 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, 26, 27, -1, -1, -1, -1 + }, + /* Event to channel map for region 1 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 + }, + /* Event to channel map for region 2 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 + }, + /* Event to channel map for region 3 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 + }, + /* Event to channel map for region 4 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 + }, + /* Event to channel map for region 5 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 + }, + /* Event to channel map for region 6 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 + }, + /* Event to channel map for region 7 */ + { + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1 + }, + } +}; + +/* End of File */ + diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_arm_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_arm_int_reg.c new file mode 100755 index 0000000..4bb6a34 --- /dev/null +++ b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_arm_int_reg.c @@ -0,0 +1,357 @@ +/* + * sample_ti814x_int_reg.c + * + * Platform specific interrupt registration and un-registration routines. + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +*/ + +#include +#include +#include +#include + +#include + +/** + * EDMA3 TC ISRs which need to be registered with the underlying OS by the user + * (Not all TC error ISRs need to be registered, register only for the + * available Transfer Controllers). + */ +void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) = + { + &lisrEdma3TC0ErrHandler0, + &lisrEdma3TC1ErrHandler0, + &lisrEdma3TC2ErrHandler0, + &lisrEdma3TC3ErrHandler0, + &lisrEdma3TC4ErrHandler0, + &lisrEdma3TC5ErrHandler0, + &lisrEdma3TC6ErrHandler0, + &lisrEdma3TC7ErrHandler0, + }; + +extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS]; +extern unsigned int ccErrorInt[]; +extern unsigned int tcErrorInt[][EDMA3_MAX_TC]; +extern unsigned int numEdma3Tc[]; + +/** + * Variables which will be used internally for referring the hardware interrupt + * for various EDMA3 interrupts. + */ +extern unsigned int hwIntXferComp[]; +extern unsigned int hwIntCcErr[]; +extern unsigned int hwIntTcErr[]; + +extern unsigned int dsp_num; +/* This variable has to be used as an extern */ +unsigned int gpp_num = 0; + +Hwi_Handle hwiCCXferCompInt; +Hwi_Handle hwiCCErrInt; +Hwi_Handle hwiTCErrInt[EDMA3_MAX_TC]; + +/* External Instance Specific Configuration Structure */ +extern EDMA3_DRV_GblXbarToChanConfigParams + sampleXbarChanInitConfig[][EDMA3_MAX_REGIONS]; + +typedef struct { + volatile Uint32 DSP_INTMUX[21]; + volatile Uint32 DUCATI_INTMUX[15]; + volatile Uint32 TPCC_EVTMUX[16]; + volatile Uint32 TIMER_EVTCAPT; + volatile Uint32 GPIO_MUX; +} CSL_IntmuxRegs; + +typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly; + + +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK (0x3F000000u) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT (0x00000018u) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_RESETVAL (0x00000000u) + + +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK (0x003F0000u) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT (0x00000010u) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_RESETVAL (0x00000000u) + + +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK (0x00003F00u) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT (0x00000008u) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_RESETVAL (0x00000000u) + + +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK (0x0000003Fu) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_SHIFT (0x00000000u) +#define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u) + + +#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (95u) +#define EDMA3_NUM_TCC (64u) + +/* + * Forward decleration + */ +EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum, + unsigned int *chanNum, + const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig); +EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum, + unsigned int chanNum); + +void Edma3MemProtectionHandler(unsigned int edma3InstanceId); + +/** To Register the ISRs with the underlying OS, if required. */ +void registerEdma3Interrupts (unsigned int edma3Id) + { + static UInt32 cookie = 0; + unsigned int numTc = 0; + Hwi_Params hwiParams; + Error_Block eb; + + /* Initialize the Error Block */ + Error_init(&eb); + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + /* Initialize the HWI parameters with user specified values */ + Hwi_Params_init(&hwiParams); + + /* argument for the ISR */ + hwiParams.arg = edma3Id; + /* set the priority ID */ + hwiParams.priority = hwIntXferComp[edma3Id]; + + hwiCCXferCompInt = Hwi_create( ccXferCompInt[edma3Id][gpp_num], + (&lisrEdma3ComplHandler0), + (const Hwi_Params *) (&hwiParams), + &eb); + if (TRUE == Error_check(&eb)) + { + System_printf("HWI Create Failed\n",Error_getCode(&eb)); + } + + /* Initialize the HWI parameters with user specified values */ + Hwi_Params_init(&hwiParams); + /* argument for the ISR */ + hwiParams.arg = edma3Id; + /* set the priority ID */ + hwiParams.priority = hwIntCcErr[edma3Id]; + + hwiCCErrInt = Hwi_create( ccErrorInt[edma3Id], + (&lisrEdma3CCErrHandler0), + (const Hwi_Params *) (&hwiParams), + &eb); + + if (TRUE == Error_check(&eb)) + { + System_printf("HWI Create Failed\n",Error_getCode(&eb)); + } + + while (numTc < numEdma3Tc[edma3Id]) + { + /* Initialize the HWI parameters with user specified values */ + Hwi_Params_init(&hwiParams); + /* argument for the ISR */ + hwiParams.arg = edma3Id; + /* set the priority ID */ + hwiParams.priority = hwIntTcErr[edma3Id]; + + hwiTCErrInt[numTc] = Hwi_create( tcErrorInt[edma3Id][numTc], + (ptrEdma3TcIsrHandler[numTc]), + (const Hwi_Params *) (&hwiParams), + &eb); + if (TRUE == Error_check(&eb)) + { + System_printf("HWI Create Failed\n",Error_getCode(&eb)); + } + numTc++; + } + /** + * Enabling the HWI_ID. + * EDMA3 interrupts (transfer completion, CC error etc.) + * correspond to different ECM events (SoC specific). These ECM events come + * under ECM block XXX (handling those specific ECM events). Normally, block + * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events + * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX) + * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this + * mapped HWI_INT YYY, one should use the corresponding bitmask in the + * API C64_enableIER(), in which the YYY bit is SET. + */ + Hwi_enableInterrupt(ccErrorInt[edma3Id]); +#if 0 + Hwi_enableInterrupt(13); +#endif + Hwi_enableInterrupt(ccXferCompInt[edma3Id][gpp_num]); + numTc = 0; + while (numTc < numEdma3Tc[edma3Id]) + { + Hwi_enableInterrupt(tcErrorInt[edma3Id][numTc]); + numTc++; + } + + /* Restore interrupts */ + Hwi_restore(cookie); + } + +/** To Unregister the ISRs with the underlying OS, if previously registered. */ +void unregisterEdma3Interrupts (unsigned int edma3Id) + { + static UInt32 cookie = 0; + unsigned int numTc = 0; + + /* Disabling the global interrupts */ + cookie = Hwi_disable(); + + Hwi_delete(&hwiCCXferCompInt); + Hwi_delete(&hwiCCErrInt); + while (numTc < numEdma3Tc[edma3Id]) + { + Hwi_delete(&hwiTCErrInt[numTc]); + numTc++; + } + /* Restore interrupts */ + Hwi_restore(cookie); + } + +/** + * \brief sampleMapXbarEvtToChan + * + * This function reads from the sample configuration structure which specifies + * cross bar events mapped to DMA channel. + * + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Result sampleMapXbarEvtToChan (unsigned int eventNum, + unsigned int *chanNum, + const EDMA3_DRV_GblXbarToChanConfigParams * edmaGblXbarConfig) + { + EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM; + unsigned int xbarEvtNum = 0; + int edmaChanNum = 0; + + if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) && + (chanNum != NULL) && + (edmaGblXbarConfig != NULL)) + { + xbarEvtNum = eventNum - EDMA3_NUM_TCC; + edmaChanNum = edmaGblXbarConfig->dmaMapXbarToChan[xbarEvtNum]; + if (edmaChanNum != -1) + { + *chanNum = edmaChanNum; + edma3Result = EDMA3_DRV_SOK; + } + } + return (edma3Result); + } + + +/** + * \brief sampleConfigScr + * + * This function configures control config registers for the cross bar events + * mapped to the EDMA channel. + * + * \return EDMA3_DRV_SOK if success, else error code + */ +EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum, + unsigned int chanNum) + { + EDMA3_DRV_Result edma3Result = EDMA3_DRV_SOK; + unsigned int scrChanOffset = 0; + unsigned int scrRegOffset = 0; + unsigned int xBarEvtNum = 0; + CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x48140F00); + + + if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) && + (chanNum < EDMA3_NUM_TCC)) + { + scrRegOffset = chanNum / 4; + scrChanOffset = chanNum - (scrRegOffset * 4); + xBarEvtNum = (eventNum - EDMA3_NUM_TCC) + 1; + + switch(scrChanOffset) + { + case 0: + scrEvtMux->TPCC_EVTMUX[scrRegOffset] |= + (xBarEvtNum & CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_MASK); + break; + case 1: + scrEvtMux->TPCC_EVTMUX[scrRegOffset] |= + ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & + (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK)); + break; + case 2: + scrEvtMux->TPCC_EVTMUX[scrRegOffset] |= + ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & + (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK)); + break; + case 3: + scrEvtMux->TPCC_EVTMUX[scrRegOffset] |= + ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & + (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK)); + break; + default: + edma3Result = EDMA3_DRV_E_INVALID_PARAM; + break; + } + } + else + { + edma3Result = EDMA3_DRV_E_INVALID_PARAM; + } + return edma3Result; + } + +EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, + unsigned int edma3Id) + { + EDMA3_DRV_Result retVal = EDMA3_DRV_SOK; + const EDMA3_DRV_GblXbarToChanConfigParams *sampleXbarToChanConfig = + &(sampleXbarChanInitConfig[edma3Id][dsp_num]); + if (hEdma != NULL) + { + retVal = EDMA3_DRV_initXbarEventMap(hEdma, + sampleXbarToChanConfig, + &sampleMapXbarEvtToChan, + &sampleConfigScr); + } + + return retVal; + } + +void Edma3MemProtectionHandler(unsigned int edma3InstanceId) + { + printf("memory Protection error"); + } diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_cfg.c index 86dec63..914affd 100755 --- a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_cfg.c +++ b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_cfg.c @@ -139,7 +139,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL}; * To allocate more DMA channels or TCCs, one has to modify the event mapping. */ /* 31 0 */ -#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFFFFFFFFu) /* TBD */ +#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0 (0xFCFF3F00u) /* TBD */ /** @@ -157,7 +157,7 @@ EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL}; * To allocate more DMA channels or TCCs, one has to modify the event mapping. */ /* DMA channels 32-63 DOES NOT exist in omapl138. */ -#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xFFFFFFFFu) /* TBD */ +#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1 (0xFF033C00u) /* TBD */ /* Variable which will be used internally for referring number of Event Queues*/ @@ -250,19 +250,19 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = * for a channel number to a parameter entry number or, in other words, * PaRAM entry n corresponds to channel n. */ - 0u, + 1u, /** Existence of memory protection feature */ 0u, /** Global Register Region of CC Registers */ - (void *)0x49000000u, + (void *)0x09000000u, /** Transfer Controller (TC) Registers */ { - (void *)0x49800000u, - (void *)0x49900000u, - (void *)0x49A00000u, - (void *)0x49B00000u, + (void *)0x09800000u, + (void *)0x09900000u, + (void *)0x09A00000u, + (void *)0x09B00000u, (void *)NULL, (void *)NULL, (void *)NULL, @@ -401,47 +401,52 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ - {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, + {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, /* ownDmaChannels */ /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, + {0xFFFFFFFFu, 0x00000000u}, /* ownQdmaChannels */ /* 31 0 */ - {0x00000000u}, + {0x000000FFu}, /* ownTccs */ /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, + {0xFFFFFFFFu, 0x00000000u}, + /* Resources reserved by Region 1 */ /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ - {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, /* resvdDmaChannels */ - /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, + /* 31 0 */ + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, /* resvdQdmaChannels */ /* 31 0 */ {0x00000000u}, /* resvdTccs */ - /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, + /* 31 0 */ + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, + /* 63..32 */ + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, }, /* Resources owned/reserved by region 1 */ { @@ -457,7 +462,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_ /* ownDmaChannels */ /* 31 0 63 32 */ - {0xFFFFFFFFu, 0x00000000u}, + {0xFFFFFFFFu, 0xFFFFFFFFu}, /* ownQdmaChannels */ /* 31 0 */ @@ -465,12 +470,12 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_ /* ownTccs */ /* 31 0 63 32 */ - {0xFFFFFFFFu, 0x00000000u}, + {0xFFFFFFFFu, 0xFFFFFFFFu}, /* Resources reserved by Region 1 */ /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ - {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, + {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ @@ -480,9 +485,9 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_ /* resvdDmaChannels */ /* 31 0 */ - {0xFF3FF3FFu, + {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0, /* 63..32 */ - 0x00000000u}, + EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1}, /* resvdQdmaChannels */ /* 31 0 */ @@ -795,7 +800,7 @@ EDMA3_RM_GblXbarToChanConfigParams sampleXbarChanInitConfig[NUM_EDMA3_INSTANCES] -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1 + -1, 26, 27, -1, -1, -1, -1 }, /* Event to channel map for region 2 */ { diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_int_reg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_int_reg.c index d39f8b1..7f7a5be 100755 --- a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_int_reg.c +++ b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_ti814x_int_reg.c @@ -1,5 +1,5 @@ /* - * sample_omapl138_int_reg.c + * sample_ti814x_int_reg.c * * Platform specific interrupt registration and un-registration routines. * @@ -109,7 +109,7 @@ typedef volatile CSL_IntmuxRegs *CSL_IntmuxRegsOvly; #define CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_0_RESETVAL (0x00000000u) -#define EDMA3_MAX_CROSS_BAR_EVENTS_DM8148 (64u) +#define EDMA3_MAX_CROSS_BAR_EVENTS_TI814X (64u) #define EDMA3_NUM_TCC (64u) /* @@ -214,7 +214,7 @@ EDMA3_RM_Result sampleMapXbarEvtToChan (unsigned int eventNum, unsigned int xbarEvtNum = 0; int edmaChanNum = 0; - if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DM8148) && + if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) && (chanNum != NULL) && (edmaGblXbarConfig != NULL)) { @@ -238,17 +238,17 @@ EDMA3_RM_Result sampleMapXbarEvtToChan (unsigned int eventNum, * * \return EDMA3_DRV_SOK if success, else error code */ -EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum, +EDMA3_RM_Result sampleConfigScr (unsigned int eventNum, unsigned int chanNum) { EDMA3_RM_Result edma3Result = EDMA3_RM_SOK; unsigned int scrChanOffset = 0; unsigned int scrRegOffset = 0; unsigned int xBarEvtNum = 0; - CSL_IntmuxRegsOvly scrEvtMux = (unsigned int)(0x0); + CSL_IntmuxRegsOvly scrEvtMux = (CSL_IntmuxRegsOvly)(0x08140F00); - if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_DM8148) && + if ((eventNum < EDMA3_MAX_CROSS_BAR_EVENTS_TI814X) && (chanNum < EDMA3_NUM_TCC)) { scrRegOffset = chanNum / 4; @@ -263,18 +263,18 @@ EDMA3_DRV_Result sampleConfigScr (unsigned int eventNum, break; case 1: scrEvtMux->TPCC_EVTMUX[scrRegOffset] |= - ((xBarEvtNum < CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & - (~(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK))); + ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_SHIFT) & + (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_1_MASK)); break; case 2: scrEvtMux->TPCC_EVTMUX[scrRegOffset] |= - ((xBarEvtNum < CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & - (~(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK))); + ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_SHIFT) & + (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_2_MASK)); break; case 3: scrEvtMux->TPCC_EVTMUX[scrRegOffset] |= - ((xBarEvtNum < CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & - (~(CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK))); + ((xBarEvtNum << CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_SHIFT) & + (CSL_INTMUX_TPCC_EVTMUX_TPCCEVT_MUX_3_MASK)); break; default: edma3Result = EDMA3_RM_E_INVALID_PARAM; diff --git a/packages/ti/sdo/edma3/rm/sample/src/sample_arm_init.c b/packages/ti/sdo/edma3/rm/sample/src/sample_arm_init.c index e0bd004..5b7f09e 100644 --- a/packages/ti/sdo/edma3/rm/sample/src/sample_arm_init.c +++ b/packages/ti/sdo/edma3/rm/sample/src/sample_arm_init.c @@ -153,6 +153,14 @@ EDMA3_RM_Handle edma3init (unsigned int edma3Id, EDMA3_RM_Result *errorCode) &edma3Result); } +#if defined (CHIP_TI814X1) + { + if(hEdmaResMgr && (edma3Result == EDMA3_RM_SOK)) + { + edma3Result = sampleInitXbarEvt(hEdmaResMgr, edma3Id); + } + } +#endif if(hEdmaResMgr && (edma3Result == EDMA3_DRV_SOK)) { /**