From cddbfad11539aab56da4f43ce63911972b7b7ffa Mon Sep 17 00:00:00 2001 From: Sinthu Raja M Date: Tue, 6 Feb 2018 14:14:47 +0530 Subject: [PATCH] PRSDK-415: Updated config file to be generic Updated AM335x config file generically on all EDMA3 regions to allocate user request PARAM set from any regions. --- .../sample/src/platforms/sample_am335x_cfg.c | 77 ++++++++++++++++++ .../sample/src/platforms/sample_am335x_cfg.c | 79 ++++++++++++++++++- 2 files changed, 155 insertions(+), 1 deletion(-) diff --git a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_am335x_cfg.c b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_am335x_cfg.c index c4f8573..142cd13 100644 --- a/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_am335x_cfg.c +++ b/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_am335x_cfg.c @@ -455,6 +455,16 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU { /* Resources owned by Region 0 */ /* ownPaRAMSets */ +#ifdef EDMA3_RES_USER_REQ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#else /* 31 0 63 32 95 64 127 96 */ {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, /* 159 128 191 160 223 192 255 224 */ @@ -463,6 +473,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#endif /* ownDmaChannels */ /* 31 0 63 32 */ @@ -562,6 +573,16 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU { /* Resources owned by Region 2 */ /* ownPaRAMSets */ +#ifdef EDMA3_RES_USER_REQ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#else /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ @@ -570,6 +591,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#endif /* ownDmaChannels */ /* 31 0 63 32 */ @@ -610,6 +632,16 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU { /* Resources owned by Region 3 */ /* ownPaRAMSets */ +#ifdef EDMA3_RES_USER_REQ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#else /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ @@ -618,6 +650,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#endif /* ownDmaChannels */ /* 31 0 63 32 */ @@ -658,6 +691,16 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU { /* Resources owned by Region 4 */ /* ownPaRAMSets */ +#ifdef EDMA3_RES_USER_REQ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#else /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ @@ -666,6 +709,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#endif /* ownDmaChannels */ /* 31 0 63 32 */ @@ -706,6 +750,16 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU { /* Resources owned by Region 5 */ /* ownPaRAMSets */ +#ifdef EDMA3_RES_USER_REQ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#else /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ @@ -714,6 +768,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#endif /* ownDmaChannels */ /* 31 0 63 32 */ @@ -754,6 +809,16 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU { /* Resources owned by Region 6 */ /* ownPaRAMSets */ +#ifdef EDMA3_RES_USER_REQ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#else /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ @@ -762,6 +827,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#endif /* ownDmaChannels */ /* 31 0 63 32 */ @@ -802,6 +868,16 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU { /* Resources owned by Region 7 */ /* ownPaRAMSets */ +#ifdef EDMA3_RES_USER_REQ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#else /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ @@ -810,6 +886,7 @@ EDMA3_DRV_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NU 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#endif /* ownDmaChannels */ /* 31 0 63 32 */ diff --git a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_am335x_cfg.c b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_am335x_cfg.c index 11ae7cd..21f98ad 100644 --- a/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_am335x_cfg.c +++ b/packages/ti/sdo/edma3/rm/sample/src/platforms/sample_am335x_cfg.c @@ -454,6 +454,16 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM { /* Resources owned by Region 0 */ /* ownPaRAMSets */ +#ifdef EDMA3_RES_USER_REQ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#else /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ @@ -462,6 +472,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#endif /* ownDmaChannels */ /* 31 0 63 32 */ @@ -537,7 +548,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM /* Resources reserved by Region 1 */ /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ - {0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, + {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ @@ -561,6 +572,16 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM { /* Resources owned by Region 2 */ /* ownPaRAMSets */ +#ifdef EDMA3_RES_USER_REQ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#else /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ @@ -569,6 +590,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#endif /* ownDmaChannels */ /* 31 0 63 32 */ @@ -609,6 +631,16 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM { /* Resources owned by Region 3 */ /* ownPaRAMSets */ +#ifdef EDMA3_RES_USER_REQ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#else /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ @@ -617,6 +649,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#endif /* ownDmaChannels */ /* 31 0 63 32 */ @@ -657,6 +690,16 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM { /* Resources owned by Region 4 */ /* ownPaRAMSets */ +#ifdef EDMA3_RES_USER_REQ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#else /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ @@ -665,6 +708,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#endif /* ownDmaChannels */ /* 31 0 63 32 */ @@ -705,6 +749,16 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM { /* Resources owned by Region 5 */ /* ownPaRAMSets */ +#ifdef EDMA3_RES_USER_REQ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#else /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ @@ -713,6 +767,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#endif /* ownDmaChannels */ /* 31 0 63 32 */ @@ -753,6 +808,16 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM { /* Resources owned by Region 6 */ /* ownPaRAMSets */ +#ifdef EDMA3_RES_USER_REQ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#else /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ @@ -761,6 +826,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#endif /* ownDmaChannels */ /* 31 0 63 32 */ @@ -801,6 +867,16 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM { /* Resources owned by Region 7 */ /* ownPaRAMSets */ +#ifdef EDMA3_RES_USER_REQ + /* 31 0 63 32 95 64 127 96 */ + {0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 159 128 191 160 223 192 255 224 */ + 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, 0xFFFFFFFFU, + /* 287 256 319 288 351 320 383 352 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + /* 415 384 447 416 479 448 511 480 */ + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#else /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ @@ -809,6 +885,7 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig [NUM_EDMA3_INSTANCES][EDMA3_NUM 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, +#endif /* ownDmaChannels */ /* 31 0 63 32 */ -- 2.39.2