am65xx: Adding TX port queue size field to EMAC_FW_APP_CONFIG

 passed in at time of emac_open to perform TX port queue size check to
 ensure there is enough memory provided by the app to configure ICSSG
 SWITCH host/port and host egress queues.

 Adding macro to define port queue size per instance

diff --git a/emac_drv.h b/emac_drv.h
index 732bcd8e494b078dd058e79b20be0099292d35ab..9817760ef342e99769603739df9265dce481381d 100644 (file)
--- a/emac_drv.h
+++ b/emac_drv.h
@@ -143,8 +143,10 @@ typedef enum EMAC_DrvError_e
     /**< IOCTL command error, port is closed                                */
     EMAC_DRV_RESULT_IOCTL_ERR_SEND_MGMT_MSG                 = (-(int32_t)16),
     /**< IOCTL command error, error when sending MGMT message over PSI I/F to FW   */
-    EMAC_DRV_RESULT_IOCTL_ERR_NO_FREE_DESC                 = (-(int32_t)17),
+    EMAC_DRV_RESULT_IOCTL_ERR_NO_FREE_DESC                  = (-(int32_t)17),
     /**< IOCTL command error, no free descriptor available for sending MGMT message over PSI I/F to FW    */
+    EMAC_DRV_RESULT_TX_PORT_QUEUE_SIZE_ERR                  = (-(int32_t)18),
+    /**< Size of TX port queue is not big enough to setup all the FW port queues    */
     EMAC_DRV_RESULT_IOCTL_IN_PROGRESS                       = ((int32_t)1),
     /**< IOCTL command in progress                                          */
 } EMAC_DrvError;

diff --git a/firmware/icss_switch/config/emac_fw_config_switch.c b/firmware/icss_switch/config/emac_fw_config_switch.c
index f96797972a6e183399389a766e50baadc2dfe074..80ce93448cec93e3b906746ba70876b794a219cd 100644 (file)
--- a/firmware/icss_switch/config/emac_fw_config_switch.c
+++ b/firmware/icss_switch/config/emac_fw_config_switch.c
@@ -205,6 +205,7 @@ int32_t emacSetSwitchFwAppInitCfg(uint32_t portNum, EMAC_FW_APP_CONFIG *pFwAppCf
      {
           emacFwCfgMmapSwitch[portNum].fwAppCfg.txPortQueueHighAddr = pFwAppCfg->txPortQueueHighAddr;
           emacFwCfgMmapSwitch[portNum].fwAppCfg.txPortQueueLowAddr = pFwAppCfg->txPortQueueLowAddr;
+          emacFwCfgMmapSwitch[portNum].fwAppCfg.txPortQueueSize = pFwAppCfg->txPortQueueSize;
           return 0;
      }
      return ret;

diff --git a/firmware/icss_switch/config/emac_fw_config_switch.h b/firmware/icss_switch/config/emac_fw_config_switch.h
index 5939390b2885edb8965c769b3f8f6e2abb172a02..59831c355cf17f3e69d5a51b02f8a05a13f03904 100644 (file)
--- a/firmware/icss_switch/config/emac_fw_config_switch.h
+++ b/firmware/icss_switch/config/emac_fw_config_switch.h
@@ -50,6 +50,10 @@ extern int32_t emacSetSwitchFwConfig(uint32_t portNum, const EMAC_PER_PORT_ICSSG
 extern int32_t emacSetSwitchFwAppInitCfg(uint32_t portNum, EMAC_FW_APP_CONFIG *pFwAppCfg);\r
 extern int32_t emacGetSwitchFwAppInitCfg(uint32_t portNum, EMAC_FW_APP_CONFIG **pFwAppCfg);\r
 \r
+\r
+/* Size required for configurtion of port queues */\r
+#define EMAC_TOTAL_PORT_QUEUE_SIZE (MSMC_END_OFFSET/0x2 + 0x3F) & 0xFFFFFFC0\r
+\r
 #ifdef __cplusplus\r
 }\r
 #endif /* EMAC_FW_CONFIG_SWITCH_H_ */\r

diff --git a/src/v5/emac_drv_v5.c b/src/v5/emac_drv_v5.c
index ceced0dcabda229e497f1fd6a98284af745decd3..fd1b0b1e2cb6cf3c50e887e625bed0d27f26ac23 100644 (file)
--- a/src/v5/emac_drv_v5.c
+++ b/src/v5/emac_drv_v5.c
@@ -1268,7 +1268,7 @@ EMAC_TX_QUEUE_CONTEXT host_egress_q_desc_context[EMAC_NUM_HOST_EGRESS_FW_QUEUES]
 /*
  *  ======== emac_config_icssg_switch_fw========
  */
-static void emac_config_icssg_switch_fw(uint32_t port_num, EMAC_HwAttrs_V5 *hwAttrs)
+static int32_t emac_config_icssg_switch_fw(uint32_t port_num, EMAC_HwAttrs_V5 *hwAttrs)
 {
     uint8_t queue_num;
     uint32_t smem_offset;
@@ -1290,6 +1290,7 @@ static void emac_config_icssg_switch_fw(uint32_t port_num, EMAC_HwAttrs_V5 *hwAt
     Udma_ChHandle chHandle;
     uint32_t flowIdBase;
     uint32_t descQueueSize;
+    int32_t retVal = EMAC_DRV_RESULT_OK;
 
     emac_mcb.port_cb[port_num].getFwCfg= hwAttrs->portCfg[port_num].getFwCfg;
     emac_mcb.port_cb[port_num].icssSharedRamBaseAddr = hwAttrs->portCfg[port_num].icssSharedRamBaseAddr;
@@ -1350,76 +1351,86 @@ static void emac_config_icssg_switch_fw(uint32_t port_num, EMAC_HwAttrs_V5 *hwAt
             emac_hw_mem_write (smem_offset, &(host_egress_q_msmc_context[queue_num]), (sizeof(EMAC_TX_QUEUE_CONTEXT)/sizeof(uint32_t)));
         }
 
-        /* write context for all Port descriptor queues to SMEM */
-        smem_offset_start_port_desc_Q_context = smem_offset + EMAC_NRT_QUEUE_CONTEXT_SIZE;
-        start_of_port_desc_Q_offset = pSwitchFwCfg->descQueueOffset;
-        for(queue_num = 0; queue_num < EMAC_NUM_TRANSMIT_FW_QUEUES; queue_num++) 
+        /* need size check to make sure memory for port queue is big enough */
+        if ((host_egress_q_msmc_context[1].end_addr - txPortQBaseAddr) > pEmacFwCfg->fwAppCfg.txPortQueueSize)
         {
-            descQueueSize = pSwitchFwCfg->txPortQueueDescSize;
-            port_tx_q_desc_context[queue_num].start_addr = start_of_port_desc_Q_offset + descQueueSize * queue_num;
-            port_tx_q_desc_context[queue_num].rd_ptr = port_tx_q_desc_context[queue_num].start_addr;
-            port_tx_q_desc_context[queue_num].wr_ptr = port_tx_q_desc_context[queue_num].start_addr;
-            port_tx_q_desc_context[queue_num].end_addr = port_tx_q_desc_context[queue_num].start_addr + descQueueSize;
-            smem_offset = smem_offset_start_port_desc_Q_context +  EMAC_NRT_QUEUE_CONTEXT_SIZE * queue_num;
-            emac_hw_mem_write (smem_offset, &(port_tx_q_desc_context[queue_num]), (sizeof(EMAC_TX_QUEUE_CONTEXT)/sizeof(uint32_t)));
+            retVal = EMAC_DRV_RESULT_TX_PORT_QUEUE_SIZE_ERR;
         }
 
-        /* write context for all Host descriptor queues to SMEM */
-        smem_offset_start_host_desc_Q_context = smem_offset + EMAC_NRT_QUEUE_CONTEXT_SIZE;
-        start_of_host_desc_Q_offset = port_tx_q_desc_context[EMAC_NUM_TRANSMIT_FW_QUEUES-1].end_addr;
-        for(queue_num = 0; queue_num < EMAC_NUM_TRANSMIT_FW_QUEUES; queue_num++) 
-        {
-            descQueueSize = pSwitchFwCfg->txHostQueueDescSize;
-            host_tx_q_desc_context[queue_num].start_addr = start_of_host_desc_Q_offset + descQueueSize * queue_num;
-            host_tx_q_desc_context[queue_num].rd_ptr = host_tx_q_desc_context[queue_num].start_addr;
-            host_tx_q_desc_context[queue_num].wr_ptr = host_tx_q_desc_context[queue_num].start_addr;
-            host_tx_q_desc_context[queue_num].end_addr = host_tx_q_desc_context[queue_num].start_addr+ descQueueSize ;
-            smem_offset = smem_offset_start_host_desc_Q_context + EMAC_NRT_QUEUE_CONTEXT_SIZE * queue_num; 
-            emac_hw_mem_write (smem_offset, &(host_tx_q_desc_context[queue_num]), (sizeof(EMAC_TX_QUEUE_CONTEXT)/sizeof(uint32_t)));
-        }
-
-        /* write context for all Host egress descriptor queues to SMEM */
-        smem_offset_start_host_egress_desc_Q_context = smem_offset + EMAC_NRT_QUEUE_CONTEXT_SIZE;
-        start_of_host_egress_desc_Q_offset = host_tx_q_desc_context[EMAC_NUM_TRANSMIT_FW_QUEUES-1].end_addr;
-        for(queue_num = 0; queue_num < EMAC_NUM_HOST_EGRESS_FW_QUEUES; queue_num++) 
-        {
-            descQueueSize = pSwitchFwCfg->txPortQueueDescSize;
-            host_egress_q_desc_context[queue_num].start_addr = start_of_host_egress_desc_Q_offset + descQueueSize * queue_num;
-            host_egress_q_desc_context[queue_num].rd_ptr = host_egress_q_desc_context[queue_num].start_addr;
-            host_egress_q_desc_context[queue_num].wr_ptr = host_egress_q_desc_context[queue_num].start_addr;
-            host_egress_q_desc_context[queue_num].end_addr = host_egress_q_desc_context[queue_num].start_addr+ descQueueSize ;
-            smem_offset = smem_offset_start_host_egress_desc_Q_context + EMAC_NRT_QUEUE_CONTEXT_SIZE * queue_num; 
-            emac_hw_mem_write (smem_offset, &(host_egress_q_desc_context[queue_num]), (sizeof(EMAC_TX_QUEUE_CONTEXT)/sizeof(uint32_t)));
-        }
-
-        /* write pkt flow Id start to SMEM */
-        smem_offset = hwAttrs->portCfg[port_num].icssSharedRamBaseAddr + pSwitchFwCfg->pktFlowIdOffset;
-
-        /* Flow for rx pkt. 1 subChan use default flow */
-        if (emac_mcb.port_cb[port_num].rxPktCh.nsubChan > 1)
-        {
-            flowIdBase = Udma_flowGetNum(emac_mcb.port_cb[port_num].rxPktCh.flowHandle);
-        }
-        else
+        if (retVal == EMAC_DRV_RESULT_OK)
         {
-            chHandle = emac_mcb.port_cb[port_num].rxPktCh.rxChHandle;
-            flowHandle = Udma_chGetDefaultFlowHandle(chHandle);
-            flowIdBase= Udma_flowGetNum( flowHandle);
-        }
+            /* write context for all Port descriptor queues to SMEM */
+            smem_offset_start_port_desc_Q_context = smem_offset + EMAC_NRT_QUEUE_CONTEXT_SIZE;
+            start_of_port_desc_Q_offset = pSwitchFwCfg->descQueueOffset;
+            for(queue_num = 0; queue_num < EMAC_NUM_TRANSMIT_FW_QUEUES; queue_num++) 
+            {
+                descQueueSize = pSwitchFwCfg->txPortQueueDescSize;
+                port_tx_q_desc_context[queue_num].start_addr = start_of_port_desc_Q_offset + descQueueSize * queue_num;
+                port_tx_q_desc_context[queue_num].rd_ptr = port_tx_q_desc_context[queue_num].start_addr;
+                port_tx_q_desc_context[queue_num].wr_ptr = port_tx_q_desc_context[queue_num].start_addr;
+                port_tx_q_desc_context[queue_num].end_addr = port_tx_q_desc_context[queue_num].start_addr + descQueueSize;
+                smem_offset = smem_offset_start_port_desc_Q_context +  EMAC_NRT_QUEUE_CONTEXT_SIZE * queue_num;
+                emac_hw_mem_write (smem_offset, &(port_tx_q_desc_context[queue_num]), (sizeof(EMAC_TX_QUEUE_CONTEXT)/sizeof(uint32_t)));
+            }
+    
+            /* write context for all Host descriptor queues to SMEM */
+            smem_offset_start_host_desc_Q_context = smem_offset + EMAC_NRT_QUEUE_CONTEXT_SIZE;
+            start_of_host_desc_Q_offset = port_tx_q_desc_context[EMAC_NUM_TRANSMIT_FW_QUEUES-1].end_addr;
+            for(queue_num = 0; queue_num < EMAC_NUM_TRANSMIT_FW_QUEUES; queue_num++) 
+            {
+                descQueueSize = pSwitchFwCfg->txHostQueueDescSize;
+                host_tx_q_desc_context[queue_num].start_addr = start_of_host_desc_Q_offset + descQueueSize * queue_num;
+                host_tx_q_desc_context[queue_num].rd_ptr = host_tx_q_desc_context[queue_num].start_addr;
+                host_tx_q_desc_context[queue_num].wr_ptr = host_tx_q_desc_context[queue_num].start_addr;
+                host_tx_q_desc_context[queue_num].end_addr = host_tx_q_desc_context[queue_num].start_addr+ descQueueSize ;
+                smem_offset = smem_offset_start_host_desc_Q_context + EMAC_NRT_QUEUE_CONTEXT_SIZE * queue_num; 
+                emac_hw_mem_write (smem_offset, &(host_tx_q_desc_context[queue_num]), (sizeof(EMAC_TX_QUEUE_CONTEXT)/sizeof(uint32_t)));
+            }
+    
+            /* write context for all Host egress descriptor queues to SMEM */
+            smem_offset_start_host_egress_desc_Q_context = smem_offset + EMAC_NRT_QUEUE_CONTEXT_SIZE;
+            start_of_host_egress_desc_Q_offset = host_tx_q_desc_context[EMAC_NUM_TRANSMIT_FW_QUEUES-1].end_addr;
+            for(queue_num = 0; queue_num < EMAC_NUM_HOST_EGRESS_FW_QUEUES; queue_num++) 
+            {
+                descQueueSize = pSwitchFwCfg->txPortQueueDescSize;
+                host_egress_q_desc_context[queue_num].start_addr = start_of_host_egress_desc_Q_offset + descQueueSize * queue_num;
+                host_egress_q_desc_context[queue_num].rd_ptr = host_egress_q_desc_context[queue_num].start_addr;
+                host_egress_q_desc_context[queue_num].wr_ptr = host_egress_q_desc_context[queue_num].start_addr;
+                host_egress_q_desc_context[queue_num].end_addr = host_egress_q_desc_context[queue_num].start_addr+ descQueueSize ;
+                smem_offset = smem_offset_start_host_egress_desc_Q_context + EMAC_NRT_QUEUE_CONTEXT_SIZE * queue_num; 
+                emac_hw_mem_write (smem_offset, &(host_egress_q_desc_context[queue_num]), (sizeof(EMAC_TX_QUEUE_CONTEXT)/sizeof(uint32_t)));
+            }
 
-        /* Flow for rx mgmt, 1 subChan use default flow */
-        if (emac_mcb.port_cb[port_num].rxMgmtCh.nsubChan > 1)
-        {
-            flowIdBase |= (Udma_flowGetNum(emac_mcb.port_cb[port_num].rxMgmtCh.flowHandle) << 16);
-        }
-        else
-        {
-            chHandle = emac_mcb.port_cb[port_num].rxMgmtCh.rxChHandle;
-            flowHandle = Udma_chGetDefaultFlowHandle(chHandle);
-            flowIdBase |= Udma_flowGetNum( flowHandle) << 16;
+            /* write pkt flow Id start to SMEM */
+            smem_offset = hwAttrs->portCfg[port_num].icssSharedRamBaseAddr + pSwitchFwCfg->pktFlowIdOffset;
+    
+            /* Flow for rx pkt. 1 subChan use default flow */
+            if (emac_mcb.port_cb[port_num].rxPktCh.nsubChan > 1)
+            {
+                flowIdBase = Udma_flowGetNum(emac_mcb.port_cb[port_num].rxPktCh.flowHandle);
+            }
+            else
+            {
+                chHandle = emac_mcb.port_cb[port_num].rxPktCh.rxChHandle;
+                flowHandle = Udma_chGetDefaultFlowHandle(chHandle);
+                flowIdBase= Udma_flowGetNum( flowHandle);
+            }
+    
+            /* Flow for rx mgmt, 1 subChan use default flow */
+            if (emac_mcb.port_cb[port_num].rxMgmtCh.nsubChan > 1)
+            {
+                flowIdBase |= (Udma_flowGetNum(emac_mcb.port_cb[port_num].rxMgmtCh.flowHandle) << 16);
+            }
+            else
+            {
+                chHandle = emac_mcb.port_cb[port_num].rxMgmtCh.rxChHandle;
+                flowHandle = Udma_chGetDefaultFlowHandle(chHandle);
+                flowIdBase |= Udma_flowGetNum( flowHandle) << 16;
+            }
+            emac_hw_mem_write (smem_offset, &(flowIdBase), 1);
         }
-        emac_hw_mem_write (smem_offset, &(flowIdBase), 1);
     }
+    return retVal;
 }
 
 /*
@@ -1502,15 +1513,18 @@ static EMAC_DRV_ERR_E  emac_open_v5_local(uint32_t port_num, uint32_t switch_por
         /* lets configure the switch firmware based on switch port */
         if (switch_port_num== EMAC_SWITCH_PORT)
         {
-           emac_config_icssg_switch_fw(port_num, hwAttrs);
-           emac_switch_vlan_init(port_num, p_config);
-           emac_switch_config_ft3_priority_tag(port_num);
+            if (emac_config_icssg_switch_fw(port_num, hwAttrs) != EMAC_DRV_RESULT_OK)
+            {
+                return EMAC_DRV_RESULT_OPEN_PORT_ERR;
+            }
+            emac_switch_vlan_init(port_num, p_config);
+            emac_switch_config_ft3_priority_tag(port_num);
         }
         else
         {
-           emac_config_icssg_dual_mac_fw(port_num, hwAttrs);
-           /* Update classifier/filters for PORT_MAC address */
-           emac_ioctl_icss_add_mac(port_num,p_config->p_chan_mac_addr->p_mac_addr->addr);
+            emac_config_icssg_dual_mac_fw(port_num, hwAttrs);
+            /* Update classifier/filters for PORT_MAC address */
+            emac_ioctl_icss_add_mac(port_num,p_config->p_chan_mac_addr->p_mac_addr->addr);
         }
     }
 

diff --git a/src/v5/emac_drv_v5.h b/src/v5/emac_drv_v5.h
index bd732a01e3ec88bf7ce08611cdb94182e7d334a9..cd1dd4196f0c8d832c716015ba3ba9847361208b 100644 (file)
--- a/src/v5/emac_drv_v5.h
+++ b/src/v5/emac_drv_v5.h
@@ -288,6 +288,7 @@ typedef struct EMAC_PER_CHANNEL_CFG_RX_s{
 typedef struct EMAC_FW_APP_CONFIG_S {
     uint32_t txPortQueueHighAddr;                           /* MSMC address high of transmit queues */
     uint32_t txPortQueueLowAddr;                            /* MSMC address low of  transmit queues */
+    uint32_t txPortQueueSize;                               /* Total size required in bytes for all port queues */
 }EMAC_FW_APP_CONFIG;
 
 struct EMAC_FW_PORT_CFG;