am65xx: Update icssg switch firmware

 update firmware headers
 update firmware memory map files
 adding version.txt with version info

Signed-off-by: Tinku Mannan <tmannan@ti.com>

diff --git a/firmware/icss_switch/bin/RTU0_SLICE0_bin.h b/firmware/icss_switch/bin/RTU0_SLICE0_bin.h
index ef59db62d67004c2369b0f196bc82f80e85a08ea..8a2a9cca80d4a4f25dd8ccb2711f189de09badd2 100644 (file)
--- a/firmware/icss_switch/bin/RTU0_SLICE0_bin.h
+++ b/firmware/icss_switch/bin/RTU0_SLICE0_bin.h
@@ -62,21 +62,21 @@ const unsigned int RTU0_SLICE0_b00[]= {
 0xe1003293,
 0x240002d2,
 0x24a10092,
-0x24013ff3,
-0x240097f4,
-0x24013ff5,
+0x240131f3,
+0x240094f4,
+0x240131f5,
 0xe108b293,
-0x24013ff3,
-0x2400ccf4,
+0x240131f3,
+0x2400bcf4,
 0xe1147293,
 0x240002d2,
 0x24a10092,
-0x24013ff3,
-0x24013ff4,
-0x24013ff5,
+0x240131f3,
+0x240131f4,
+0x240131f5,
 0xe11cb293,
-0x24013ff3,
-0x24013ff4,
+0x240131f3,
+0x240131f4,
 0xe1287293,
 0x240002d2,
 0x24a10092,
@@ -156,17 +156,14 @@ const unsigned int RTU0_SLICE0_b00[]= {
 0x5f018af9,
 0x2eff819e,
 0x1f049e9e,
-0x910c1952,
-0x51005202,
-0x1f0c9e9e,
-0x23021295,
+0x23020895,
 0x2ea80181,
 0x110fe1e1,
-0x5700e1fa,
+0x5700e1fd,
 0x51002e04,
 0x102ee152,
 0x69005206,
-0x7f0000f6,
+0x7f0000f9,
 0x51000e03,
 0x100ee152,
 0x69005206,
@@ -181,8 +178,8 @@ const unsigned int RTU0_SLICE0_b00[]= {
 0x00520101,
 0x2c20016e,
 0x1f054e4e,
-0x2301ecd5,
-0x570137e6,
+0x2301e2d5,
+0x570137e9,
 0x1f064e4e,
 0x100ee12e,
 0x1c520e0e,
@@ -192,34 +189,27 @@ const unsigned int RTU0_SLICE0_b00[]= {
 0x7900000d,
 0x2ea88981,
 0x24000017,
-0x23014195,
-0x7f0000db,
+0x23013395,
+0x7f0000de,
 0x2ea90981,
 0x24000117,
-0x23014195,
-0x7f0000d7,
+0x23013395,
+0x7f0000da,
 0x2ea98981,
 0x24000217,
-0x23014195,
-0x7f0000d3,
+0x23013395,
+0x7f0000d6,
 0x2eaa0981,
 0x24000317,
-0x23014195,
-0x7f0000cf,
+0x23013395,
+0x7f0000d2,
 0x2f853380,
 0x2e878a02,
-0xc90c9e07,
-0xd104072a,
-0xc9020705,
-0x2e85861a,
-0x103c3c04,
-0x10dcdcc3,
-0x101d1d07,
-0xc90ec329,
+0xc90ec323,
 0xc90bc302,
 0x81145cc5,
 0xd1010703,
-0xd1000725,
+0xd100071f,
 0x79000003,
 0xc9000702,
 0x1f067a7a,
@@ -250,15 +240,9 @@ const unsigned int RTU0_SLICE0_b00[]= {
 0x10e2e2e4,
 0x2f0f008a,
 0x2f0f0f82,
-0x79000006,
-0xc9030705,
-0x1004043c,
-0x1007071d,
-0x10c3c3dc,
-0x2f05861a,
 0x2efe0060,
 0x2f853380,
-0x2100cb00,
+0x2100bb00,
 0x2f853380,
 0x2e878a02,
 0x2eff861a,
@@ -311,21 +295,23 @@ const unsigned int RTU0_SLICE0_b00[]= {
 0x24000013,
 0xc9020c05,
 0x11074a13,
-0xc9044a0e,
+0xc9044a11,
 0x1f04c3c3,
-0x7900000c,
+0x7900000f,
 0xc9021c03,
 0x24000513,
-0x79000009,
-0xc9001c04,
-0xc90a9e06,
+0x7900000c,
+0xc9001c08,
+0xd1051c05,
+0xd1071c04,
+0xc90a9e07,
 0x24000513,
-0x79000005,
-0xc9049e03,
+0x79000006,
+0x24000113,
+0x79000004,
 0xc9072a02,
 0x13011313,
 0x24000413,
-0xc9049e02,
 0x102a1313,
 0xc9001302,
 0x1f0cc3c3,
@@ -351,10 +337,10 @@ const unsigned int RTU0_SLICE0_b00[]= {
 0xc9002e03,
 0x13057a7a,
 0x79000006,
-0xd1050705,
+0xd1061c05,
 0x1f007a7a,
 0x79000003,
-0xc9050702,
+0xc9061c02,
 0x1f027a7a,
 0xc9040c02,
 0x7900000d,
@@ -373,16 +359,16 @@ const unsigned int RTU0_SLICE0_b00[]= {
 0x2f0780c3,
 0x2efe0060,
 0x2f853380,
-0x21013e00,
+0x21013000,
 0x2efe0060,
-0x21014000,
+0x21013200,
 0x6900411f,
 0x1107646e,
 0x69014405,
 0x1f034e4e,
 0x24000152,
 0x0817522e,
-0x790000a4,
+0x790000a8,
 0x51004402,
 0x1f044e4e,
 0x0b1be2e2,
@@ -391,29 +377,28 @@ const unsigned int RTU0_SLICE0_b00[]= {
 0x1f034e4e,
 0x24000152,
 0x0817522e,
-0x7900009b,
+0x7900009f,
 0x108383ef,
 0x090cefef,
-0xd1064e98,
-0x2301ecd5,
-0x51013796,
+0xd1064e9c,
+0x2301e2d5,
+0x5101379a,
 0x24000152,
 0x0817522e,
-0x79000093,
+0x79000097,
 0x69104102,
-0x79000091,
-0xd1034e90,
-0xc91fe38f,
+0x79000095,
+0xd1034e94,
+0xc91fe393,
 0x1f074e4e,
 0x81303c82,
-0x7900008c,
+0x79000090,
 0x6f1441f9,
-0xd1024e38,
+0xd1024e3c,
 0x1f024e4e,
-0xd1034e46,
-0xd1089e31,
+0xd1034e4a,
+0xd1089e35,
 0x2ed00782,
-0xc9049e10,
 0x24000016,
 0x240081d3,
 0x50d38506,
@@ -430,23 +415,23 @@ const unsigned int RTU0_SLICE0_b00[]= {
 0x6900d302,
 0x1f011616,
 0x10838393,
-0x81782982,
+0x81702982,
+0x81740993,
+0x2eff8292,
+0x81782992,
 0x817c2993,
 0x917c2993,
 0x2e91040a,
 0xcf030cff,
-0xd1044e0a,
-0xd1040c02,
-0x13076a6a,
-0xd1049e02,
-0x13072a2a,
-0x106a2a6a,
-0x11066a52,
+0xd1044e08,
+0xd1020c02,
+0x13074a4a,
+0x104a2a4a,
+0x11064a52,
 0x51065203,
-0xd1026a02,
-0x79000010,
-0xc9049e0b,
-0xd1046a0a,
+0xd1024a02,
+0x79000014,
+0xd1044a0a,
 0xc9052a07,
 0xc9011603,
 0x13056f6f,
@@ -459,6 +444,11 @@ const unsigned int RTU0_SLICE0_b00[]= {
 0x2ed00782,
 0x24002101,
 0x81440901,
+0x0b0ceff2,
+0x090ef2f2,
+0x24008072,
+0x24000212,
+0x81802592,
 0x79000015,
 0x1f034e4e,
 0x24002201,

diff --git a/firmware/icss_switch/bin/RTU0_SLICE1_bin.h b/firmware/icss_switch/bin/RTU0_SLICE1_bin.h
index d9064a27b38fbd3acd37a4ba9494cc74c41908d0..9d1c1ee74e27d16c83262e3debcdf10a295e8423 100644 (file)
--- a/firmware/icss_switch/bin/RTU0_SLICE1_bin.h
+++ b/firmware/icss_switch/bin/RTU0_SLICE1_bin.h
@@ -62,21 +62,21 @@ const unsigned int RTU0_SLICE1_b00[]= {
 0xe1003293,
 0x240002d2,
 0x24a10092,
-0x24013ff3,
-0x240097f4,
-0x24013ff5,
+0x240131f3,
+0x240094f4,
+0x240131f5,
 0xe108b293,
-0x24013ff3,
-0x2400ccf4,
+0x240131f3,
+0x2400bcf4,
 0xe1147293,
 0x240002d2,
 0x24a10092,
-0x24013ff3,
-0x24013ff4,
-0x24013ff5,
+0x240131f3,
+0x240131f4,
+0x240131f5,
 0xe11cb293,
-0x24013ff3,
-0x24013ff4,
+0x240131f3,
+0x240131f4,
 0xe1287293,
 0x240002d2,
 0x24a10092,
@@ -156,17 +156,14 @@ const unsigned int RTU0_SLICE1_b00[]= {
 0x5f018af9,
 0x2eff819e,
 0x1f049e9e,
-0x910c1952,
-0x51005202,
-0x1f0c9e9e,
-0x23021295,
+0x23020895,
 0x2ea80181,
 0x110fe1e1,
-0x5700e1fa,
+0x5700e1fd,
 0x51002e04,
 0x102ee152,
 0x69005206,
-0x7f0000f6,
+0x7f0000f9,
 0x51000e03,
 0x100ee152,
 0x69005206,
@@ -181,8 +178,8 @@ const unsigned int RTU0_SLICE1_b00[]= {
 0x00520101,
 0x2c20016e,
 0x1f054e4e,
-0x2301ecd5,
-0x570137e6,
+0x2301e2d5,
+0x570137e9,
 0x1f064e4e,
 0x100ee12e,
 0x1c520e0e,
@@ -192,34 +189,27 @@ const unsigned int RTU0_SLICE1_b00[]= {
 0x7900000d,
 0x2ea88981,
 0x24000017,
-0x23014195,
-0x7f0000db,
+0x23013395,
+0x7f0000de,
 0x2ea90981,
 0x24000117,
-0x23014195,
-0x7f0000d7,
+0x23013395,
+0x7f0000da,
 0x2ea98981,
 0x24000217,
-0x23014195,
-0x7f0000d3,
+0x23013395,
+0x7f0000d6,
 0x2eaa0981,
 0x24000317,
-0x23014195,
-0x7f0000cf,
+0x23013395,
+0x7f0000d2,
 0x2f853380,
 0x2e878a02,
-0xc90c9e07,
-0xd104072a,
-0xc9020705,
-0x2e85861a,
-0x103c3c04,
-0x10dcdcc3,
-0x101d1d07,
-0xc90ec329,
+0xc90ec323,
 0xc90bc302,
 0x81145cc5,
 0xd1010703,
-0xd1000725,
+0xd100071f,
 0x79000003,
 0xc9000702,
 0x1f067a7a,
@@ -250,15 +240,9 @@ const unsigned int RTU0_SLICE1_b00[]= {
 0x10e2e2e4,
 0x2f0f008a,
 0x2f0f0f82,
-0x79000006,
-0xc9030705,
-0x1004043c,
-0x1007071d,
-0x10c3c3dc,
-0x2f05861a,
 0x2efe0060,
 0x2f853380,
-0x2100cb00,
+0x2100bb00,
 0x2f853380,
 0x2e878a02,
 0x2eff861a,
@@ -311,21 +295,23 @@ const unsigned int RTU0_SLICE1_b00[]= {
 0x24000013,
 0xc9020c05,
 0x11074a13,
-0xc9044a0e,
+0xc9044a11,
 0x1f04c3c3,
-0x7900000c,
+0x7900000f,
 0xc9021c03,
 0x24000313,
-0x79000009,
-0xc9001c04,
-0xc90a9e06,
+0x7900000c,
+0xc9001c08,
+0xd1051c05,
+0xd1071c04,
+0xc90a9e07,
 0x24000313,
-0x79000005,
-0xc9049e03,
+0x79000006,
+0x24000113,
+0x79000004,
 0xc9072a02,
 0x13011313,
 0x24000213,
-0xc9049e02,
 0x102a1313,
 0xc9001302,
 0x1f0cc3c3,
@@ -351,10 +337,10 @@ const unsigned int RTU0_SLICE1_b00[]= {
 0xc9002e03,
 0x13057a7a,
 0x79000006,
-0xd1050705,
+0xd1061c05,
 0x1f007a7a,
 0x79000003,
-0xc9050702,
+0xc9061c02,
 0x1f027a7a,
 0xc9040c02,
 0x7900000d,
@@ -373,16 +359,16 @@ const unsigned int RTU0_SLICE1_b00[]= {
 0x2f0780c3,
 0x2efe0060,
 0x2f853380,
-0x21013e00,
+0x21013000,
 0x2efe0060,
-0x21014000,
+0x21013200,
 0x6900411f,
 0x1107646e,
 0x69024405,
 0x1f034e4e,
 0x24000152,
 0x0817522e,
-0x790000a4,
+0x790000a8,
 0x51004402,
 0x1f044e4e,
 0x0b1be2e2,
@@ -391,29 +377,28 @@ const unsigned int RTU0_SLICE1_b00[]= {
 0x1f034e4e,
 0x24000152,
 0x0817522e,
-0x7900009b,
+0x7900009f,
 0x108383ef,
 0x090cefef,
-0xd1064e98,
-0x2301ecd5,
-0x51013796,
+0xd1064e9c,
+0x2301e2d5,
+0x5101379a,
 0x24000152,
 0x0817522e,
-0x79000093,
+0x79000097,
 0x69104102,
-0x79000091,
-0xd1034e90,
-0xc91fe38f,
+0x79000095,
+0xd1034e94,
+0xc91fe393,
 0x1f074e4e,
 0x81303c82,
-0x7900008c,
+0x79000090,
 0x6f1441f9,
-0xd1024e38,
+0xd1024e3c,
 0x1f024e4e,
-0xd1034e46,
-0xd1089e31,
+0xd1034e4a,
+0xd1089e35,
 0x2ed00782,
-0xc9049e10,
 0x24000016,
 0x240081d3,
 0x50d38506,
@@ -430,23 +415,23 @@ const unsigned int RTU0_SLICE1_b00[]= {
 0x6900d302,
 0x1f011616,
 0x10838393,
-0x81782982,
+0x81702982,
+0x81740993,
+0x2eff8292,
+0x81782992,
 0x817c2993,
 0x917c2993,
 0x2e91040a,
 0xcf030cff,
-0xd1044e0a,
-0xd1040c02,
-0x13076a6a,
-0xd1049e02,
-0x13072a2a,
-0x106a2a6a,
-0x11066a52,
+0xd1044e08,
+0xd1020c02,
+0x13074a4a,
+0x104a2a4a,
+0x11064a52,
 0x51065203,
-0xd1016a02,
-0x79000010,
-0xc9049e0b,
-0xd1046a0a,
+0xd1014a02,
+0x79000014,
+0xd1044a0a,
 0xc9042a07,
 0xc9011603,
 0x13056f6f,
@@ -459,6 +444,11 @@ const unsigned int RTU0_SLICE1_b00[]= {
 0x2ed00782,
 0x24002101,
 0x81440901,
+0x0b0ceff2,
+0x090ef2f2,
+0x24008072,
+0x24000212,
+0x81802592,
 0x79000015,
 0x1f034e4e,
 0x24002201,

diff --git a/firmware/icss_switch/bin/RX_PRU_SLICE0_bin.h b/firmware/icss_switch/bin/RX_PRU_SLICE0_bin.h
index f3b5d530c753b709b423fa206b4d370dcf50b5ad..37cc7850267d5dff8b743dae6710233c443d5fb5 100644 (file)
--- a/firmware/icss_switch/bin/RX_PRU_SLICE0_bin.h
+++ b/firmware/icss_switch/bin/RX_PRU_SLICE0_bin.h
@@ -63,21 +63,21 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0xe1003293,
 0x240002d2,
 0x24a00092,
-0x240208f3,
-0x240302f4,
-0x2402b6f5,
+0x240215f3,
+0x2402c6f4,
+0x24028df5,
 0xe108b293,
-0x24020df3,
-0x240208f4,
+0x24021af3,
+0x240215f4,
 0xe1147293,
 0x240002d2,
 0x24a00092,
-0x240208f3,
-0x24020af4,
-0x240208f5,
+0x240215f3,
+0x240217f4,
+0x240215f5,
 0xe11cb293,
-0x240208f3,
-0x240208f4,
+0x240215f3,
+0x240215f4,
 0xe1287293,
 0x240002d2,
 0x24a00092,
@@ -186,15 +186,15 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x10000000,
 0x2f0f0f82,
 0x01018a8a,
+0x91702180,
+0x1f04e0e0,
+0x81702180,
 0x2effbb80,
-0x910c1952,
-0x51005202,
-0x1f0a9e9e,
 0x91383992,
 0x50d2920c,
 0x9114dc8d,
 0x108f8fce,
-0x2304f193,
+0x23038293,
 0x0101d2d2,
 0x813a19d2,
 0x913c3992,
@@ -207,43 +207,51 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x50d29207,
 0x9144d98d,
 0x108f8fce,
-0x2304f193,
+0x23038293,
 0x0101d2d2,
 0x814219d2,
 0x814212d2,
 0x91740152,
-0xc9035220,
+0xc9035228,
 0x24000852,
 0x81740152,
 0x91106182,
-0x240098c4,
-0x24968084,
+0x91687984,
 0x00e4e2e2,
 0x0300e3e3,
+0x00e5e3e3,
 0x81906182,
 0x91241c8a,
 0x2f0f008a,
 0x10000000,
 0x10000000,
 0x2e8f0f82,
-0xc9036303,
-0xd1066302,
+0xc9036305,
+0xc9066303,
+0x1d066363,
+0x79000002,
 0x2eff8382,
-0xc9036503,
-0xd1066502,
+0xc9036505,
+0xc9066503,
+0x1d066565,
+0x79000002,
 0x2eff8384,
-0xc9036703,
-0xd1066702,
+0xc9036705,
+0xc9066703,
+0x1d066767,
+0x79000002,
 0x2eff8386,
-0xc9036903,
-0xd1066902,
+0xc9036905,
+0xc9066903,
+0x1d066969,
+0x79000002,
 0x2eff8388,
+0x2f0f1082,
 0x01018a8a,
 0x24020093,
 0x68938a02,
 0x2400008a,
 0x81241c8a,
-0x2f0f1082,
 0x91781c80,
 0xc90000a0,
 0x6900209f,
@@ -415,7 +423,7 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x51075c67,
 0x51085c74,
 0x7900007f,
-0x51009c9f,
+0x51009ca4,
 0x2400028a,
 0x32000000,
 0x2f18008a,
@@ -438,7 +446,7 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x2eb00012,
 0xc903f203,
 0x2400015c,
-0x79000088,
+0x7900008d,
 0x2eb00f82,
 0x81407c82,
 0x0120fafa,
@@ -448,7 +456,7 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x2ea80381,
 0xd100e203,
 0x2400025c,
-0x7900007d,
+0x79000082,
 0x10040412,
 0x2400008a,
 0x32000000,
@@ -459,8 +467,8 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x00128282,
 0x81103992,
 0x2f288981,
-0x049bdbd1,
-0x7120d128,
+0x049bdbde,
+0x7120de28,
 0x10fafaf3,
 0x24000094,
 0x24000492,
@@ -469,12 +477,12 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x2eb00012,
 0xc903f203,
 0x2400035c,
-0x79000069,
+0x7900006e,
 0x2400005c,
 0x2ea80381,
 0xd100e203,
 0x2400045c,
-0x79000064,
+0x79000069,
 0x2eb00f82,
 0x69818507,
 0x91101912,
@@ -492,7 +500,7 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x2ea80381,
 0xd100e203,
 0x2400055c,
-0x79000051,
+0x79000056,
 0x241014c1,
 0x24000081,
 0x2ed08f82,
@@ -508,11 +516,11 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x2eb00012,
 0xc903f203,
 0x2400065c,
-0x79000042,
+0x79000047,
 0x2eb00f82,
 0x0120fafa,
-0x00d19b9b,
-0x7110d10f,
+0x00de9b9b,
+0x7110de0f,
 0x10e2e2ea,
 0x79000002,
 0x95143982,
@@ -520,12 +528,12 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x2ea80381,
 0xd100e203,
 0x2400075c,
-0x79000035,
+0x7900003a,
 0x10eaeae2,
 0x241014c1,
 0x24000081,
 0x2f288981,
-0x0510d1d1,
+0x0510dede,
 0x2ed08f82,
 0x10e2e2ea,
 0x79000002,
@@ -534,18 +542,18 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x2ea80381,
 0xd100e203,
 0x2400085c,
-0x79000027,
+0x7900002c,
 0x10eaeae2,
 0x240014c1,
 0x24001081,
-0x10d1d161,
-0x0104d140,
+0x10dede61,
+0x0104de40,
 0x2f28bf01,
 0x2400005c,
 0x2ea80381,
 0xd100e203,
 0x2400095c,
-0x7900001d,
+0x79000022,
 0x240f18c1,
 0x24001281,
 0x91407c82,
@@ -565,6 +573,11 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x05019c9c,
 0x24002001,
 0x81400901,
+0x10dbdbf2,
+0x090ef2f2,
+0x24008072,
+0x24000012,
+0x81802592,
 0x0104e7e7,
 0x68e7e902,
 0x10e6e6e7,
@@ -574,68 +587,15 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x32800000,
 0x79000002,
 0x85143982,
-0x7d00007d,
+0x7d000073,
 0x2efe0060,
-0x21020900,
+0x21021600,
 0x10dfdfde,
 0x2efe0060,
-0x21020c00,
+0x21021900,
 0x2f852980,
 0x1f089e9e,
 0x2effaf82,
-0xc90a9e35,
-0xd1029e6c,
-0x2e8a058a,
-0x2400005d,
-0x51d50a0c,
-0x51001d07,
-0x683d0a03,
-0x1f005d5d,
-0x21022600,
-0x51070a27,
-0x51190a26,
-0x21024100,
-0xc901eb07,
-0x104a4a3d,
-0x2400021d,
-0x21023c00,
-0x51001d25,
-0x2400011d,
-0x21024500,
-0x51070a1d,
-0x51190a1c,
-0x21024100,
-0x24000000,
-0x2e858995,
-0x2e858a02,
-0x11e30707,
-0x2f078a02,
-0x2e8a0012,
-0x672012ff,
-0x2e8a0f82,
-0x2f040f82,
-0x01207d7d,
-0x2e840f82,
-0x05207d7d,
-0x0120d6d6,
-0x1f001515,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0x79000078,
-0x240002ea,
-0x2f04008a,
-0x2400007d,
-0x21024500,
-0x79000073,
-0x24004901,
-0x81400901,
-0x1d089e9e,
-0x79000039,
 0x2e8a0682,
 0x10858580,
 0x2eff8a02,
@@ -651,14 +611,11 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x1d062b2b,
 0x122b3535,
 0x2e90040a,
-0xd1029e0d,
-0xc9059e02,
-0xd103350e,
-0xd1046a10,
+0xd1029e0a,
+0xd103350c,
 0xc9020c03,
-0xd1044a23,
-0xd1069e10,
-0xc9049e21,
+0xd1044a22,
+0xd1069e0f,
 0xd1009e1f,
 0xd1019e1c,
 0xc906351d,
@@ -666,35 +623,35 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x7900000d,
 0x24003f01,
 0x81400901,
-0x7900001a,
+0x79000050,
 0x24004001,
 0x81400901,
-0x79000017,
+0x7900004d,
 0x24004101,
 0x81400901,
-0x79000014,
+0x7900004a,
 0x24004201,
 0x81400901,
-0x79000011,
+0x79000047,
 0x24004301,
 0x81400901,
-0x7900000e,
+0x79000044,
 0x24004401,
 0x81400901,
-0x7900000b,
+0x79000041,
 0x24004501,
 0x81400901,
-0x79000008,
+0x7900003e,
 0x24004601,
 0x81400901,
-0x79000005,
+0x7900003b,
 0xd7002ef7,
 0xcf0635f9,
 0xcf012afb,
-0x79000003,
-0x1f000707,
-0x2f078007,
 0x2400068a,
+0xd114ff36,
+0x2e8a0012,
+0x672012fe,
 0x2e8a0f82,
 0x2f181082,
 0x2422b093,
@@ -714,15 +671,14 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x5893f204,
 0x24003301,
 0x81400901,
-0x79000009,
+0x79000008,
 0x1f007575,
 0x10e4e4f8,
 0x04e2e4f9,
 0x0b05f9f9,
 0x91206182,
 0x2400018a,
-0x2f18008a,
-0x2f180f82,
+0x2f181082,
 0x2e878582,
 0x57ff04ff,
 0x10040436,
@@ -741,28 +697,25 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x10f7f7ea,
 0x2f311282,
 0x0120f7f7,
-0x51014302,
+0x69014302,
 0x1f015555,
 0x10c3c3c5,
 0x10e4e4e6,
 0x2f0782c5,
+0x79000003,
+0x1f000707,
+0x2f078007,
 0x2efe0060,
 0x2f852980,
-0x2102b500,
+0x21028c00,
 0x2f852980,
-0xc9089e48,
-0xd1051547,
-0xd114fe20,
+0xc9089e35,
+0xd1051534,
+0xd114fe1a,
 0xd1001503,
 0x2e8a0f82,
 0x79000002,
 0x2e8a8f82,
-0xc90a9e06,
-0x61021d05,
-0x2f040f82,
-0x01207d7d,
-0x2e840f82,
-0x05207d7d,
 0x2400008b,
 0x10f8f8ea,
 0x2f319282,
@@ -772,36 +725,26 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x0120f7f7,
 0x0120d6d6,
 0x15011515,
-0xd114fe32,
+0xd114fe25,
 0x2e878a02,
-0xd1000730,
-0xc90fc32f,
-0xd101072e,
+0xd1000723,
+0xc90fc322,
+0xd1010721,
 0x1f010707,
 0x09010452,
 0x24015293,
 0x00935293,
 0x80931c83,
 0x2f078007,
-0x79000027,
+0x7900001a,
 0x24018893,
 0x1093ded3,
-0x5100d322,
-0x61021d09,
-0x2400001d,
-0x2f058995,
-0x51031d04,
-0x24004901,
-0x81400901,
-0x79000003,
-0x24004a01,
-0x81400901,
+0x5100d315,
 0x1f16ffff,
 0xc9035f02,
 0x1f17ffff,
 0x1f1febeb,
 0x2f0b006b,
-0x240000de,
 0x1f071515,
 0x2e878007,
 0x1f000707,
@@ -809,95 +752,61 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x24003801,
 0x81400901,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
 0x24002e01,
 0x2ec80061,
 0x2f480061,
 0x79000003,
-0x23036f93,
+0x23030f93,
 0x1f071515,
 0x2efe0060,
 0x2f852980,
-0x21030100,
+0x2102c500,
 0x2f852980,
-0xd1089e0f,
-0x61021d09,
-0x2400001d,
-0x2f058995,
-0x51031d04,
-0x24004901,
-0x81400901,
-0x79000003,
-0x24004a01,
-0x81400901,
+0xd1089e07,
 0x1f16ffff,
+0xc9035f02,
+0x1f17ffff,
 0x1f1febeb,
 0x2f0b006b,
-0x240000de,
-0x79000055,
-0xd1071525,
+0x7900003d,
+0xd1071518,
 0x24018893,
 0x1093ded3,
-0x5100d321,
-0x61021d09,
-0x2400001d,
-0x2f058995,
-0x51031d04,
-0x24004901,
-0x81400901,
-0x79000003,
-0x24004a01,
-0x81400901,
+0x5100d314,
 0x1f16ffff,
 0xc9035f02,
 0x1f17ffff,
 0x1f1febeb,
 0x2f0b006b,
-0x240000de,
 0x2e878007,
 0x1f000707,
 0x2f078007,
 0x24003801,
 0x81400901,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
 0x24002e01,
 0x2ec80061,
 0x2f480061,
-0x79000031,
-0x23036f93,
-0x1d071515,
+0x79000026,
+0x23030f93,
 0x2e878a02,
-0xd100072d,
-0xc900752c,
-0xc90a9e0d,
-0xc90ec302,
-0x1f067575,
-0xd1005d07,
-0xc90cc327,
-0xc90bc302,
-0x1f039e9e,
-0x1f027575,
-0xd1015d23,
-0x79000007,
-0xd1015d21,
-0xc9027520,
-0x79000004,
-0xc90cc31e,
-0xc90bc302,
-0x1f039e9e,
+0xd1000723,
+0xc9007522,
+0xc90cc321,
+0xc90bc306,
+0xd1015505,
+0x91383992,
+0x68d29203,
+0x01019292,
+0x81381992,
 0x090c85f4,
 0x12f4f9f9,
 0x2400038a,
@@ -915,8 +824,7 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x0104e8e8,
 0x48e8e902,
 0x10e6e6e8,
-0x2f18008a,
-0x2f180f82,
+0x2f181082,
 0x2400018a,
 0x2f18008a,
 0x2e980f82,
@@ -925,50 +833,29 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x2400008b,
 0x2f319282,
 0x01019c9c,
-0xc9015d04,
-0x24000000,
-0x2f058995,
-0x2f058a02,
 0x1f051515,
 0x1d089e9e,
 0x2efe0060,
 0x2f852980,
-0x21036e00,
+0x21030e00,
 0x2e8a0012,
-0xd100152b,
-0x69001216,
-0x2e8a058a,
-0x100b0b00,
+0xd100151a,
+0x6900120f,
 0x1f16ffff,
 0xc9035f02,
 0x1f17ffff,
 0x1f1febeb,
 0x2f0b006b,
-0x240000de,
-0xd3000076,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
 0x24002e01,
 0x2ec80061,
 0x2f480061,
-0x7b00006a,
-0x2e8a1582,
-0xc90a9e0a,
-0x51001d09,
-0x51011d07,
-0xc900eb04,
-0x2400031d,
-0x1f015d5d,
-0x21048b00,
-0x2400001d,
-0x79000081,
-0x2400031d,
+0x79000062,
+0x2e8a0f82,
 0x2400008b,
 0x10f8f8ea,
 0x2f319282,
@@ -977,40 +864,23 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x2f311282,
 0x0120f7f7,
 0x2e8a8f82,
-0x7900002a,
-0x69201216,
-0x2e8a058a,
-0x100b0b00,
+0x79000019,
+0x6920120f,
 0x1f16ffff,
 0xc9035f02,
 0x1f17ffff,
 0x1f1febeb,
 0x2f0b006b,
-0x240000de,
-0xd300004c,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
 0x24002e01,
 0x2ec80061,
 0x2f480061,
-0x7b000040,
-0x2e8a9582,
-0xc90a9e0a,
-0x51001d09,
-0x51011d07,
-0xc900eb04,
-0x2400031d,
-0x1f015d5d,
-0x21048b00,
-0x2400001d,
-0x79000057,
-0x2400031d,
+0x79000049,
+0x2e8a8f82,
 0x2400008b,
 0x10f8f8ea,
 0x2f319282,
@@ -1024,54 +894,44 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x1f17ffff,
 0x1f1febeb,
 0x2f0b006b,
-0x240000de,
-0xc9001512,
-0x6900120e,
+0xc900150f,
+0x6900120b,
 0x0120d6d6,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
 0x24002e01,
 0x2ec80061,
 0x2f480061,
-0x7b000018,
-0x61201220,
+0x7900002f,
+0x6120121a,
 0x05201220,
-0x79000011,
-0x6920120e,
+0x7900000e,
+0x6920120b,
 0x0120d6d6,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
 0x24002e01,
 0x2ec80061,
 0x2f480061,
-0x7b000007,
-0x4920120f,
+0x79000021,
+0x4920120c,
 0x10121220,
 0x0020d6d6,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
 0x24002e01,
 0x2ec80061,
 0x2f480061,
-0x790000f8,
+0x79000015,
 0x0120d6d6,
 0x05201220,
 0xc9001502,
@@ -1085,237 +945,10 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x2f311282,
 0x0120f7f7,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
-0x24002e01,
-0x2ec80061,
-0x2f480061,
-0x790000e0,
-0x24004c01,
-0x81400901,
-0xd1001510,
-0x7120121e,
-0x2f040f82,
-0x01207d7d,
-0x2e840f82,
-0x05207d7d,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0x0120d6d6,
-0x2e8a9582,
-0x79000020,
-0x4920121f,
-0x51001216,
-0x2f040f82,
-0x01207d7d,
-0x2e840f82,
-0x05207d7d,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0x0120d6d6,
-0x2e8a1582,
-0x1f16ffff,
-0xc9035f02,
-0x1f17ffff,
-0x1f1febeb,
-0x2f0b006b,
-0x240000de,
-0x10121220,
-0x79000010,
-0x1f16ffff,
-0xc9035f02,
-0x1f17ffff,
-0x1f1febeb,
-0x2f0b006b,
-0x240000de,
-0x24002020,
-0x79000008,
-0x1f16ffff,
-0xc9035f02,
-0x1f17ffff,
-0x1f1febeb,
-0x2f0b006b,
-0x240000de,
-0x05201220,
-0x51002004,
-0x10202000,
-0x2f043e02,
-0x00007d7d,
-0x71207d0b,
-0x2e840f82,
-0x05207d7d,
-0x0120d6d6,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0x51007d0b,
-0x007dd6d6,
-0x2e840f82,
-0x05207d7d,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0xd1005d0d,
-0x2e878a02,
-0x111c5d01,
-0x12010707,
-0x10d6d685,
-0x10f7f7e2,
-0x2f078182,
-0x2f078405,
-0x2f078007,
-0x24002e01,
-0x2ec80061,
-0x2f480061,
-0x79000081,
-0xc906750e,
-0x1f025d5d,
-0x2e878a02,
-0x111c5d01,
-0x12010707,
-0x10d6d685,
-0x10f7f7e2,
-0x2f078182,
-0x2f078405,
-0x2f078007,
-0x24002e01,
-0x2ec80061,
-0x2f480061,
-0x79000073,
-0x1f045d5d,
-0x2e878a02,
-0x111c5d01,
-0x12010707,
-0x10d6d685,
-0x10f7f7e2,
-0x2f078182,
-0x2f078405,
-0x2f078007,
-0x24002e01,
-0x2ec80061,
-0x2f480061,
-0x79000066,
-0x24004d01,
-0x81400901,
-0xd1001510,
-0x7120121e,
-0x2f040f82,
-0x01207d7d,
-0x2e840f82,
-0x05207d7d,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0x0120d6d6,
-0x2e8a9582,
-0x79000020,
-0x4920121f,
-0x51001216,
-0x2f040f82,
-0x01207d7d,
-0x2e840f82,
-0x05207d7d,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0x0120d6d6,
-0x2e8a1582,
-0x1f16ffff,
-0xc9035f02,
-0x1f17ffff,
-0x1f1febeb,
-0x2f0b006b,
-0x240000de,
-0x10121220,
-0x79000010,
-0x1f16ffff,
-0xc9035f02,
-0x1f17ffff,
-0x1f1febeb,
-0x2f0b006b,
-0x240000de,
-0x24002020,
-0x79000008,
-0x1f16ffff,
-0xc9035f02,
-0x1f17ffff,
-0x1f1febeb,
-0x2f0b006b,
-0x240000de,
-0x05201220,
-0x51002004,
-0x10202000,
-0x2f043e02,
-0x00007d7d,
-0x240001ea,
-0x2f04008a,
-0x05047d7d,
-0x71207d0b,
-0x2e840f82,
-0x05207d7d,
-0x0120d6d6,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0xc9005d0e,
-0x1f045d5d,
-0x2e878a02,
-0x111c5d01,
-0x12010707,
-0x10d6d685,
-0x10f7f7e2,
-0x2f078182,
-0x2f078405,
-0x2f078007,
-0x24002e01,
-0x2ec80061,
-0x2f480061,
-0x7900000e,
-0x1f045d5d,
-0x1f035d5d,
-0x2e878a02,
-0x111c5d01,
-0x12010707,
-0x10d6d685,
-0x10f7f7e2,
-0x2f078182,
-0x2f078405,
-0x2f078007,
 0x24002e01,
 0x2ec80061,
 0x2f480061,
@@ -1335,7 +968,7 @@ const unsigned int RX_PRU_SLICE0_b00[]= {
 0x01080101,
 0x79000004,
 0xc9076902,
-0xc9036306,
+0xc9036906,
 0x01080101,
 0x2c82ed01,
 0x01040101,

diff --git a/firmware/icss_switch/bin/RX_PRU_SLICE1_bin.h b/firmware/icss_switch/bin/RX_PRU_SLICE1_bin.h
index dd1e18f37fc5eefab3640ddcd9088f86dc225ba1..79762c2ee561fed70b6cc06191a836838032b9ec 100644 (file)
--- a/firmware/icss_switch/bin/RX_PRU_SLICE1_bin.h
+++ b/firmware/icss_switch/bin/RX_PRU_SLICE1_bin.h
@@ -63,21 +63,21 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0xe1003293,
 0x240002d2,
 0x24a00092,
-0x240208f3,
-0x240302f4,
-0x2402b6f5,
+0x240215f3,
+0x2402c6f4,
+0x24028df5,
 0xe108b293,
-0x24020df3,
-0x240208f4,
+0x24021af3,
+0x240215f4,
 0xe1147293,
 0x240002d2,
 0x24a00092,
-0x240208f3,
-0x24020af4,
-0x240208f5,
+0x240215f3,
+0x240217f4,
+0x240215f5,
 0xe11cb293,
-0x240208f3,
-0x240208f4,
+0x240215f3,
+0x240215f4,
 0xe1287293,
 0x240002d2,
 0x24a00092,
@@ -186,15 +186,15 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x10000000,
 0x2f0f0f82,
 0x01018a8a,
+0x91702180,
+0x1f04e0e0,
+0x81702180,
 0x2effbb80,
-0x910c1952,
-0x51005202,
-0x1f0a9e9e,
 0x91383992,
 0x50d2920c,
 0x9114dc8d,
 0x108f8fce,
-0x2304f193,
+0x23038293,
 0x0101d2d2,
 0x813a19d2,
 0x91403992,
@@ -207,43 +207,51 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x50d29207,
 0x9144d98d,
 0x108f8fce,
-0x2304f193,
+0x23038293,
 0x0101d2d2,
 0x813e19d2,
 0x813e12d2,
 0x91740152,
-0xc9035220,
+0xc9035228,
 0x24000852,
 0x81740152,
 0x91106182,
-0x240098c4,
-0x24968084,
+0x91687984,
 0x00e4e2e2,
 0x0300e3e3,
+0x00e5e3e3,
 0x81906182,
 0x91241c8a,
 0x2f0f008a,
 0x10000000,
 0x10000000,
 0x2e8f0f82,
-0xc9036303,
-0xd1066302,
+0xc9036305,
+0xc9066303,
+0x1d066363,
+0x79000002,
 0x2eff8382,
-0xc9036503,
-0xd1066502,
+0xc9036505,
+0xc9066503,
+0x1d066565,
+0x79000002,
 0x2eff8384,
-0xc9036703,
-0xd1066702,
+0xc9036705,
+0xc9066703,
+0x1d066767,
+0x79000002,
 0x2eff8386,
-0xc9036903,
-0xd1066902,
+0xc9036905,
+0xc9066903,
+0x1d066969,
+0x79000002,
 0x2eff8388,
+0x2f0f1082,
 0x01018a8a,
 0x24020093,
 0x68938a02,
 0x2400008a,
 0x81241c8a,
-0x2f0f1082,
 0x91781c80,
 0xc90000a0,
 0x6900209f,
@@ -415,7 +423,7 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x51075c67,
 0x51085c74,
 0x7900007f,
-0x51009c9f,
+0x51009ca4,
 0x2400028a,
 0x32000000,
 0x2f18008a,
@@ -438,7 +446,7 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x2eb00012,
 0xc903f203,
 0x2400015c,
-0x79000088,
+0x7900008d,
 0x2eb00f82,
 0x81407c82,
 0x0120fafa,
@@ -448,7 +456,7 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x2ea80381,
 0xd100e203,
 0x2400025c,
-0x7900007d,
+0x79000082,
 0x10040412,
 0x2400008a,
 0x32000000,
@@ -459,8 +467,8 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x00128282,
 0x81103992,
 0x2f288981,
-0x049bdbd1,
-0x7120d128,
+0x049bdbde,
+0x7120de28,
 0x10fafaf3,
 0x24000094,
 0x24000492,
@@ -469,12 +477,12 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x2eb00012,
 0xc903f203,
 0x2400035c,
-0x79000069,
+0x7900006e,
 0x2400005c,
 0x2ea80381,
 0xd100e203,
 0x2400045c,
-0x79000064,
+0x79000069,
 0x2eb00f82,
 0x69818507,
 0x91101912,
@@ -492,7 +500,7 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x2ea80381,
 0xd100e203,
 0x2400055c,
-0x79000051,
+0x79000056,
 0x241014c1,
 0x24000081,
 0x2ed08f82,
@@ -508,11 +516,11 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x2eb00012,
 0xc903f203,
 0x2400065c,
-0x79000042,
+0x79000047,
 0x2eb00f82,
 0x0120fafa,
-0x00d19b9b,
-0x7110d10f,
+0x00de9b9b,
+0x7110de0f,
 0x10e2e2ea,
 0x79000002,
 0x95143982,
@@ -520,12 +528,12 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x2ea80381,
 0xd100e203,
 0x2400075c,
-0x79000035,
+0x7900003a,
 0x10eaeae2,
 0x241014c1,
 0x24000081,
 0x2f288981,
-0x0510d1d1,
+0x0510dede,
 0x2ed08f82,
 0x10e2e2ea,
 0x79000002,
@@ -534,18 +542,18 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x2ea80381,
 0xd100e203,
 0x2400085c,
-0x79000027,
+0x7900002c,
 0x10eaeae2,
 0x240014c1,
 0x24001081,
-0x10d1d161,
-0x0104d140,
+0x10dede61,
+0x0104de40,
 0x2f28bf01,
 0x2400005c,
 0x2ea80381,
 0xd100e203,
 0x2400095c,
-0x7900001d,
+0x79000022,
 0x240f18c1,
 0x24001281,
 0x91407c82,
@@ -565,6 +573,11 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x05019c9c,
 0x24002001,
 0x81400901,
+0x10dbdbf2,
+0x090ef2f2,
+0x24008072,
+0x24000012,
+0x81802592,
 0x0104e7e7,
 0x68e7e902,
 0x10e6e6e7,
@@ -574,68 +587,15 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x32800000,
 0x79000002,
 0x85143982,
-0x7d00007d,
+0x7d000073,
 0x2efe0060,
-0x21020900,
+0x21021600,
 0x10dfdfde,
 0x2efe0060,
-0x21020c00,
+0x21021900,
 0x2f852980,
 0x1f089e9e,
 0x2effaf82,
-0xc90a9e35,
-0xd1029e6c,
-0x2e8a058a,
-0x2400005d,
-0x51d50a0c,
-0x51001d07,
-0x683d0a03,
-0x1f005d5d,
-0x21022600,
-0x51070a27,
-0x51190a26,
-0x21024100,
-0xc901eb07,
-0x104a4a3d,
-0x2400021d,
-0x21023c00,
-0x51001d25,
-0x2400011d,
-0x21024500,
-0x51070a1d,
-0x51190a1c,
-0x21024100,
-0x24000000,
-0x2e858995,
-0x2e858a02,
-0x11e30707,
-0x2f078a02,
-0x2e8a0012,
-0x672012ff,
-0x2e8a0f82,
-0x2f040f82,
-0x01207d7d,
-0x2e840f82,
-0x05207d7d,
-0x0120d6d6,
-0x1f001515,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0x79000078,
-0x240002ea,
-0x2f04008a,
-0x2400007d,
-0x21024500,
-0x79000073,
-0x24004901,
-0x81400901,
-0x1d089e9e,
-0x79000039,
 0x2e8a0682,
 0x10858580,
 0x2eff8a02,
@@ -651,14 +611,11 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x1d062b2b,
 0x122b3535,
 0x2e90040a,
-0xd1029e0d,
-0xc9059e02,
-0xd103350e,
-0xd1046a10,
+0xd1029e0a,
+0xd103350c,
 0xc9020c03,
-0xd1044a23,
-0xd1069e10,
-0xc9049e21,
+0xd1044a22,
+0xd1069e0f,
 0xd1009e1f,
 0xd1019e1c,
 0xc906351d,
@@ -666,35 +623,35 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x7900000d,
 0x24003f01,
 0x81400901,
-0x7900001a,
+0x79000050,
 0x24004001,
 0x81400901,
-0x79000017,
+0x7900004d,
 0x24004101,
 0x81400901,
-0x79000014,
+0x7900004a,
 0x24004201,
 0x81400901,
-0x79000011,
+0x79000047,
 0x24004301,
 0x81400901,
-0x7900000e,
+0x79000044,
 0x24004401,
 0x81400901,
-0x7900000b,
+0x79000041,
 0x24004501,
 0x81400901,
-0x79000008,
+0x7900003e,
 0x24004601,
 0x81400901,
-0x79000005,
+0x7900003b,
 0xd7002ef7,
 0xcf0635f9,
 0xcf022afb,
-0x79000003,
-0x1f000707,
-0x2f078007,
 0x2400068a,
+0xd114ff36,
+0x2e8a0012,
+0x672012fe,
 0x2e8a0f82,
 0x2f181082,
 0x2422b093,
@@ -714,15 +671,14 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x5893f204,
 0x24003301,
 0x81400901,
-0x79000009,
+0x79000008,
 0x1f007575,
 0x10e4e4f8,
 0x04e2e4f9,
 0x0b05f9f9,
 0x91206182,
 0x2400018a,
-0x2f18008a,
-0x2f180f82,
+0x2f181082,
 0x2e878582,
 0x57ff04ff,
 0x10040436,
@@ -741,28 +697,25 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x10f7f7ea,
 0x2f311282,
 0x0120f7f7,
-0x51014302,
+0x69014302,
 0x1f015555,
 0x10c3c3c5,
 0x10e4e4e6,
 0x2f0782c5,
+0x79000003,
+0x1f000707,
+0x2f078007,
 0x2efe0060,
 0x2f852980,
-0x2102b500,
+0x21028c00,
 0x2f852980,
-0xc9089e48,
-0xd1051547,
-0xd114fe20,
+0xc9089e35,
+0xd1051534,
+0xd114fe1a,
 0xd1001503,
 0x2e8a0f82,
 0x79000002,
 0x2e8a8f82,
-0xc90a9e06,
-0x61021d05,
-0x2f040f82,
-0x01207d7d,
-0x2e840f82,
-0x05207d7d,
 0x2400008b,
 0x10f8f8ea,
 0x2f319282,
@@ -772,36 +725,26 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x0120f7f7,
 0x0120d6d6,
 0x15011515,
-0xd114fe32,
+0xd114fe25,
 0x2e878a02,
-0xd1000730,
-0xc90fc32f,
-0xd101072e,
+0xd1000723,
+0xc90fc322,
+0xd1010721,
 0x1f010707,
 0x09010452,
 0x24015293,
 0x00935293,
 0x80931c83,
 0x2f078007,
-0x79000027,
+0x7900001a,
 0x24018893,
 0x1093ded3,
-0x5100d322,
-0x61021d09,
-0x2400001d,
-0x2f058995,
-0x51031d04,
-0x24004901,
-0x81400901,
-0x79000003,
-0x24004a01,
-0x81400901,
+0x5100d315,
 0x1f16ffff,
 0xc9035f02,
 0x1f17ffff,
 0x1f1febeb,
 0x2f0b006b,
-0x240000de,
 0x1f071515,
 0x2e878007,
 0x1f000707,
@@ -809,95 +752,61 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x24003801,
 0x81400901,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
 0x24002f01,
 0x2ec80061,
 0x2f480061,
 0x79000003,
-0x23036f93,
+0x23030f93,
 0x1f071515,
 0x2efe0060,
 0x2f852980,
-0x21030100,
+0x2102c500,
 0x2f852980,
-0xd1089e0f,
-0x61021d09,
-0x2400001d,
-0x2f058995,
-0x51031d04,
-0x24004901,
-0x81400901,
-0x79000003,
-0x24004a01,
-0x81400901,
+0xd1089e07,
 0x1f16ffff,
+0xc9035f02,
+0x1f17ffff,
 0x1f1febeb,
 0x2f0b006b,
-0x240000de,
-0x79000055,
-0xd1071525,
+0x7900003d,
+0xd1071518,
 0x24018893,
 0x1093ded3,
-0x5100d321,
-0x61021d09,
-0x2400001d,
-0x2f058995,
-0x51031d04,
-0x24004901,
-0x81400901,
-0x79000003,
-0x24004a01,
-0x81400901,
+0x5100d314,
 0x1f16ffff,
 0xc9035f02,
 0x1f17ffff,
 0x1f1febeb,
 0x2f0b006b,
-0x240000de,
 0x2e878007,
 0x1f000707,
 0x2f078007,
 0x24003801,
 0x81400901,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
 0x24002f01,
 0x2ec80061,
 0x2f480061,
-0x79000031,
-0x23036f93,
-0x1d071515,
+0x79000026,
+0x23030f93,
 0x2e878a02,
-0xd100072d,
-0xc900752c,
-0xc90a9e0d,
-0xc90ec302,
-0x1f067575,
-0xd1005d07,
-0xc90cc327,
-0xc90bc302,
-0x1f039e9e,
-0x1f027575,
-0xd1015d23,
-0x79000007,
-0xd1015d21,
-0xc9027520,
-0x79000004,
-0xc90cc31e,
-0xc90bc302,
-0x1f039e9e,
+0xd1000723,
+0xc9007522,
+0xc90cc321,
+0xc90bc306,
+0xd1015505,
+0x91383992,
+0x68d29203,
+0x01019292,
+0x81381992,
 0x090c85f4,
 0x12f4f9f9,
 0x2400038a,
@@ -915,8 +824,7 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x0104e8e8,
 0x48e8e902,
 0x10e6e6e8,
-0x2f18008a,
-0x2f180f82,
+0x2f181082,
 0x2400018a,
 0x2f18008a,
 0x2e980f82,
@@ -925,50 +833,29 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x2400008b,
 0x2f319282,
 0x01019c9c,
-0xc9015d04,
-0x24000000,
-0x2f058995,
-0x2f058a02,
 0x1f051515,
 0x1d089e9e,
 0x2efe0060,
 0x2f852980,
-0x21036e00,
+0x21030e00,
 0x2e8a0012,
-0xd100152b,
-0x69001216,
-0x2e8a058a,
-0x100b0b00,
+0xd100151a,
+0x6900120f,
 0x1f16ffff,
 0xc9035f02,
 0x1f17ffff,
 0x1f1febeb,
 0x2f0b006b,
-0x240000de,
-0xd3000076,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
 0x24002f01,
 0x2ec80061,
 0x2f480061,
-0x7b00006a,
-0x2e8a1582,
-0xc90a9e0a,
-0x51001d09,
-0x51011d07,
-0xc900eb04,
-0x2400031d,
-0x1f015d5d,
-0x21048b00,
-0x2400001d,
-0x79000081,
-0x2400031d,
+0x79000062,
+0x2e8a0f82,
 0x2400008b,
 0x10f8f8ea,
 0x2f319282,
@@ -977,40 +864,23 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x2f311282,
 0x0120f7f7,
 0x2e8a8f82,
-0x7900002a,
-0x69201216,
-0x2e8a058a,
-0x100b0b00,
+0x79000019,
+0x6920120f,
 0x1f16ffff,
 0xc9035f02,
 0x1f17ffff,
 0x1f1febeb,
 0x2f0b006b,
-0x240000de,
-0xd300004c,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
 0x24002f01,
 0x2ec80061,
 0x2f480061,
-0x7b000040,
-0x2e8a9582,
-0xc90a9e0a,
-0x51001d09,
-0x51011d07,
-0xc900eb04,
-0x2400031d,
-0x1f015d5d,
-0x21048b00,
-0x2400001d,
-0x79000057,
-0x2400031d,
+0x79000049,
+0x2e8a8f82,
 0x2400008b,
 0x10f8f8ea,
 0x2f319282,
@@ -1024,54 +894,44 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x1f17ffff,
 0x1f1febeb,
 0x2f0b006b,
-0x240000de,
-0xc9001512,
-0x6900120e,
+0xc900150f,
+0x6900120b,
 0x0120d6d6,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
 0x24002f01,
 0x2ec80061,
 0x2f480061,
-0x7b000018,
-0x61201220,
+0x7900002f,
+0x6120121a,
 0x05201220,
-0x79000011,
-0x6920120e,
+0x7900000e,
+0x6920120b,
 0x0120d6d6,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
 0x24002f01,
 0x2ec80061,
 0x2f480061,
-0x7b000007,
-0x4920120f,
+0x79000021,
+0x4920120c,
 0x10121220,
 0x0020d6d6,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
 0x24002f01,
 0x2ec80061,
 0x2f480061,
-0x790000f8,
+0x79000015,
 0x0120d6d6,
 0x05201220,
 0xc9001502,
@@ -1085,237 +945,10 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x2f311282,
 0x0120f7f7,
 0x2e878a02,
-0x111c5d01,
-0x12010707,
 0x10d6d685,
 0x10f7f7e2,
 0x2f078182,
 0x2f078405,
-0x2f078007,
-0x24002f01,
-0x2ec80061,
-0x2f480061,
-0x790000e0,
-0x24004c01,
-0x81400901,
-0xd1001510,
-0x7120121e,
-0x2f040f82,
-0x01207d7d,
-0x2e840f82,
-0x05207d7d,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0x0120d6d6,
-0x2e8a9582,
-0x79000020,
-0x4920121f,
-0x51001216,
-0x2f040f82,
-0x01207d7d,
-0x2e840f82,
-0x05207d7d,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0x0120d6d6,
-0x2e8a1582,
-0x1f16ffff,
-0xc9035f02,
-0x1f17ffff,
-0x1f1febeb,
-0x2f0b006b,
-0x240000de,
-0x10121220,
-0x79000010,
-0x1f16ffff,
-0xc9035f02,
-0x1f17ffff,
-0x1f1febeb,
-0x2f0b006b,
-0x240000de,
-0x24002020,
-0x79000008,
-0x1f16ffff,
-0xc9035f02,
-0x1f17ffff,
-0x1f1febeb,
-0x2f0b006b,
-0x240000de,
-0x05201220,
-0x51002004,
-0x10202000,
-0x2f043e02,
-0x00007d7d,
-0x71207d0b,
-0x2e840f82,
-0x05207d7d,
-0x0120d6d6,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0x51007d0b,
-0x007dd6d6,
-0x2e840f82,
-0x05207d7d,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0xd1005d0d,
-0x2e878a02,
-0x111c5d01,
-0x12010707,
-0x10d6d685,
-0x10f7f7e2,
-0x2f078182,
-0x2f078405,
-0x2f078007,
-0x24002f01,
-0x2ec80061,
-0x2f480061,
-0x79000081,
-0xc906750e,
-0x1f025d5d,
-0x2e878a02,
-0x111c5d01,
-0x12010707,
-0x10d6d685,
-0x10f7f7e2,
-0x2f078182,
-0x2f078405,
-0x2f078007,
-0x24002f01,
-0x2ec80061,
-0x2f480061,
-0x79000073,
-0x1f045d5d,
-0x2e878a02,
-0x111c5d01,
-0x12010707,
-0x10d6d685,
-0x10f7f7e2,
-0x2f078182,
-0x2f078405,
-0x2f078007,
-0x24002f01,
-0x2ec80061,
-0x2f480061,
-0x79000066,
-0x24004d01,
-0x81400901,
-0xd1001510,
-0x7120121e,
-0x2f040f82,
-0x01207d7d,
-0x2e840f82,
-0x05207d7d,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0x0120d6d6,
-0x2e8a9582,
-0x79000020,
-0x4920121f,
-0x51001216,
-0x2f040f82,
-0x01207d7d,
-0x2e840f82,
-0x05207d7d,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0x0120d6d6,
-0x2e8a1582,
-0x1f16ffff,
-0xc9035f02,
-0x1f17ffff,
-0x1f1febeb,
-0x2f0b006b,
-0x240000de,
-0x10121220,
-0x79000010,
-0x1f16ffff,
-0xc9035f02,
-0x1f17ffff,
-0x1f1febeb,
-0x2f0b006b,
-0x240000de,
-0x24002020,
-0x79000008,
-0x1f16ffff,
-0xc9035f02,
-0x1f17ffff,
-0x1f1febeb,
-0x2f0b006b,
-0x240000de,
-0x05201220,
-0x51002004,
-0x10202000,
-0x2f043e02,
-0x00007d7d,
-0x240001ea,
-0x2f04008a,
-0x05047d7d,
-0x71207d0b,
-0x2e840f82,
-0x05207d7d,
-0x0120d6d6,
-0x2400008b,
-0x10f8f8ea,
-0x2f319282,
-0x0120f8f8,
-0x10f7f7ea,
-0x2f311282,
-0x0120f7f7,
-0xc9005d0e,
-0x1f045d5d,
-0x2e878a02,
-0x111c5d01,
-0x12010707,
-0x10d6d685,
-0x10f7f7e2,
-0x2f078182,
-0x2f078405,
-0x2f078007,
-0x24002f01,
-0x2ec80061,
-0x2f480061,
-0x7900000e,
-0x1f045d5d,
-0x1f035d5d,
-0x2e878a02,
-0x111c5d01,
-0x12010707,
-0x10d6d685,
-0x10f7f7e2,
-0x2f078182,
-0x2f078405,
-0x2f078007,
 0x24002f01,
 0x2ec80061,
 0x2f480061,
@@ -1335,7 +968,7 @@ const unsigned int RX_PRU_SLICE1_b00[]= {
 0x01080101,
 0x79000004,
 0xc9076902,
-0xc9036306,
+0xc9036906,
 0x01080101,
 0x2c82ed01,
 0x01040101,

diff --git a/firmware/icss_switch/bin/TX_PRU_SLICE0_bin.h b/firmware/icss_switch/bin/TX_PRU_SLICE0_bin.h
index 9d90c910077211abc8ac1e9df3dbc87e407b08b4..671eea5d772b817463ac0263eedafa9e15458922 100644 (file)
--- a/firmware/icss_switch/bin/TX_PRU_SLICE0_bin.h
+++ b/firmware/icss_switch/bin/TX_PRU_SLICE0_bin.h
@@ -66,21 +66,21 @@ const unsigned int TX_PRU_SLICE0_b00[]= {
 0xe1002283,
 0x240002c2,
 0x24a20082,
-0x24015fe3,
-0x24015fe4,
-0x24015fe5,
+0x240145e3,
+0x240145e4,
+0x240145e5,
 0xe108a283,
-0x24015fe3,
-0x24015fe4,
+0x240145e3,
+0x240145e4,
 0xe1146283,
 0x240002c2,
 0x24a20082,
-0x24015fe3,
-0x240161e4,
-0x24015fe5,
+0x240145e3,
+0x240147e4,
+0x240145e5,
 0xe11ca283,
-0x24015fe3,
-0x2401b2e4,
+0x240145e3,
+0x240194e4,
 0xe1286283,
 0x240002c2,
 0x24a20082,
@@ -163,19 +163,16 @@ const unsigned int TX_PRU_SLICE0_b00[]= {
 0x0510d3d3,
 0x5f118af9,
 0x1f089e9e,
-0x910c1852,
-0x51005202,
-0x1f0e9e9e,
-0xd10b9e99,
+0xd10b9e8e,
 0xc9002c09,
-0xc9074c97,
+0xc9074c8c,
 0x90f03c94,
-0xd1077495,
+0xd107748a,
 0x0b0cf48d,
 0x240fff93,
 0x10938d8d,
 0x1d074c4c,
-0x79000090,
+0x79000085,
 0xc9029e11,
 0x1d029e9e,
 0x2400218a,
@@ -196,28 +193,20 @@ const unsigned int TX_PRU_SLICE0_b00[]= {
 0x2eff858c,
 0x2e878187,
 0xd1019e06,
-0x5100870c,
+0x510087ab,
 0x2701870c,
 0xc9000c07,
 0x1f032c2c,
 0x79000005,
-0x5100c707,
+0x5100c7a6,
 0x2701c70c,
 0xd1000c02,
 0x1f032c2c,
 0x0b010c0c,
-0xc90e9e0c,
-0x79000004,
-0xc90e9eb7,
-0xc9009eb6,
-0x79000005,
-0x51070c07,
-0xd1009e03,
-0x1f012c2c,
-0x79000004,
+0xc9009e04,
 0x1d009e9e,
-0x2e85858c,
-0x79000023,
+0x91005c8c,
+0x7900001f,
 0x09020c94,
 0xd1032c05,
 0x01190c8f,
@@ -236,33 +225,33 @@ const unsigned int TX_PRU_SLICE0_b00[]= {
 0x32800000,
 0x90e73c94,
 0x10e7e7f0,
-0x0104e7e7,
-0x48e7e902,
-0x10e6e6e7,
-0x80911c87,
-0x24000601,
-0x2ec80061,
-0x2f480061,
+0x0104e7d1,
+0x48d1e902,
+0x10e6e6d1,
 0x0b18f44c,
 0x240fff93,
 0x0b0cf48d,
 0x10938d8d,
-0x51008d45,
+0x51008d46,
 0x1093f4ee,
 0x0905eeee,
 0x00e2eeee,
-0xd1089e56,
+0xd1089e46,
 0x10eeeef3,
 0x24000094,
 0x24000492,
 0x32000000,
+0x2eb00002,
 0x2f300492,
 0x32800000,
 0xd1074c01,
+0x80911cd1,
+0x24000601,
+0x2ec80061,
+0x2f480061,
 0x2eb00012,
 0xd703f2ff,
 0x2eb00f82,
-0x1f002c2c,
 0x11054c12,
 0x24003493,
 0xc9032c02,
@@ -293,17 +282,14 @@ const unsigned int TX_PRU_SLICE0_b00[]= {
 0x12525555,
 0x240c1493,
 0x80932995,
-0xc9012c03,
-0x1f051212,
-0x79000002,
-0x1f041212,
 0x24004094,
 0xc9001202,
-0x24000894,
+0x24000194,
 0x916c1b96,
 0x4e9496ff,
 0x2f140012,
 0x2f140f82,
+0x1f002c2c,
 0x0120cdcd,
 0x0120eeee,
 0x10eeeef3,
@@ -319,24 +305,11 @@ const unsigned int TX_PRU_SLICE0_b00[]= {
 0x2eff858c,
 0x24003601,
 0x81480901,
-0xc90e9e11,
-0xc9012c10,
-0x2e878187,
-0xd1019e04,
-0x5100870d,
-0x27018700,
-0x79000003,
-0x5100c70a,
-0x2701c700,
-0x0b010000,
-0x69070007,
-0x6120cd06,
-0x04cd8d80,
-0x61608004,
-0x1f022c2c,
-0x24004b01,
-0x81480901,
-0x7900003a,
+0x7900003f,
+0x80911cd1,
+0x24000601,
+0x2ec80061,
+0x2f480061,
 0x24ffe0d3,
 0x10d38d93,
 0x0093eeee,
@@ -390,7 +363,8 @@ const unsigned int TX_PRU_SLICE0_b00[]= {
 0x2f288981,
 0x24003d01,
 0x81480901,
-0x79000004,
+0x79000005,
+0x2eff858c,
 0x24000601,
 0x2ec80061,
 0x2f480061,
@@ -405,25 +379,21 @@ const unsigned int TX_PRU_SLICE0_b00[]= {
 0x79000002,
 0x1f042020,
 0x817a1c80,
-0x7f00000e,
+0x7f000028,
 0x2efe0060,
-0x21016000,
+0x21014600,
 0x2f861780,
 0x2f861792,
-0xc9002c4b,
-0xc9022c0f,
-0x2eb00012,
-0xd703f2ff,
-0x2eb00f82,
-0x2f143e82,
-0x0120cdcd,
-0x0120eeee,
+0xc9002c47,
+0x2e940193,
+0x117f5353,
+0x49015344,
+0xc9022c08,
 0x24008012,
 0x2f140012,
 0x242c00df,
 0x1f009e9e,
-0x1d022c2c,
-0x2f05858c,
+0x81005c8c,
 0x2eff858c,
 0x7900003c,
 0x6920cd04,
@@ -488,7 +458,7 @@ const unsigned int TX_PRU_SLICE0_b00[]= {
 0x2f861792,
 0x2f861780,
 0x2efe0060,
-0x2101b100,
+0x21019300,
 0x2f063b80,
 0x91543992,
 0x4902f20e,
@@ -509,4 +479,4 @@ const unsigned int TX_PRU_SLICE0_b00[]= {
 0x81543992,
 0x2efe0060,
 0x2e863b80,
-0x2101c600 };
+0x2101a800 };

diff --git a/firmware/icss_switch/bin/TX_PRU_SLICE1_bin.h b/firmware/icss_switch/bin/TX_PRU_SLICE1_bin.h
index 563154fba949d52ca0a7f10855b0f504d0bb3f08..17b9ca44341b62f7796684ac222f11ba28e0faea 100644 (file)
--- a/firmware/icss_switch/bin/TX_PRU_SLICE1_bin.h
+++ b/firmware/icss_switch/bin/TX_PRU_SLICE1_bin.h
@@ -66,21 +66,21 @@ const unsigned int TX_PRU_SLICE1_b00[]= {
 0xe1002283,
 0x240002c2,
 0x24a20082,
-0x24015fe3,
-0x24015fe4,
-0x24015fe5,
+0x240145e3,
+0x240145e4,
+0x240145e5,
 0xe108a283,
-0x24015fe3,
-0x24015fe4,
+0x240145e3,
+0x240145e4,
 0xe1146283,
 0x240002c2,
 0x24a20082,
-0x24015fe3,
-0x240161e4,
-0x24015fe5,
+0x240145e3,
+0x240147e4,
+0x240145e5,
 0xe11ca283,
-0x24015fe3,
-0x2401b2e4,
+0x240145e3,
+0x240194e4,
 0xe1286283,
 0x240002c2,
 0x24a20082,
@@ -163,19 +163,16 @@ const unsigned int TX_PRU_SLICE1_b00[]= {
 0x0510d3d3,
 0x5f118af9,
 0x1f089e9e,
-0x910c1852,
-0x51005202,
-0x1f0e9e9e,
-0xd10b9e99,
+0xd10b9e8e,
 0xc9002c09,
-0xc9074c97,
+0xc9074c8c,
 0x90f03c94,
-0xd1077495,
+0xd107748a,
 0x0b0cf48d,
 0x240fff93,
 0x10938d8d,
 0x1d074c4c,
-0x79000090,
+0x79000085,
 0xc9029e11,
 0x1d029e9e,
 0x2400218a,
@@ -196,28 +193,20 @@ const unsigned int TX_PRU_SLICE1_b00[]= {
 0x2eff858c,
 0x2e878187,
 0xd1019e06,
-0x5100870c,
+0x510087ab,
 0x2701870c,
 0xc9000c07,
 0x1f032c2c,
 0x79000005,
-0x5100c707,
+0x5100c7a6,
 0x2701c70c,
 0xd1000c02,
 0x1f032c2c,
 0x0b010c0c,
-0xc90e9e0c,
-0x79000004,
-0xc90e9eb7,
-0xc9009eb6,
-0x79000005,
-0x51070c07,
-0xd1009e03,
-0x1f012c2c,
-0x79000004,
+0xc9009e04,
 0x1d009e9e,
-0x2e85858c,
-0x79000023,
+0x91005c8c,
+0x7900001f,
 0x09020c94,
 0xd1032c05,
 0x01190c8f,
@@ -236,33 +225,33 @@ const unsigned int TX_PRU_SLICE1_b00[]= {
 0x32800000,
 0x90e73c94,
 0x10e7e7f0,
-0x0104e7e7,
-0x48e7e902,
-0x10e6e6e7,
-0x80911c87,
-0x24000701,
-0x2ec80061,
-0x2f480061,
+0x0104e7d1,
+0x48d1e902,
+0x10e6e6d1,
 0x0b18f44c,
 0x240fff93,
 0x0b0cf48d,
 0x10938d8d,
-0x51008d45,
+0x51008d46,
 0x1093f4ee,
 0x0905eeee,
 0x00e2eeee,
-0xd1089e56,
+0xd1089e46,
 0x10eeeef3,
 0x24000094,
 0x24000492,
 0x32000000,
+0x2eb00002,
 0x2f300492,
 0x32800000,
 0xd1074c01,
+0x80911cd1,
+0x24000701,
+0x2ec80061,
+0x2f480061,
 0x2eb00012,
 0xd703f2ff,
 0x2eb00f82,
-0x1f002c2c,
 0x11054c12,
 0x24003493,
 0xc9032c02,
@@ -293,17 +282,14 @@ const unsigned int TX_PRU_SLICE1_b00[]= {
 0x12525555,
 0x240c1493,
 0x80932995,
-0xc9012c03,
-0x1f051212,
-0x79000002,
-0x1f041212,
 0x24004094,
 0xc9001202,
-0x24000894,
+0x24000194,
 0x916c1b96,
 0x4e9496ff,
 0x2f140012,
 0x2f140f82,
+0x1f002c2c,
 0x0120cdcd,
 0x0120eeee,
 0x10eeeef3,
@@ -319,24 +305,11 @@ const unsigned int TX_PRU_SLICE1_b00[]= {
 0x2eff858c,
 0x24003601,
 0x81480901,
-0xc90e9e11,
-0xc9012c10,
-0x2e878187,
-0xd1019e04,
-0x5100870d,
-0x27018700,
-0x79000003,
-0x5100c70a,
-0x2701c700,
-0x0b010000,
-0x69070007,
-0x6120cd06,
-0x04cd8d80,
-0x61608004,
-0x1f022c2c,
-0x24004b01,
-0x81480901,
-0x7900003a,
+0x7900003f,
+0x80911cd1,
+0x24000701,
+0x2ec80061,
+0x2f480061,
 0x24ffe0d3,
 0x10d38d93,
 0x0093eeee,
@@ -390,7 +363,8 @@ const unsigned int TX_PRU_SLICE1_b00[]= {
 0x2f288981,
 0x24003d01,
 0x81480901,
-0x79000004,
+0x79000005,
+0x2eff858c,
 0x24000701,
 0x2ec80061,
 0x2f480061,
@@ -405,25 +379,21 @@ const unsigned int TX_PRU_SLICE1_b00[]= {
 0x79000002,
 0x1f042020,
 0x817a1c80,
-0x7f00000e,
+0x7f000028,
 0x2efe0060,
-0x21016000,
+0x21014600,
 0x2f861780,
 0x2f861792,
-0xc9002c4b,
-0xc9022c0f,
-0x2eb00012,
-0xd703f2ff,
-0x2eb00f82,
-0x2f143e82,
-0x0120cdcd,
-0x0120eeee,
+0xc9002c47,
+0x2e940193,
+0x117f5353,
+0x49015344,
+0xc9022c08,
 0x24008012,
 0x2f140012,
 0x242c00df,
 0x1f009e9e,
-0x1d022c2c,
-0x2f05858c,
+0x81005c8c,
 0x2eff858c,
 0x7900003c,
 0x6920cd04,
@@ -488,7 +458,7 @@ const unsigned int TX_PRU_SLICE1_b00[]= {
 0x2f861792,
 0x2f861780,
 0x2efe0060,
-0x2101b100,
+0x21019300,
 0x2f063b80,
 0x91543992,
 0x4902f20e,
@@ -509,4 +479,4 @@ const unsigned int TX_PRU_SLICE1_b00[]= {
 0x81543992,
 0x2efe0060,
 0x2e863b80,
-0x2101c600 };
+0x2101a800 };

diff --git a/firmware/icss_switch/bin/switch_mem_map.h b/firmware/icss_switch/bin/switch_mem_map.h
index ba47c08275e21890fe07b268db8ee4521846bf7d..3ae04111b0e136a909c22692dcab8556e7fb9d36 100644 (file)
--- a/firmware/icss_switch/bin/switch_mem_map.h
+++ b/firmware/icss_switch/bin/switch_mem_map.h
@@ -1,706 +1,708 @@
-//***********************************************************************************\r
-//**+-----------------------------------------------------------------------------+**\r
-//**|                              ******                                         |**\r
-//**|                              ******     o                                   |**\r
-//**|                              *******__////__****                            |**\r
-//**|                              ***** /_ //___/ ***                            |**\r
-//**|                           ********* ////__ ******                           |**\r
-//**|                             *******(_____/ ******                           |**\r
-//**|                                 **********                                  |**\r
-//**|                                   ******                                    |**\r
-//**|                                      ***                                    |**\r
-//**|                                                                             |**\r
-//**|            Copyright (c) 2019 Texas Instruments Incorporated                |**\r
-//**|                           ALL RIGHTS RESERVED                               |**\r
-//**|                                                                             |**\r
-//**|    Permission is hereby granted to licensees of Texas Instruments           |**\r
-//**|    Incorporated (TI) products to use this computer program for the sole     |**\r
-//**|    purpose of implementing a licensee product based on TI products.         |**\r
-//**|    No other rights to reproduce, use, or disseminate this computer          |**\r
-//**|    program, whether in part or in whole, are granted.                       |**\r
-//**|                                                                             |**\r
-//**|    TI makes no representation or warranties with respect to the             |**\r
-//**|    performance of this computer program, and specifically disclaims         |**\r
-//**|    any responsibility for any damages, special or consequential,            |**\r
-//**|    connected with the use of this program.                                  |**\r
-//**|                                                                             |**\r
-//**+-----------------------------------------------------------------------------+**\r
-//***********************************************************************************\r
-// file:     switch_mem_map.h\r
-//\r
-// brief:    Contains memory map for Ethernet Switch.\r
-//           This file is shared by firmware and driver.\r
-\r
-#ifndef ____switch_mem_map_h\r
-#define ____switch_mem_map_h 1\r
-\r
-#include "switch_mmap_defines.h"\r
-\r
-//************************************************************************************\r
-//\r
-// Memory Usage of : SHARED_MEMORY\r
-//\r
-//************************************************************************************\r
-\r
-#define SHARED_MEMORY_START_OFFSET                         0x0000\r
-#define PRE_EMPTION_CONTEXT_OFFSET                         0x0000    //Backup of active Tx and Q context. The offset is not used\r
-#define PRE_EMPTION_CONTEXT_OFFSET_SIZE                    0x8\r
-#define FW_HOST_HANDSHAKE_MAGIC_VAL_OFFSET                 0x0008    //Firmware host handshake\r
-#define FW_HOST_HANDSHAKE_MAGIC_VAL_OFFSET_SIZE            0x4\r
-#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET                  0x000C    //Base Flow ID for sending packets to Host\r
-#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET_SIZE             0x2\r
-#define EMAC_ICSSG_SWITCH_PSI_L_REGULAR_FLOW_ID_BASE_OFFSET PSI_L_REGULAR_FLOW_ID_BASE_OFFSET    //Same as PSI_L_REGULAR_FLOW_ID_BASE_OFFSET\r
-#define PSI_L_MGMT_FLOW_ID_OFFSET                          0x000E    //Base Flow ID for sending mgmt and Tx TS to Host\r
-#define PSI_L_MGMT_FLOW_ID_OFFSET_SIZE                     0x2\r
-#define EMAC_ICSSG_SWITCH_PSI_L_MGMT_FLOW_ID_BASE_OFFSET   PSI_L_MGMT_FLOW_ID_OFFSET    //Same as PSI_L_MGMT_FLOW_ID_OFFSET\r
-#define SPL_PKT_DEFAULT_PRIORITY                           0x0010    //Queue number for Special packets written here. Only 1B is used\r
-#define SPL_PKT_DEFAULT_PRIORITY_SIZE                      0x4\r
-#define FDB_SA_MAC_ADDRESS                                 0x0014    //Used internally by FW for learning\r
-#define FDB_SA_MAC_ADDRESS_SIZE                            0x8\r
-#define FDB_FID_FIDC2_OFFSET                               0x001C    //Used internally by FW for learning\r
-#define FDB_FID_FIDC2_OFFSET_SIZE                          0x4\r
-#define FDB_BUCKET_OFFSET                                  0x0020    //Used internally by FW for learning\r
-#define FDB_BUCKET_OFFSET_SIZE                             0x4\r
-#define FDB_AGEING_LAST_USED_OFFSET                        0x0024    //Used internally by FW for learning\r
-#define FDB_AGEING_LAST_USED_OFFSET_SIZE                   0x4\r
-#define TX_SOF_TS_OFFSET                                   0x0028    //Used internally by FW to store Tx timestamp\r
-#define TX_SOF_TS_OFFSET_SIZE                              0x8\r
-#define TX_TS_COOKIE_OFFSET                                0x0030    //Used internally by FW to stash cookie\r
-#define TX_TS_COOKIE_OFFSET_SIZE                           0x4\r
-#define HOST_PORT_DF_VLAN_OFFSET                           0x0034    //default VLAN tag for Host Port\r
-#define HOST_PORT_DF_VLAN_OFFSET_SIZE                      0x4\r
-#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET        HOST_PORT_DF_VLAN_OFFSET    //Same as HOST_PORT_DF_VLAN_OFFSET\r
-#define P1_PORT_DF_VLAN_OFFSET                             0x0038    //default VLAN tag for P1 Port\r
-#define P1_PORT_DF_VLAN_OFFSET_SIZE                        0x4\r
-#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET        P1_PORT_DF_VLAN_OFFSET    //Same as P1_PORT_DF_VLAN_OFFSET\r
-#define P2_PORT_DF_VLAN_OFFSET                             0x003C    //default VLAN tag for P2 Port\r
-#define P2_PORT_DF_VLAN_OFFSET_SIZE                        0x4\r
-#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET        P2_PORT_DF_VLAN_OFFSET    //Same as P2_PORT_DF_VLAN_OFFSET\r
-#define RX_TS_STASHED                                      0x0040    //Used internally by FW for stashed Rx timestamp\r
-#define RX_TS_STASHED_SIZE                                 0x8\r
-#define MGR_CMD_OFFSET                                     0x0048    //Management command from Host to RTU0\r
-#define MGR_CMD_OFFSET_SIZE                                0x20\r
-#define MGR_CMD_RET                                        0x0068    //Management reply to Host from RTU0\r
-#define MGR_CMD_RET_SIZE                                   0xc\r
-#define MGR_CMD_STATE                                      0x0074    //0 - idle; 1 - todo; 2 - executing\r
-#define MGR_CMD_STATE_SIZE                                 0x1\r
-//Padding of 3 bytes\r
-#define MGR_CMD_PRU0_STATUS                                0x0078    //Used internally by FW to communicate from RTU0 to PRU0\r
-#define MGR_CMD_PRU0_STATUS_SIZE                           0x2\r
-#define MGR_CMD_PRU1_STATUS                                0x007A    //Used internally by FW to communicate from RTU0 to PRU1\r
-#define MGR_CMD_PRU1_STATUS_SIZE                           0x2\r
-#define MGR_CMD_RTU0_STATUS                                0x007C    //Used internally by FW to communicate from RTU0 to RTU0\r
-#define MGR_CMD_RTU0_STATUS_SIZE                           0x2\r
-#define MGR_CMD_RTU1_STATUS                                0x007E    //Used internally by FW to for management state machine\r
-#define MGR_CMD_RTU1_STATUS_SIZE                           0x42\r
-#define MGR_CMD_END_OFFSET                                 0x00C0    //End of Management command region\r
-#define PORT_Q0_RD_PTR_OFFSET                              0x0100    //Port Tx Q0 MSMC Read pointer stored here\r
-#define PORT_Q0_RD_PTR_OFFSET_SIZE                         0x4\r
-#define EMAC_ICSSG_SWITCH_PORT_QUEUE_READ_PTR_OFFSET       PORT_Q0_RD_PTR_OFFSET    //Same as PORT_Q0_RD_PTR_OFFSET\r
-#define PORT_Q1_RD_PTR_OFFSET                              0x0104    //Port Tx Q1 MSMC Read pointer stored here\r
-#define PORT_Q1_RD_PTR_OFFSET_SIZE                         0x4\r
-#define PORT_Q2_RD_PTR_OFFSET                              0x0108    //Port Tx Q2 MSMC Read pointer stored here\r
-#define PORT_Q2_RD_PTR_OFFSET_SIZE                         0x4\r
-#define PORT_Q3_RD_PTR_OFFSET                              0x010C    //Port Tx Q3 MSMC Read pointer stored here\r
-#define PORT_Q3_RD_PTR_OFFSET_SIZE                         0x4\r
-#define PORT_Q4_RD_PTR_OFFSET                              0x0110    //Port Tx Q4 MSMC Read pointer stored here\r
-#define PORT_Q4_RD_PTR_OFFSET_SIZE                         0x4\r
-#define PORT_Q5_RD_PTR_OFFSET                              0x0114    //Port Tx Q5 MSMC Read pointer stored here\r
-#define PORT_Q5_RD_PTR_OFFSET_SIZE                         0x4\r
-#define PORT_Q6_RD_PTR_OFFSET                              0x0118    //Port Tx Q6 MSMC Read pointer stored here\r
-#define PORT_Q6_RD_PTR_OFFSET_SIZE                         0x4\r
-#define PORT_Q7_RD_PTR_OFFSET                              0x011C    //Port Tx Q1 MSMC Read pointer stored here\r
-#define PORT_Q7_RD_PTR_OFFSET_SIZE                         0x4\r
-#define HOST_Q0_RD_PTR_OFFSET                              0x0120    //Host Tx Q0 MSMC Read pointer stored here\r
-#define HOST_Q0_RD_PTR_OFFSET_SIZE                         0x4\r
-#define HOST_Q1_RD_PTR_OFFSET                              0x0124    //Host Tx Q1 MSMC Read pointer stored here\r
-#define HOST_Q1_RD_PTR_OFFSET_SIZE                         0x4\r
-#define HOST_Q2_RD_PTR_OFFSET                              0x0128    //Host Tx Q2 MSMC Read pointer stored here\r
-#define HOST_Q2_RD_PTR_OFFSET_SIZE                         0x4\r
-#define HOST_Q3_RD_PTR_OFFSET                              0x012C    //Host Tx Q3 MSMC Read pointer stored here\r
-#define HOST_Q3_RD_PTR_OFFSET_SIZE                         0x4\r
-#define HOST_Q4_RD_PTR_OFFSET                              0x0130    //Host Tx Q4 MSMC Read pointer stored here\r
-#define HOST_Q4_RD_PTR_OFFSET_SIZE                         0x4\r
-#define HOST_Q5_RD_PTR_OFFSET                              0x0134    //Host Tx Q5 MSMC Read pointer stored here\r
-#define HOST_Q5_RD_PTR_OFFSET_SIZE                         0x4\r
-#define HOST_Q6_RD_PTR_OFFSET                              0x0138    //Host Tx Q6 MSMC Read pointer stored here\r
-#define HOST_Q6_RD_PTR_OFFSET_SIZE                         0x4\r
-#define HOST_Q7_RD_PTR_OFFSET                              0x013C    //Host Tx Q7 MSMC Read pointer stored here\r
-#define HOST_Q7_RD_PTR_OFFSET_SIZE                         0x4\r
-#define HOST_RX_PRE_RD_PTR_OFFSET                          0x0140    //Host Egress Q MSMC Read pointer (for Pre-emptive queue) stored here\r
-#define HOST_RX_PRE_RD_PTR_OFFSET_SIZE                     0x4\r
-#define EMAC_ICSSG_SWITCH_HOST_QUEUE_READ_PTR_OFFSET       HOST_RX_PRE_RD_PTR_OFFSET    //Same as HOST_RX_PRE_RD_PTR_OFFSET\r
-#define HOST_RX_PRE_WR_PTR_OFFSET                          0x0144    //Host Egress Q MSMC Write pointer (for Pre-emptive queue) stored here\r
-#define HOST_RX_PRE_WR_PTR_OFFSET_SIZE                     0x4\r
-#define HOST_RX_EXP_RD_PTR_OFFSET                          0x0148    //Reserved for Future Use\r
-#define HOST_RX_EXP_RD_PTR_OFFSET_SIZE                     0x4\r
-#define HOST_RX_EXP_WR_PTR_OFFSET                          0x014C    //Reserved for Future Use\r
-#define HOST_RX_EXP_WR_PTR_OFFSET_SIZE                     0x4\r
-#define PORT_Q0_DESC_RD_PTR_OFFSET                         0x0150    //Port Tx Q0 Desc Read pointer stored here\r
-#define PORT_Q0_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q0_DESC_WR_PTR_OFFSET                         0x0152    //Port Tx Q0 Desc Write pointer stored here\r
-#define PORT_Q0_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q1_DESC_RD_PTR_OFFSET                         0x0154    //Port Tx Q1 Desc Read pointer stored here\r
-#define PORT_Q1_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q1_DESC_WR_PTR_OFFSET                         0x0156    //Port Tx Q1 Desc Write pointer stored here\r
-#define PORT_Q1_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q2_DESC_RD_PTR_OFFSET                         0x0158    //Port Tx Q2 Desc Read pointer stored here\r
-#define PORT_Q2_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q2_DESC_WR_PTR_OFFSET                         0x015A    //Port Tx Q2 Desc Write pointer stored here\r
-#define PORT_Q2_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q3_DESC_RD_PTR_OFFSET                         0x015C    //Port Tx Q3 Desc Read pointer stored here\r
-#define PORT_Q3_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q3_DESC_WR_PTR_OFFSET                         0x015E    //Port Tx Q3 Desc Write pointer stored here\r
-#define PORT_Q3_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q4_DESC_RD_PTR_OFFSET                         0x0160    //Port Tx Q4 Desc Read pointer stored here\r
-#define PORT_Q4_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q4_DESC_WR_PTR_OFFSET                         0x0162    //Port Tx Q4 Desc Write pointer stored here\r
-#define PORT_Q4_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q5_DESC_RD_PTR_OFFSET                         0x0164    //Port Tx Q5 Desc Read pointer stored here\r
-#define PORT_Q5_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q5_DESC_WR_PTR_OFFSET                         0x0166    //Port Tx Q5 Desc Write pointer stored here\r
-#define PORT_Q5_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q6_DESC_RD_PTR_OFFSET                         0x0168    //Port Tx Q3 Desc Read pointer stored here\r
-#define PORT_Q6_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q6_DESC_WR_PTR_OFFSET                         0x016A    //Port Tx Q6 Desc Write pointer stored here\r
-#define PORT_Q6_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q7_DESC_RD_PTR_OFFSET                         0x016C    //Port Tx Q7 Desc Read pointer stored here\r
-#define PORT_Q7_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define PORT_Q7_DESC_WR_PTR_OFFSET                         0x016E    //Port Tx Q7 Desc Write pointer stored here\r
-#define PORT_Q7_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q0_DESC_RD_PTR_OFFSET                         0x0170    //Host Tx Q0 Desc Read pointer stored here\r
-#define HOST_Q0_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q0_DESC_WR_PTR_OFFSET                         0x0172    //Host Tx Q0 Desc Write pointer stored here\r
-#define HOST_Q0_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q1_DESC_RD_PTR_OFFSET                         0x0174    //Host Tx Q1 Desc Read pointer stored here\r
-#define HOST_Q1_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q1_DESC_WR_PTR_OFFSET                         0x0176    //Host Tx Q1 Desc Write pointer stored here\r
-#define HOST_Q1_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q2_DESC_RD_PTR_OFFSET                         0x0178    //Host Tx Q2 Desc Read pointer stored here\r
-#define HOST_Q2_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q2_DESC_WR_PTR_OFFSET                         0x017A    //Host Tx Q2 Desc Write pointer stored here\r
-#define HOST_Q2_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q3_DESC_RD_PTR_OFFSET                         0x017C    //Host Tx Q3 Desc Read pointer stored here\r
-#define HOST_Q3_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q3_DESC_WR_PTR_OFFSET                         0x017E    //Host Tx Q3 Desc Write pointer stored here\r
-#define HOST_Q3_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q4_DESC_RD_PTR_OFFSET                         0x0180    //Host Tx Q4 Desc Read pointer stored here\r
-#define HOST_Q4_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q4_DESC_WR_PTR_OFFSET                         0x0182    //Host Tx Q4 Desc Write pointer stored here\r
-#define HOST_Q4_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q5_DESC_RD_PTR_OFFSET                         0x0184    //Host Tx Q5 Desc Read pointer stored here\r
-#define HOST_Q5_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q5_DESC_WR_PTR_OFFSET                         0x0186    //Host Tx Q5 Desc Write pointer stored here\r
-#define HOST_Q5_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q6_DESC_RD_PTR_OFFSET                         0x0188    //Host Tx Q6 Desc Read pointer stored here\r
-#define HOST_Q6_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q6_DESC_WR_PTR_OFFSET                         0x018A    //Host Tx Q6 Desc Write pointer stored here\r
-#define HOST_Q6_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q7_DESC_RD_PTR_OFFSET                         0x018C    //Host Tx Q7 Desc Read pointer stored here\r
-#define HOST_Q7_DESC_RD_PTR_OFFSET_SIZE                    0x2\r
-#define HOST_Q7_DESC_WR_PTR_OFFSET                         0x018E    //Host Tx Q7 Desc Write pointer stored here\r
-#define HOST_Q7_DESC_WR_PTR_OFFSET_SIZE                    0x2\r
-#define VLAN_STATIC_REG_TABLE_OFFSET                       0x0190    //VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000\r
-#define VLAN_STATIC_REG_TABLE_OFFSET_SIZE                  0x2000\r
-#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET        VLAN_STATIC_REG_TABLE_OFFSET    //VLAN-FID Table offset for EMAC\r
-#define SMEM_VLAN_END_OF_MEM                               0x2190    //End of VLAN-FID table marker\r
-#define SMEM_VLAN_END_OF_MEM_SIZE                          0x4\r
-#define PORT_Q0_CONTEXT_OFFSET                             0x2194    //16B for Port Tx MSMC Q context\r
-#define PORT_Q0_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define EMAC_ICSSG_SWITCH_PORT_QUEUE_CONTEXT_OFFSET        PORT_Q0_CONTEXT_OFFSET    //Same as PORT_Q0_CONTEXT_OFFSET\r
-#define PORT_Q1_CONTEXT_OFFSET                             0x21A4    //16B for Port Tx MSMC Q context\r
-#define PORT_Q1_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define PORT_Q2_CONTEXT_OFFSET                             0x21B4    //16B for Port Tx MSMC Q context\r
-#define PORT_Q2_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define PORT_Q3_CONTEXT_OFFSET                             0x21C4    //16B for Port Tx MSMC Q context\r
-#define PORT_Q3_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define PORT_Q4_CONTEXT_OFFSET                             0x21D4    //16B for Port Tx MSMC Q context\r
-#define PORT_Q4_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define PORT_Q5_CONTEXT_OFFSET                             0x21E4    //16B for Port Tx MSMC Q context\r
-#define PORT_Q5_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define PORT_Q6_CONTEXT_OFFSET                             0x21F4    //16B for Port Tx MSMC Q context\r
-#define PORT_Q6_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define PORT_Q7_CONTEXT_OFFSET                             0x2204    //16B for Port Tx MSMC Q context\r
-#define PORT_Q7_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q0_CONTEXT_OFFSET                             0x2214    //16B for Host Tx MSMC Q context\r
-#define HOST_Q0_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q1_CONTEXT_OFFSET                             0x2224    //16B for Host Tx MSMC Q context\r
-#define HOST_Q1_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q2_CONTEXT_OFFSET                             0x2234    //16B for Host Tx MSMC Q context\r
-#define HOST_Q2_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q3_CONTEXT_OFFSET                             0x2244    //16B for Host Tx MSMC Q context\r
-#define HOST_Q3_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q4_CONTEXT_OFFSET                             0x2254    //16B for Host Tx MSMC Q context\r
-#define HOST_Q4_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q5_CONTEXT_OFFSET                             0x2264    //16B for Host Tx MSMC Q context\r
-#define HOST_Q5_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q6_CONTEXT_OFFSET                             0x2274    //16B for Host Tx MSMC Q context\r
-#define HOST_Q6_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q7_CONTEXT_OFFSET                             0x2284    //16B for Host Tx MSMC Q context\r
-#define HOST_Q7_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_RX_Q_PRE_CONTEXT_OFFSET                       0x2294    //16B for Host Egress MSMC Q (Pre-emptible) context\r
-#define HOST_RX_Q_PRE_CONTEXT_OFFSET_SIZE                  (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_RX_Q_EXP_CONTEXT_OFFSET                       0x22A4    //16B for Host Egress MSMC Q (Express) context\r
-#define HOST_RX_Q_EXP_CONTEXT_OFFSET_SIZE                  (NRT_QUEUE_CONTEXT_SIZE) //0x10\r
-#define DEFAULT_MSMC_Q_OFFSET                              (HOST_RX_Q_EXP_CONTEXT_OFFSET + 12)    //End of NRT MSMC region.\r
-#define PORT_Q0_DESC_CONTEXT_OFFSET                        0x22B4    //16B for Port Tx Q Desc context\r
-#define PORT_Q0_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define EMAC_ICSSG_SWITCH_PORT_DESC_QUEUE_CONTEXT_OFFSET   PORT_Q0_DESC_CONTEXT_OFFSET    //Start of Queue Descriptors for EMAC\r
-#define PORT_Q1_DESC_CONTEXT_OFFSET                        0x22C4    //16B for Port Tx Q Desc context\r
-#define PORT_Q1_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define PORT_Q2_DESC_CONTEXT_OFFSET                        0x22D4    //16B for Port Tx Q Desc context\r
-#define PORT_Q2_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define PORT_Q3_DESC_CONTEXT_OFFSET                        0x22E4    //16B for Port Tx Q Desc context\r
-#define PORT_Q3_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define PORT_Q4_DESC_CONTEXT_OFFSET                        0x22F4    //16B for Port Tx Q Desc context\r
-#define PORT_Q4_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define PORT_Q5_DESC_CONTEXT_OFFSET                        0x2304    //16B for Port Tx Q Desc context\r
-#define PORT_Q5_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define PORT_Q6_DESC_CONTEXT_OFFSET                        0x2314    //16B for Port Tx Q Desc context\r
-#define PORT_Q6_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define PORT_Q7_DESC_CONTEXT_OFFSET                        0x2324    //16B for Port Tx Q Desc context\r
-#define PORT_Q7_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q0_DESC_CONTEXT_OFFSET                        0x2334    //16B for Port Tx Q Desc context\r
-#define HOST_Q0_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q1_DESC_CONTEXT_OFFSET                        0x2344    //16B for Host Tx Q Desc context\r
-#define HOST_Q1_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q2_DESC_CONTEXT_OFFSET                        0x2354    //16B for Host Tx Q Desc context\r
-#define HOST_Q2_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q3_DESC_CONTEXT_OFFSET                        0x2364    //16B for Host Tx Q Desc context\r
-#define HOST_Q3_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q4_DESC_CONTEXT_OFFSET                        0x2374    //16B for Host Tx Q Desc context\r
-#define HOST_Q4_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q5_DESC_CONTEXT_OFFSET                        0x2384    //16B for Host Tx Q Desc context\r
-#define HOST_Q5_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q6_DESC_CONTEXT_OFFSET                        0x2394    //16B for Host Tx Q Desc context\r
-#define HOST_Q6_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_Q7_DESC_CONTEXT_OFFSET                        0x23A4    //16B for Host Tx Q Desc context\r
-#define HOST_Q7_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_RX_Q_PRE_DESC_CONTEXT_OFFSET                  0x23B4    //16B for Host Egress Q (pre-emptible) Desc context\r
-#define HOST_RX_Q_PRE_DESC_CONTEXT_OFFSET_SIZE             (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define HOST_RX_Q_EXP_DESC_CONTEXT_OFFSET                  0x23C4    //16B for Host Egress Q (Express) Desc context. redundant\r
-#define HOST_RX_Q_EXP_DESC_CONTEXT_OFFSET_SIZE             (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10\r
-#define PORT_DESC_Q0_OFFSET                                0x23D4    //packet descriptor Q reserved memory\r
-#define PORT_DESC_Q0_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734\r
-#define PORT_DESC_Q1_OFFSET                                0x2B08    //packet descriptor Q reserved memory for Port Tx queues\r
-#define PORT_DESC_Q1_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734\r
-#define PORT_DESC_Q2_OFFSET                                0x323C    //packet descriptor Q reserved memory for Port Tx queues\r
-#define PORT_DESC_Q2_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734\r
-#define PORT_DESC_Q3_OFFSET                                0x3970    //packet descriptor Q reserved memory for Port Tx queues\r
-#define PORT_DESC_Q3_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734\r
-#define PORT_DESC_Q4_OFFSET                                0x40A4    //packet descriptor Q reserved memory for Port Tx queues\r
-#define PORT_DESC_Q4_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734\r
-#define PORT_DESC_Q5_OFFSET                                0x47D8    //packet descriptor Q reserved memory for Port Tx queues\r
-#define PORT_DESC_Q5_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734\r
-#define PORT_DESC_Q6_OFFSET                                0x4F0C    //packet descriptor Q reserved memory for Port Tx queues\r
-#define PORT_DESC_Q6_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734\r
-#define PORT_DESC_Q7_OFFSET                                0x5640    //packet descriptor Q reserved memory for Port Tx queues\r
-#define PORT_DESC_Q7_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734\r
-#define HOST_DESC_Q0_OFFSET                                0x5D74    //packet descriptor Q reserved memory for Host Tx queues\r
-#define HOST_DESC_Q0_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234\r
-#define HOST_DESC_Q1_OFFSET                                0x5FA8    //packet descriptor Q reserved memory for Host Tx queues\r
-#define HOST_DESC_Q1_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234\r
-#define HOST_DESC_Q2_OFFSET                                0x61DC    //packet descriptor Q reserved memory for Host Tx queues\r
-#define HOST_DESC_Q2_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234\r
-#define HOST_DESC_Q3_OFFSET                                0x6410    //packet descriptor Q reserved memory for Host Tx queues\r
-#define HOST_DESC_Q3_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234\r
-#define HOST_DESC_Q4_OFFSET                                0x6644    //packet descriptor Q reserved memory for Host Tx queues\r
-#define HOST_DESC_Q4_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234\r
-#define HOST_DESC_Q5_OFFSET                                0x6878    //packet descriptor Q reserved memory for Host Tx queues\r
-#define HOST_DESC_Q5_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234\r
-#define HOST_DESC_Q6_OFFSET                                0x6AAC    //packet descriptor Q reserved memory for Host Tx queues\r
-#define HOST_DESC_Q6_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234\r
-#define HOST_DESC_Q7_OFFSET                                0x6CE0    //packet descriptor Q reserved memory for Host Tx queues\r
-#define HOST_DESC_Q7_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234\r
-#define HOST_RX_DESC_Q_PRE_OFFSET                          0x6F14    //packet descriptor Q reserved memory for Host Egress (Pre-emptible) queues\r
-#define HOST_RX_DESC_Q_PRE_OFFSET_SIZE                     (NRT_PORT_DESC_QUEUE_SIZE) //0x734\r
-#define HOST_RX_DESC_Q_EXP_OFFSET                          0x7648    //packet descriptor Q reserved memory for Host Egress (Pre-emptible) queues. redundant\r
-#define HOST_RX_DESC_Q_EXP_OFFSET_SIZE                     (NRT_PORT_DESC_QUEUE_SIZE) //0x734\r
-#define SHARED_MEMORY_END_OFFSET                           0x7D7C\r
-\r
-// total SHARED_MEMORY memory usage : 31.37109375 KB from total of 64.0KB \r
-\r
-//************************************************************************************\r
-//\r
-// Memory Usage of : MSMC\r
-//\r
-//************************************************************************************\r
-\r
-#define MSMC_START_OFFSET                                  0x0000\r
-#define MSMC_END_OFFSET                                    0x0000\r
-\r
-// total MSMC memory usage : 0.0 KB from total of 2048.0KB \r
-\r
-//************************************************************************************\r
-//\r
-// Memory Usage of : DMEM0\r
-//\r
-//************************************************************************************\r
-\r
-#define DMEM0_START_OFFSET                                 0x0000\r
-#define PORT_Q_PRIORITY_REGEN_OFFSET                       0x0000    //Stores the table used for priority regeneration. 4B per PCP/Queue. Only 1B is used\r
-#define PORT_Q_PRIORITY_REGEN_OFFSET_SIZE                  0x20\r
-#define EXPRESS_PRE_EMPTIVE_Q_MAP                          0x0020    //For marking packet as priority/express (this feature is disabled) or cut-through/S&F. One per slice\r
-#define EXPRESS_PRE_EMPTIVE_Q_MAP_SIZE                     0x20\r
-#define TAS_CONFIG_CHANGE_TIME                             0x0040    //New list is copied at this time\r
-#define TAS_CONFIG_CHANGE_TIME_SIZE                        0x8\r
-#define TAS_CONFIG_CHANGE_ERROR_COUNTER                    0x0048    //config change error counter\r
-#define TAS_CONFIG_CHANGE_ERROR_COUNTER_SIZE               0x4\r
-#define TAS_CONFIG_PENDING                                 0x004C    //TAS List update pending flag\r
-#define TAS_CONFIG_PENDING_SIZE                            0x1\r
-#define TAS_CONFIG_CHANGE                                  0x004D    //TAS list update trigger flag\r
-#define TAS_CONFIG_CHANGE_SIZE                             0x1\r
-//Padding of 2 bytes\r
-#define TAS_ADMIN_CYCLE_TIME                               0x0050    //Cycle time for the new TAS schedule\r
-#define TAS_ADMIN_CYCLE_TIME_SIZE                          0x4\r
-#define TAS_CONFIG_CHANGE_CYCLE_COUNT                      0x0054    //Cycle counts remaining till the TAS list update\r
-#define TAS_CONFIG_CHANGE_CYCLE_COUNT_SIZE                 0x4\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE0                       0x0100    //TAS gate expiry list for gate0\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE0_SIZE                  0x20\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE1                       0x0120    //TAS gate expiry list for gate1\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE1_SIZE                  0x20\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE2                       0x0140    //TAS gate expiry list for gate2\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE2_SIZE                  0x20\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE3                       0x0160    //TAS gate expiry list for gate3\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE3_SIZE                  0x20\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE4                       0x0180    //TAS gate expiry list for gate4\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE4_SIZE                  0x20\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE5                       0x01A0    //TAS gate expiry list for gate5\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE5_SIZE                  0x20\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE6                       0x01C0    //TAS gate expiry list for gate6\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE6_SIZE                  0x20\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE7                       0x01E0    //TAS gate expiry list for gate7\r
-#define TAS_SHADOW_EXPIRY_LIST_GATE7_SIZE                  0x20\r
-#define PRE_EMPTION_ENABLE_TX                              0x0200    //Memory to Enable/Disable Preemption on TX side\r
-#define PRE_EMPTION_ENABLE_TX_SIZE                         0x1\r
-#define PRE_EMPTION_ACTIVE_TX                              0x0201    //Active State of Preemption on TX side\r
-#define PRE_EMPTION_ACTIVE_TX_SIZE                         0x1\r
-#define PRE_EMPTION_ENABLE_VERIFY                          0x0202    //Memory to Enable/Disable Verify State Machine Preemption\r
-#define PRE_EMPTION_ENABLE_VERIFY_SIZE                     0x1\r
-#define PRE_EMPTION_VERIFY_STATUS                          0x0203    //Verify Status of State Machine\r
-#define PRE_EMPTION_VERIFY_STATUS_SIZE                     0x1\r
-#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE                   0x0204    //Non Final Fragment Size supported by Link Partner\r
-#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE_SIZE              0x2\r
-#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL                    0x0206    //Non Final Fragment Size supported by Firmware\r
-#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL_SIZE               0x1\r
-//Padding of 1 bytes\r
-#define PRE_EMPTION_VERIFY_TIME                            0x0208    //Time in ms the State machine waits for respond packet\r
-#define PRE_EMPTION_VERIFY_TIME_SIZE                       0x2\r
-#define DMEM0_END_OFFSET                                   0x020A\r
-\r
-// total DMEM0 memory usage : 0.509765625 KB from total of 8.0KB \r
-\r
-//************************************************************************************\r
-//\r
-// Memory Usage of : DMEM1\r
-//\r
-//************************************************************************************\r
-\r
-#define DMEM1_START_OFFSET                                 0x0000\r
-#define ICSS_FIRMWARE_VERSION_OFFSET                       0x0000    //ICSSG Firmware version details\r
-#define ICSS_FIRMWARE_VERSION_OFFSET_SIZE                  0xc\r
-#define NRT_FRAME_PREEMPTION_ENABLE_OFFSET                 0x000C    //Memory used for Global enable and disable Frame Preemption\r
-#define NRT_FRAME_PREEMPTION_ENABLE_OFFSET_SIZE            0x4\r
-#define NRT_STASHED_Q_NUM_OFFSET                           0x0010    //Memory used for Stashing queue number during Host Egress in BG Task\r
-#define NRT_STASHED_Q_NUM_OFFSET_SIZE                      0x4\r
-#define PSI_TX_PKT_DATA_OFFSET                             0x0014    //Used Internally by FW. \r
-#define PSI_TX_PKT_DATA_OFFSET_SIZE                        0x24\r
-#define LEARNING_WR_RD_COUNT_OFFSET                        0x0038    //Used Internally by FW to synchronize FDB Learning between RTU0 and PRU0 \r
-#define LEARNING_WR_RD_COUNT_OFFSET_SIZE                   0x4\r
-#define FDB_G0_M_G1_SLV_OFFSET                             0x003C    //Used Internally by FW to synchronize FDB Learning between two ICSSG's \r
-#define FDB_G0_M_G1_SLV_OFFSET_SIZE                        0x4\r
-#define FDB_G1_M_G0_SLV_OFFSET                             0x0040    //Used Internally by FW to synchronize FDB Learning between two ICSSG's \r
-#define FDB_G1_M_G0_SLV_OFFSET_SIZE                        0x4\r
-#define FDB_SYNC_ENTRY                                     0x0044    //Used to store the FDB entry one ICSSG learnt and one that needs to be communicated to other ICSSG \r
-#define FDB_SYNC_ENTRY_SIZE                                0x10\r
-#define DEBUG_FDB_COMPARISON_MAC_VLAN                      0x0054    //Used for debugging FDB lookups, write the MAC and VLAN combination that is suspect. Currently disabled\r
-#define DEBUG_FDB_COMPARISON_MAC_VLAN_SIZE                 0x8\r
-#define DEBUG_FDB_RESULTS                                  0x005C    //The results of FBD lookup for Local injection are dumped here\r
-#define DEBUG_FDB_RESULTS_SIZE                             0xc\r
-#define DMEM1_END_OFFSET                                   0x0100\r
-\r
-// total DMEM1 memory usage : 0.25 KB from total of 8.0KB \r
-\r
-//************************************************************************************\r
-//\r
-// Memory Usage of : PRU0_BSRAM\r
-//\r
-//************************************************************************************\r
-\r
-#define PRU0_BSRAM_START_OFFSET                            0x0000\r
-#define PSI_TX_INFO_SLOT_PRU0                              0x0000    //Store PSI template for INFO chunk\r
-#define PSI_TX_INFO_SLOT_PRU0_SIZE                         0x1\r
-#define HOST_RX_PACKET_DESC_SLOT_PRU0                      0x0001    //Stores the PSI descriptor for packet being sent to Host\r
-#define HOST_RX_PACKET_DESC_SLOT_PRU0_SIZE                 0x1\r
-#define HOST_RX_PRE_CONTEXT_RD_SLOT_PRU0                   0x0002    //Contains context info for Host Egress Queue (pre-emptible). Used by read task\r
-#define HOST_RX_PRE_CONTEXT_RD_SLOT_PRU0_SIZE              0x1\r
-#define HOST_RX_PRE_CONTEXT_WR_SLOT_PRU0                   0x0003    //Contains context info for Host Egress Queue (pre-emptible). Used by write task\r
-#define HOST_RX_PRE_CONTEXT_WR_SLOT_PRU0_SIZE              0x1\r
-#define HOST_RX_EXP_CONTEXT_RD_SLOT_PRU0                   0x0004    //Contains context info for Host Egress Queue (express). redundant\r
-#define HOST_RX_EXP_CONTEXT_RD_SLOT_PRU0_SIZE              0x1\r
-#define HOST_RX_EXP_CONTEXT_WR_SLOT_PRU0                   0x0005    //Contains context info for Host Egress Queue (express). redundant\r
-#define HOST_RX_EXP_CONTEXT_WR_SLOT_PRU0_SIZE              0x1\r
-#define P0_FIRST_32B_PACKET_DATA                           0x0006    //Used to store 32B at the start of SOF\r
-#define P0_FIRST_32B_PACKET_DATA_SIZE                      0x1\r
-#define PRU0_BSRAM_END_OFFSET                              0x0007\r
-\r
-// total PRU0_BSRAM memory usage : 0.21875 KB from total of 4.0KB \r
-\r
-//************************************************************************************\r
-//\r
-// Memory Usage of : PRU1_BSRAM\r
-//\r
-//************************************************************************************\r
-\r
-#define PRU1_BSRAM_START_OFFSET                            0x0000\r
-#define P1_FIRST_32B_PACKET_DATA                           0x0000    //redundant\r
-#define P1_FIRST_32B_PACKET_DATA_SIZE                      0x1\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE0                       0x0001    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE0_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE1                       0x0002    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE1_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE2                       0x0003    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE2_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE3                       0x0004    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE3_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE4                       0x0005    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE4_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE5                       0x0006    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE5_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE6                       0x0007    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE6_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE7                       0x0008    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST0_GATE7_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE0                       0x0009    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE0_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE1                       0x000A    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE1_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE2                       0x000B    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE2_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE3                       0x000C    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE3_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE4                       0x000D    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE4_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE5                       0x000E    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE5_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE6                       0x000F    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE6_SIZE                  0x1\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE7                       0x0010    //32B total for one gate.\r
-#define TAS_BSRAM_EXPIRY_LIST1_GATE7_SIZE                  0x1\r
-#define PORT_Q0_CONTEXT_SLOT_PRU1                          0x0011    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q0_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define PORT_Q1_CONTEXT_SLOT_PRU1                          0x0012    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q1_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define PORT_Q2_CONTEXT_SLOT_PRU1                          0x0013    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q2_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define PORT_Q3_CONTEXT_SLOT_PRU1                          0x0014    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q3_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define PORT_Q4_CONTEXT_SLOT_PRU1                          0x0015    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q4_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define PORT_Q5_CONTEXT_SLOT_PRU1                          0x0016    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q5_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define PORT_Q6_CONTEXT_SLOT_PRU1                          0x0017    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q6_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define PORT_Q7_CONTEXT_SLOT_PRU1                          0x0018    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q7_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define HOST_Q0_CONTEXT_SLOT_PRU1                          0x0019    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define HOST_Q0_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define HOST_Q1_CONTEXT_SLOT_PRU1                          0x001A    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q1_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define HOST_Q2_CONTEXT_SLOT_PRU1                          0x001B    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q2_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define HOST_Q3_CONTEXT_SLOT_PRU1                          0x001C    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q3_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define HOST_Q4_CONTEXT_SLOT_PRU1                          0x001D    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q4_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define HOST_Q5_CONTEXT_SLOT_PRU1                          0x001E    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q5_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define HOST_Q6_CONTEXT_SLOT_PRU1                          0x001F    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q6_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define HOST_Q7_CONTEXT_SLOT_PRU1                          0x0020    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q7_CONTEXT_SLOT_PRU1_SIZE                     0x1\r
-#define PSI_TXTS_INFO_SLOT_PRU1                            0x0021    //Store Info chunk for Tx TS PSI transaction\r
-#define PSI_TXTS_INFO_SLOT_PRU1_SIZE                       0x1\r
-#define PRU1_BS_OFFSETS_END                                0x0022    //_Small_Description_\r
-#define PRU1_BSRAM_END_OFFSET                              0x0022\r
-\r
-// total PRU1_BSRAM memory usage : 1.0625 KB from total of 4.0KB \r
-\r
-//************************************************************************************\r
-//\r
-// Memory Usage of : RTU0_BSRAM\r
-//\r
-//************************************************************************************\r
-\r
-#define RTU0_BSRAM_START_OFFSET                            0x0000\r
-#define PSI_MGR_INFO_SLOT_RTU0                             0x0000    //Stores Management Frame PSI Info chunk\r
-#define PSI_MGR_INFO_SLOT_RTU0_SIZE                        0x1\r
-#define PORT_Q0_CONTEXT_SLOT_RTU0                          0x0001    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q0_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define PORT_Q1_CONTEXT_SLOT_RTU0                          0x0002    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q1_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define PORT_Q2_CONTEXT_SLOT_RTU0                          0x0003    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q2_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define PORT_Q3_CONTEXT_SLOT_RTU0                          0x0004    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q3_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define PORT_Q4_CONTEXT_SLOT_RTU0                          0x0005    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q4_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define PORT_Q5_CONTEXT_SLOT_RTU0                          0x0006    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q5_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define PORT_Q6_CONTEXT_SLOT_RTU0                          0x0007    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q6_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define PORT_Q7_CONTEXT_SLOT_RTU0                          0x0008    //Combined context (MSMC + Desc) for Port Tx queue\r
-#define PORT_Q7_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define HOST_Q0_CONTEXT_SLOT_RTU0                          0x0009    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q0_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define HOST_Q1_CONTEXT_SLOT_RTU0                          0x000A    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q1_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define HOST_Q2_CONTEXT_SLOT_RTU0                          0x000B    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q2_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define HOST_Q3_CONTEXT_SLOT_RTU0                          0x000C    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q3_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define HOST_Q4_CONTEXT_SLOT_RTU0                          0x000D    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q4_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define HOST_Q5_CONTEXT_SLOT_RTU0                          0x000E    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q5_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define HOST_Q6_CONTEXT_SLOT_RTU0                          0x000F    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q6_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define HOST_Q7_CONTEXT_SLOT_RTU0                          0x0010    //Combined context (MSMC + Desc) for Host Tx queue\r
-#define HOST_Q7_CONTEXT_SLOT_RTU0_SIZE                     0x1\r
-#define RTU0_BSRAM_END_OFFSET                              0x0011\r
-\r
-// total RTU0_BSRAM memory usage : 0.53125 KB from total of 16.0KB \r
-\r
-//************************************************************************************\r
-//\r
-// Memory Usage of : RTU1_BSRAM\r
-//\r
-//************************************************************************************\r
-\r
-#define RTU1_BSRAM_START_OFFSET                            0x0000\r
-#define RTU1_BS_OFFSETS_END                                0x0000    //_Small_Description_\r
-#define RTU1_BSRAM_END_OFFSET                              0x0000\r
-\r
-// total RTU1_BSRAM memory usage : 0.0 KB from total of 16.0KB \r
-\r
-//************************************************************************************\r
-//\r
-// Memory Usage of : PA_STAT\r
-//\r
-//************************************************************************************\r
-\r
-#define PA_STAT_START_OFFSET                               0x0000\r
-#define PA_STAT_64b_START_OFFSET                           0x0000    //Start of 64 bits PA_STAT counters\r
-#define NRT_HOST_RX_BYTE_COUNT_PASTATID                    0x0000    //Number of valid bytes sent by Rx PRU to Host on PSI. Currently disabled\r
-#define NRT_HOST_RX_BYTE_COUNT_PASTATID_SIZE               0x8\r
-#define NRT_HOST_TX_BYTE_COUNT_PASTATID                    0x0008    //Number of valid bytes copied by RTU0 to Tx queues. Currently disabled\r
-#define NRT_HOST_TX_BYTE_COUNT_PASTATID_SIZE               0x8\r
-#define PA_STAT_32b_START_OFFSET                           0x0080    //Start of 32 bits PA_STAT counters\r
-#define NRT_HOST_RX_PKT_COUNT_PASTATID                     0x0080    //Number of valid packets sent by Rx PRU to Host on PSI\r
-#define NRT_HOST_RX_PKT_COUNT_PASTATID_SIZE                0x4\r
-#define NRT_HOST_TX_PKT_COUNT_PASTATID                     0x0084    //Number of valid packets copied by RTU0 to Tx queues\r
-#define NRT_HOST_TX_PKT_COUNT_PASTATID_SIZE                0x4\r
-#define NRT_RTU0_PACKET_DROPPED_PASTATID                   0x0088    //PRU diagnostic error counter which increments when RTU0 drops a locally injected packet due to port disabled or rule violation\r
-#define NRT_RTU0_PACKET_DROPPED_PASTATID_SIZE              0x4\r
-#define NRT_PORT_Q0_OVERFLOW_PASTATID                      0x008C    //Port Tx Q Overflow Counters\r
-#define NRT_PORT_Q0_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_PORT_Q1_OVERFLOW_PASTATID                      0x0090    //Port Tx Q Overflow Counters\r
-#define NRT_PORT_Q1_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_PORT_Q2_OVERFLOW_PASTATID                      0x0094    //Port Tx Q Overflow Counters\r
-#define NRT_PORT_Q2_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_PORT_Q3_OVERFLOW_PASTATID                      0x0098    //Port Tx Q Overflow Counters\r
-#define NRT_PORT_Q3_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_PORT_Q4_OVERFLOW_PASTATID                      0x009C    //Port Tx Q Overflow Counters\r
-#define NRT_PORT_Q4_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_PORT_Q5_OVERFLOW_PASTATID                      0x00A0    //Port Tx Q Overflow Counters\r
-#define NRT_PORT_Q5_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_PORT_Q6_OVERFLOW_PASTATID                      0x00A4    //Port Tx Q Overflow Counters\r
-#define NRT_PORT_Q6_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_PORT_Q7_OVERFLOW_PASTATID                      0x00A8    //Port Tx Q Overflow Counters\r
-#define NRT_PORT_Q7_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_HOST_Q0_OVERFLOW_PASTATID                      0x00AC    //Host Tx Q Overflow Counters\r
-#define NRT_HOST_Q0_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_HOST_Q1_OVERFLOW_PASTATID                      0x00B0    //Host Tx Q Overflow Counters\r
-#define NRT_HOST_Q1_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_HOST_Q2_OVERFLOW_PASTATID                      0x00B4    //Host Tx Q Overflow Counters\r
-#define NRT_HOST_Q2_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_HOST_Q3_OVERFLOW_PASTATID                      0x00B8    //Host Tx Q Overflow Counters\r
-#define NRT_HOST_Q3_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_HOST_Q4_OVERFLOW_PASTATID                      0x00BC    //Host Tx Q Overflow Counters\r
-#define NRT_HOST_Q4_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_HOST_Q5_OVERFLOW_PASTATID                      0x00C0    //Host Tx Q Overflow Counters\r
-#define NRT_HOST_Q5_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_HOST_Q6_OVERFLOW_PASTATID                      0x00C4    //Host Tx Q Overflow Counters\r
-#define NRT_HOST_Q6_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_HOST_Q7_OVERFLOW_PASTATID                      0x00C8    //Host Tx Q Overflow Counters\r
-#define NRT_HOST_Q7_OVERFLOW_PASTATID_SIZE                 0x4\r
-#define NRT_HOST_EGRESS_Q_PRE_OVERFLOW_PASTATID            0x00CC    //Host Egress Q (Pre-emptible) Overflow Counter\r
-#define NRT_HOST_EGRESS_Q_PRE_OVERFLOW_PASTATID_SIZE       0x4\r
-#define NRT_HOST_EGRESS_Q_EXP_OVERFLOW_PASTATID            0x00D0    //Host Egress Q (Express) Overflow Counter. redundant\r
-#define NRT_HOST_EGRESS_Q_EXP_OVERFLOW_PASTATID_SIZE       0x4\r
-#define NRT_PSI_ABORT_CNT_PASTATID                         0x00D4    //_Small_Description_\r
-#define NRT_PSI_ABORT_CNT_PASTATID_SIZE                    0x4\r
-#define NRT_WRONG_Q_STATUS_PASTATID                        0x00D8    //Not Used, will be removed\r
-#define NRT_WRONG_Q_STATUS_PASTATID_SIZE                   0x4\r
-#define NRT_DROPPED_PKT_PASTATID                           0x00DC    //Incremented if a packet is dropped because of a rule violation\r
-#define NRT_DROPPED_PKT_PASTATID_SIZE                      0x4\r
-#define NRT_RX_ERROR_PASTATID                              0x00E0    //Incremented if there was a CRC error or Min/Max frame error\r
-#define NRT_RX_ERROR_PASTATID_SIZE                         0x4\r
-#define RX_EOF_RTU_DS_INVALID_PASTATID                     0x00E4    //RTU diagnostic counter increments when RTU detects Data Status invalid condition\r
-#define RX_EOF_RTU_DS_INVALID_PASTATID_SIZE                0x4\r
-#define RX_B1_NRT_ENTRY_PASTATID                           0x00E8    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] PRU diagnostic counter which increments when NRT path of RX_B1 handling is invoked\r
-#define RX_B1_NRT_ENTRY_PASTATID_SIZE                      0x4\r
-#define RX_Bn_NRT_ENTRY_PASTATID                           0x00EC    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] PRU diagnostic counter which increments when NRT path of RX_Bn handling is invoked\r
-#define RX_Bn_NRT_ENTRY_PASTATID_SIZE                      0x4\r
-#define RX_EOF_NRT_ENTRY_PASTATID                          0x00F0    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] PRU diagnostic counter which increments when NRT path of RX_EOF handling is invoked\r
-#define RX_EOF_NRT_ENTRY_PASTATID_SIZE                     0x4\r
-#define NRT_TX_DROPPED_PACKET_PASTATID                     0x00F4    //Counter for packets dropped via NRT TX path\r
-#define NRT_TX_DROPPED_PACKET_PASTATID_SIZE                0x4\r
-#define NRT_TX_TS_DROPPED_PACKET_PASTATID                  0x00F8    //Counter for packets with TS flag dropped via NRT TX path\r
-#define NRT_TX_TS_DROPPED_PACKET_PASTATID_SIZE             0x4\r
-#define NRT_INF_PORT_DISABLED_PASTATID                     0x00FC    //PRU diagnostic error counter which increments when RX frame is dropped due to port is disabled\r
-#define NRT_INF_PORT_DISABLED_PASTATID_SIZE                0x4\r
-#define NRT_INF_SAV_PASTATID                               0x0100    //PRU diagnostic error counter which increments when RX frame is dropped due to SA violation\r
-#define NRT_INF_SAV_PASTATID_SIZE                          0x4\r
-#define NRT_INF_SA_BL_PASTATID                             0x0104    //PRU diagnostic error counter which increments when RX frame is dropped due to SA black listed\r
-#define NRT_INF_SA_BL_PASTATID_SIZE                        0x4\r
-#define NRT_INF_PORT_BLOCKED_PASTATID                      0x0108    //PRU diagnostic error counter which increments when RX frame is dropped due to port blocked and not a special frame\r
-#define NRT_INF_PORT_BLOCKED_PASTATID_SIZE                 0x4\r
-#define NRT_INF_AFT_DROP_TAGGED_PASTATID                   0x010C    //PRU diagnostic error counter which increments when RX frame is dropped due to tagged\r
-#define NRT_INF_AFT_DROP_TAGGED_PASTATID_SIZE              0x4\r
-#define NRT_INF_AFT_DROP_PRIOTAGGED_PASTATID               0x0110    //PRU diagnostic error counter which increments when RX frame is dropped due to priority tagged\r
-#define NRT_INF_AFT_DROP_PRIOTAGGED_PASTATID_SIZE          0x4\r
-#define NRT_INF_AFT_DROP_NOTAG_PASTATID                    0x0114    //PRU diagnostic error counter which increments when RX frame is dropped due to untagged\r
-#define NRT_INF_AFT_DROP_NOTAG_PASTATID_SIZE               0x4\r
-#define NRT_INF_AFT_DROP_NOTMEMBER_PASTATID                0x0118    //PRU diagnostic error counter which increments when RX frame is dropped due to port not member of VLAN\r
-#define NRT_INF_AFT_DROP_NOTMEMBER_PASTATID_SIZE           0x4\r
-#define NRT_FDB_NO_SPACE_TO_LEARN                          0x011C    //PRU diagnostic error counter which increments when an entry couldn't be learned\r
-#define NRT_FDB_NO_SPACE_TO_LEARN_SIZE                     0x4\r
-#define NRT_FDB_LAST_ENTRY_OVERWRITTEN_FOR_LEARNING        0x0120    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] PRU diagnostic error counter which increments when the fourth entry is overwritten to accomodate leart MAC\r
-#define NRT_FDB_LAST_ENTRY_OVERWRITTEN_FOR_LEARNING_SIZE   0x4\r
-#define NRT_PREEMPT_BAD_FRAG_PASTATID                      0x0124    //Bad fragment Error Counter\r
-#define NRT_PREEMPT_BAD_FRAG_PASTATID_SIZE                 0x4\r
-#define NRT_PREEMPT_ASSEMBLY_ERROR_PASTATID                0x0128    //Fragment assembly Error Counter\r
-#define NRT_PREEMPT_ASSEMBLY_ERROR_PASTATID_SIZE           0x4\r
-#define NRT_PREEMPT_FRAG_COUNT_TX_PASTATID                 0x012C    //Fragment count in TX\r
-#define NRT_PREEMPT_FRAG_COUNT_TX_PASTATID_SIZE            0x4\r
-#define NRT_PREEMPT_ASSEMBLY_OK_PASTATID                   0x0130    //Assembly Completed\r
-#define NRT_PREEMPT_ASSEMBLY_OK_PASTATID_SIZE              0x4\r
-#define NRT_PREEMPT_FRAG_COUNT_RX_PASTATID                 0x0134    //Fragments received\r
-#define NRT_PREEMPT_FRAG_COUNT_RX_PASTATID_SIZE            0x4\r
-#define NRT_PREEMPT_DEBUG_GLOBAL_ERROR                     0x0138    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] Global Debug Error Counter\r
-#define NRT_PREEMPT_DEBUG_GLOBAL_ERROR_SIZE                0x4\r
-#define NRT_PREEMPT_DEBUG_SMDCx_PASTATID                   0x013C    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] Debug counter SMDCx\r
-#define NRT_PREEMPT_DEBUG_SMDCx_PASTATID_SIZE              0x4\r
-#define NRT_PREEMPT_DEBUG_SMDSx_PASTATID                   0x0140    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] Debug counter SMDSx\r
-#define NRT_PREEMPT_DEBUG_SMDSx_PASTATID_SIZE              0x4\r
-#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAG0_ERROR_PASTATID    0x0144    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] Debug counter - Error in SMDSx\r
-#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAG0_ERROR_PASTATID_SIZE 0x4\r
-#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAGX_ERROR_PASTATID    0x0148    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] Debug counter - Error in SMDCx\r
-#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAGX_ERROR_PASTATID_SIZE 0x4\r
-#define PA_STAT_END_OFFSET                                 0x014C\r
-\r
-// total PA_STAT memory usage : 0.32421875 KB from total of 2.0KB \r
-\r
-\r
-#endif // ____switch_mem_map_h\r
+//***********************************************************************************
+//**+-----------------------------------------------------------------------------+**
+//**|                              ******                                         |**
+//**|                              ******     o                                   |**
+//**|                              *******__////__****                            |**
+//**|                              ***** /_ //___/ ***                            |**
+//**|                           ********* ////__ ******                           |**
+//**|                             *******(_____/ ******                           |**
+//**|                                 **********                                  |**
+//**|                                   ******                                    |**
+//**|                                      ***                                    |**
+//**|                                                                             |**
+//**|            Copyright (c) 2019 Texas Instruments Incorporated                |**
+//**|                           ALL RIGHTS RESERVED                               |**
+//**|                                                                             |**
+//**|    Permission is hereby granted to licensees of Texas Instruments           |**
+//**|    Incorporated (TI) products to use this computer program for the sole     |**
+//**|    purpose of implementing a licensee product based on TI products.         |**
+//**|    No other rights to reproduce, use, or disseminate this computer          |**
+//**|    program, whether in part or in whole, are granted.                       |**
+//**|                                                                             |**
+//**|    TI makes no representation or warranties with respect to the             |**
+//**|    performance of this computer program, and specifically disclaims         |**
+//**|    any responsibility for any damages, special or consequential,            |**
+//**|    connected with the use of this program.                                  |**
+//**|                                                                             |**
+//**+-----------------------------------------------------------------------------+**
+//***********************************************************************************
+// file:     switch_mem_map.h
+//
+// brief:    Contains memory map for Ethernet Switch.
+//           This file is shared by firmware and driver.
+
+#ifndef ____switch_mem_map_h
+#define ____switch_mem_map_h 1
+
+#include "switch_mmap_defines.h"
+
+//************************************************************************************
+//
+// Memory Usage of : SHARED_MEMORY
+//
+//************************************************************************************
+
+#define SHARED_MEMORY_START_OFFSET                         0x0000
+#define PRE_EMPTION_CONTEXT_OFFSET                         0x0000    //Backup of active Tx and Q context. The offset is not used
+#define PRE_EMPTION_CONTEXT_OFFSET_SIZE                    0x8
+#define FW_HOST_HANDSHAKE_MAGIC_VAL_OFFSET                 0x0008    //Firmware host handshake
+#define FW_HOST_HANDSHAKE_MAGIC_VAL_OFFSET_SIZE            0x4
+#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET                  0x000C    //Base Flow ID for sending packets to Host
+#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET_SIZE             0x2
+#define EMAC_ICSSG_SWITCH_PSI_L_REGULAR_FLOW_ID_BASE_OFFSET PSI_L_REGULAR_FLOW_ID_BASE_OFFSET    //Same as PSI_L_REGULAR_FLOW_ID_BASE_OFFSET
+#define PSI_L_MGMT_FLOW_ID_OFFSET                          0x000E    //Base Flow ID for sending mgmt and Tx TS to Host
+#define PSI_L_MGMT_FLOW_ID_OFFSET_SIZE                     0x2
+#define EMAC_ICSSG_SWITCH_PSI_L_MGMT_FLOW_ID_BASE_OFFSET   PSI_L_MGMT_FLOW_ID_OFFSET    //Same as PSI_L_MGMT_FLOW_ID_OFFSET
+#define SPL_PKT_DEFAULT_PRIORITY                           0x0010    //Queue number for Special packets written here. Only 1B is used
+#define SPL_PKT_DEFAULT_PRIORITY_SIZE                      0x4
+#define FDB_SA_MAC_ADDRESS                                 0x0014    //Used internally by FW for learning
+#define FDB_SA_MAC_ADDRESS_SIZE                            0x8
+#define FDB_FID_FIDC2_OFFSET                               0x001C    //Used internally by FW for learning
+#define FDB_FID_FIDC2_OFFSET_SIZE                          0x4
+#define FDB_BUCKET_OFFSET                                  0x0020    //Used internally by FW for learning
+#define FDB_BUCKET_OFFSET_SIZE                             0x4
+#define FDB_AGEING_LAST_USED_OFFSET                        0x0024    //Used internally by FW for learning
+#define FDB_AGEING_LAST_USED_OFFSET_SIZE                   0x4
+#define TX_SOF_TS_OFFSET                                   0x0028    //Used internally by FW to store Tx timestamp
+#define TX_SOF_TS_OFFSET_SIZE                              0x8
+#define TX_TS_COOKIE_OFFSET                                0x0030    //Used internally by FW to stash cookie
+#define TX_TS_COOKIE_OFFSET_SIZE                           0x4
+#define HOST_PORT_DF_VLAN_OFFSET                           0x0034    //default VLAN tag for Host Port
+#define HOST_PORT_DF_VLAN_OFFSET_SIZE                      0x4
+#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET        HOST_PORT_DF_VLAN_OFFSET    //Same as HOST_PORT_DF_VLAN_OFFSET
+#define P1_PORT_DF_VLAN_OFFSET                             0x0038    //default VLAN tag for P1 Port
+#define P1_PORT_DF_VLAN_OFFSET_SIZE                        0x4
+#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET        P1_PORT_DF_VLAN_OFFSET    //Same as P1_PORT_DF_VLAN_OFFSET
+#define P2_PORT_DF_VLAN_OFFSET                             0x003C    //default VLAN tag for P2 Port
+#define P2_PORT_DF_VLAN_OFFSET_SIZE                        0x4
+#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET        P2_PORT_DF_VLAN_OFFSET    //Same as P2_PORT_DF_VLAN_OFFSET
+#define RX_TS_STASHED                                      0x0040    //Used internally by FW for stashed Rx timestamp
+#define RX_TS_STASHED_SIZE                                 0x8
+#define MGR_CMD_OFFSET                                     0x0048    //Management command from Host to RTU0
+#define MGR_CMD_OFFSET_SIZE                                0x20
+#define MGR_CMD_RET                                        0x0068    //Management reply to Host from RTU0
+#define MGR_CMD_RET_SIZE                                   0xc
+#define MGR_CMD_STATE                                      0x0074    //0 - idle; 1 - todo; 2 - executing
+#define MGR_CMD_STATE_SIZE                                 0x1
+//Padding of 3 bytes
+#define MGR_CMD_PRU0_STATUS                                0x0078    //Used internally by FW to communicate from RTU0 to PRU0
+#define MGR_CMD_PRU0_STATUS_SIZE                           0x2
+#define MGR_CMD_PRU1_STATUS                                0x007A    //Used internally by FW to communicate from RTU0 to PRU1
+#define MGR_CMD_PRU1_STATUS_SIZE                           0x2
+#define MGR_CMD_RTU0_STATUS                                0x007C    //Used internally by FW to communicate from RTU0 to RTU0
+#define MGR_CMD_RTU0_STATUS_SIZE                           0x2
+#define MGR_CMD_RTU1_STATUS                                0x007E    //Used internally by FW to for management state machine
+#define MGR_CMD_RTU1_STATUS_SIZE                           0x42
+#define MGR_CMD_END_OFFSET                                 0x00C0    //End of Management command region
+#define PORT_Q0_RD_PTR_OFFSET                              0x0100    //Port Tx Q0 MSMC Read pointer stored here
+#define PORT_Q0_RD_PTR_OFFSET_SIZE                         0x4
+#define EMAC_ICSSG_SWITCH_PORT_QUEUE_READ_PTR_OFFSET       PORT_Q0_RD_PTR_OFFSET    //Same as PORT_Q0_RD_PTR_OFFSET
+#define PORT_Q1_RD_PTR_OFFSET                              0x0104    //Port Tx Q1 MSMC Read pointer stored here
+#define PORT_Q1_RD_PTR_OFFSET_SIZE                         0x4
+#define PORT_Q2_RD_PTR_OFFSET                              0x0108    //Port Tx Q2 MSMC Read pointer stored here
+#define PORT_Q2_RD_PTR_OFFSET_SIZE                         0x4
+#define PORT_Q3_RD_PTR_OFFSET                              0x010C    //Port Tx Q3 MSMC Read pointer stored here
+#define PORT_Q3_RD_PTR_OFFSET_SIZE                         0x4
+#define PORT_Q4_RD_PTR_OFFSET                              0x0110    //Port Tx Q4 MSMC Read pointer stored here
+#define PORT_Q4_RD_PTR_OFFSET_SIZE                         0x4
+#define PORT_Q5_RD_PTR_OFFSET                              0x0114    //Port Tx Q5 MSMC Read pointer stored here
+#define PORT_Q5_RD_PTR_OFFSET_SIZE                         0x4
+#define PORT_Q6_RD_PTR_OFFSET                              0x0118    //Port Tx Q6 MSMC Read pointer stored here
+#define PORT_Q6_RD_PTR_OFFSET_SIZE                         0x4
+#define PORT_Q7_RD_PTR_OFFSET                              0x011C    //Port Tx Q1 MSMC Read pointer stored here
+#define PORT_Q7_RD_PTR_OFFSET_SIZE                         0x4
+#define HOST_Q0_RD_PTR_OFFSET                              0x0120    //Host Tx Q0 MSMC Read pointer stored here
+#define HOST_Q0_RD_PTR_OFFSET_SIZE                         0x4
+#define HOST_Q1_RD_PTR_OFFSET                              0x0124    //Host Tx Q1 MSMC Read pointer stored here
+#define HOST_Q1_RD_PTR_OFFSET_SIZE                         0x4
+#define HOST_Q2_RD_PTR_OFFSET                              0x0128    //Host Tx Q2 MSMC Read pointer stored here
+#define HOST_Q2_RD_PTR_OFFSET_SIZE                         0x4
+#define HOST_Q3_RD_PTR_OFFSET                              0x012C    //Host Tx Q3 MSMC Read pointer stored here
+#define HOST_Q3_RD_PTR_OFFSET_SIZE                         0x4
+#define HOST_Q4_RD_PTR_OFFSET                              0x0130    //Host Tx Q4 MSMC Read pointer stored here
+#define HOST_Q4_RD_PTR_OFFSET_SIZE                         0x4
+#define HOST_Q5_RD_PTR_OFFSET                              0x0134    //Host Tx Q5 MSMC Read pointer stored here
+#define HOST_Q5_RD_PTR_OFFSET_SIZE                         0x4
+#define HOST_Q6_RD_PTR_OFFSET                              0x0138    //Host Tx Q6 MSMC Read pointer stored here
+#define HOST_Q6_RD_PTR_OFFSET_SIZE                         0x4
+#define HOST_Q7_RD_PTR_OFFSET                              0x013C    //Host Tx Q7 MSMC Read pointer stored here
+#define HOST_Q7_RD_PTR_OFFSET_SIZE                         0x4
+#define HOST_RX_PRE_RD_PTR_OFFSET                          0x0140    //Host Egress Q MSMC Read pointer (for Pre-emptive queue) stored here
+#define HOST_RX_PRE_RD_PTR_OFFSET_SIZE                     0x4
+#define EMAC_ICSSG_SWITCH_HOST_QUEUE_READ_PTR_OFFSET       HOST_RX_PRE_RD_PTR_OFFSET    //Same as HOST_RX_PRE_RD_PTR_OFFSET
+#define HOST_RX_PRE_WR_PTR_OFFSET                          0x0144    //Host Egress Q MSMC Write pointer (for Pre-emptive queue) stored here
+#define HOST_RX_PRE_WR_PTR_OFFSET_SIZE                     0x4
+#define HOST_RX_EXP_RD_PTR_OFFSET                          0x0148    //Reserved for Future Use
+#define HOST_RX_EXP_RD_PTR_OFFSET_SIZE                     0x4
+#define HOST_RX_EXP_WR_PTR_OFFSET                          0x014C    //Reserved for Future Use
+#define HOST_RX_EXP_WR_PTR_OFFSET_SIZE                     0x4
+#define PORT_Q0_DESC_RD_PTR_OFFSET                         0x0150    //Port Tx Q0 Desc Read pointer stored here
+#define PORT_Q0_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q0_DESC_WR_PTR_OFFSET                         0x0152    //Port Tx Q0 Desc Write pointer stored here
+#define PORT_Q0_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q1_DESC_RD_PTR_OFFSET                         0x0154    //Port Tx Q1 Desc Read pointer stored here
+#define PORT_Q1_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q1_DESC_WR_PTR_OFFSET                         0x0156    //Port Tx Q1 Desc Write pointer stored here
+#define PORT_Q1_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q2_DESC_RD_PTR_OFFSET                         0x0158    //Port Tx Q2 Desc Read pointer stored here
+#define PORT_Q2_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q2_DESC_WR_PTR_OFFSET                         0x015A    //Port Tx Q2 Desc Write pointer stored here
+#define PORT_Q2_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q3_DESC_RD_PTR_OFFSET                         0x015C    //Port Tx Q3 Desc Read pointer stored here
+#define PORT_Q3_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q3_DESC_WR_PTR_OFFSET                         0x015E    //Port Tx Q3 Desc Write pointer stored here
+#define PORT_Q3_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q4_DESC_RD_PTR_OFFSET                         0x0160    //Port Tx Q4 Desc Read pointer stored here
+#define PORT_Q4_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q4_DESC_WR_PTR_OFFSET                         0x0162    //Port Tx Q4 Desc Write pointer stored here
+#define PORT_Q4_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q5_DESC_RD_PTR_OFFSET                         0x0164    //Port Tx Q5 Desc Read pointer stored here
+#define PORT_Q5_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q5_DESC_WR_PTR_OFFSET                         0x0166    //Port Tx Q5 Desc Write pointer stored here
+#define PORT_Q5_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q6_DESC_RD_PTR_OFFSET                         0x0168    //Port Tx Q3 Desc Read pointer stored here
+#define PORT_Q6_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q6_DESC_WR_PTR_OFFSET                         0x016A    //Port Tx Q6 Desc Write pointer stored here
+#define PORT_Q6_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q7_DESC_RD_PTR_OFFSET                         0x016C    //Port Tx Q7 Desc Read pointer stored here
+#define PORT_Q7_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define PORT_Q7_DESC_WR_PTR_OFFSET                         0x016E    //Port Tx Q7 Desc Write pointer stored here
+#define PORT_Q7_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q0_DESC_RD_PTR_OFFSET                         0x0170    //Host Tx Q0 Desc Read pointer stored here
+#define HOST_Q0_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q0_DESC_WR_PTR_OFFSET                         0x0172    //Host Tx Q0 Desc Write pointer stored here
+#define HOST_Q0_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q1_DESC_RD_PTR_OFFSET                         0x0174    //Host Tx Q1 Desc Read pointer stored here
+#define HOST_Q1_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q1_DESC_WR_PTR_OFFSET                         0x0176    //Host Tx Q1 Desc Write pointer stored here
+#define HOST_Q1_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q2_DESC_RD_PTR_OFFSET                         0x0178    //Host Tx Q2 Desc Read pointer stored here
+#define HOST_Q2_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q2_DESC_WR_PTR_OFFSET                         0x017A    //Host Tx Q2 Desc Write pointer stored here
+#define HOST_Q2_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q3_DESC_RD_PTR_OFFSET                         0x017C    //Host Tx Q3 Desc Read pointer stored here
+#define HOST_Q3_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q3_DESC_WR_PTR_OFFSET                         0x017E    //Host Tx Q3 Desc Write pointer stored here
+#define HOST_Q3_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q4_DESC_RD_PTR_OFFSET                         0x0180    //Host Tx Q4 Desc Read pointer stored here
+#define HOST_Q4_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q4_DESC_WR_PTR_OFFSET                         0x0182    //Host Tx Q4 Desc Write pointer stored here
+#define HOST_Q4_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q5_DESC_RD_PTR_OFFSET                         0x0184    //Host Tx Q5 Desc Read pointer stored here
+#define HOST_Q5_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q5_DESC_WR_PTR_OFFSET                         0x0186    //Host Tx Q5 Desc Write pointer stored here
+#define HOST_Q5_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q6_DESC_RD_PTR_OFFSET                         0x0188    //Host Tx Q6 Desc Read pointer stored here
+#define HOST_Q6_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q6_DESC_WR_PTR_OFFSET                         0x018A    //Host Tx Q6 Desc Write pointer stored here
+#define HOST_Q6_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q7_DESC_RD_PTR_OFFSET                         0x018C    //Host Tx Q7 Desc Read pointer stored here
+#define HOST_Q7_DESC_RD_PTR_OFFSET_SIZE                    0x2
+#define HOST_Q7_DESC_WR_PTR_OFFSET                         0x018E    //Host Tx Q7 Desc Write pointer stored here
+#define HOST_Q7_DESC_WR_PTR_OFFSET_SIZE                    0x2
+#define VLAN_STATIC_REG_TABLE_OFFSET                       0x0190    //VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000
+#define VLAN_STATIC_REG_TABLE_OFFSET_SIZE                  0x2000
+#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET        VLAN_STATIC_REG_TABLE_OFFSET    //VLAN-FID Table offset for EMAC
+#define SMEM_VLAN_END_OF_MEM                               0x2190    //End of VLAN-FID table marker
+#define SMEM_VLAN_END_OF_MEM_SIZE                          0x4
+#define PORT_Q0_CONTEXT_OFFSET                             0x2194    //16B for Port Tx MSMC Q context
+#define PORT_Q0_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define EMAC_ICSSG_SWITCH_PORT_QUEUE_CONTEXT_OFFSET        PORT_Q0_CONTEXT_OFFSET    //Same as PORT_Q0_CONTEXT_OFFSET
+#define PORT_Q1_CONTEXT_OFFSET                             0x21A4    //16B for Port Tx MSMC Q context
+#define PORT_Q1_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define PORT_Q2_CONTEXT_OFFSET                             0x21B4    //16B for Port Tx MSMC Q context
+#define PORT_Q2_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define PORT_Q3_CONTEXT_OFFSET                             0x21C4    //16B for Port Tx MSMC Q context
+#define PORT_Q3_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define PORT_Q4_CONTEXT_OFFSET                             0x21D4    //16B for Port Tx MSMC Q context
+#define PORT_Q4_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define PORT_Q5_CONTEXT_OFFSET                             0x21E4    //16B for Port Tx MSMC Q context
+#define PORT_Q5_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define PORT_Q6_CONTEXT_OFFSET                             0x21F4    //16B for Port Tx MSMC Q context
+#define PORT_Q6_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define PORT_Q7_CONTEXT_OFFSET                             0x2204    //16B for Port Tx MSMC Q context
+#define PORT_Q7_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q0_CONTEXT_OFFSET                             0x2214    //16B for Host Tx MSMC Q context
+#define HOST_Q0_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q1_CONTEXT_OFFSET                             0x2224    //16B for Host Tx MSMC Q context
+#define HOST_Q1_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q2_CONTEXT_OFFSET                             0x2234    //16B for Host Tx MSMC Q context
+#define HOST_Q2_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q3_CONTEXT_OFFSET                             0x2244    //16B for Host Tx MSMC Q context
+#define HOST_Q3_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q4_CONTEXT_OFFSET                             0x2254    //16B for Host Tx MSMC Q context
+#define HOST_Q4_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q5_CONTEXT_OFFSET                             0x2264    //16B for Host Tx MSMC Q context
+#define HOST_Q5_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q6_CONTEXT_OFFSET                             0x2274    //16B for Host Tx MSMC Q context
+#define HOST_Q6_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q7_CONTEXT_OFFSET                             0x2284    //16B for Host Tx MSMC Q context
+#define HOST_Q7_CONTEXT_OFFSET_SIZE                        (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_RX_Q_PRE_CONTEXT_OFFSET                       0x2294    //16B for Host Egress MSMC Q (Pre-emptible) context
+#define HOST_RX_Q_PRE_CONTEXT_OFFSET_SIZE                  (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_RX_Q_EXP_CONTEXT_OFFSET                       0x22A4    //16B for Host Egress MSMC Q (Express) context
+#define HOST_RX_Q_EXP_CONTEXT_OFFSET_SIZE                  (NRT_QUEUE_CONTEXT_SIZE) //0x10
+#define DEFAULT_MSMC_Q_OFFSET                              (HOST_RX_Q_EXP_CONTEXT_OFFSET + 12)    //End of NRT MSMC region.
+#define PORT_Q0_DESC_CONTEXT_OFFSET                        0x22B4    //16B for Port Tx Q Desc context
+#define PORT_Q0_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define EMAC_ICSSG_SWITCH_PORT_DESC_QUEUE_CONTEXT_OFFSET   PORT_Q0_DESC_CONTEXT_OFFSET    //Start of Queue Descriptors for EMAC
+#define PORT_Q1_DESC_CONTEXT_OFFSET                        0x22C4    //16B for Port Tx Q Desc context
+#define PORT_Q1_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define PORT_Q2_DESC_CONTEXT_OFFSET                        0x22D4    //16B for Port Tx Q Desc context
+#define PORT_Q2_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define PORT_Q3_DESC_CONTEXT_OFFSET                        0x22E4    //16B for Port Tx Q Desc context
+#define PORT_Q3_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define PORT_Q4_DESC_CONTEXT_OFFSET                        0x22F4    //16B for Port Tx Q Desc context
+#define PORT_Q4_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define PORT_Q5_DESC_CONTEXT_OFFSET                        0x2304    //16B for Port Tx Q Desc context
+#define PORT_Q5_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define PORT_Q6_DESC_CONTEXT_OFFSET                        0x2314    //16B for Port Tx Q Desc context
+#define PORT_Q6_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define PORT_Q7_DESC_CONTEXT_OFFSET                        0x2324    //16B for Port Tx Q Desc context
+#define PORT_Q7_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q0_DESC_CONTEXT_OFFSET                        0x2334    //16B for Port Tx Q Desc context
+#define HOST_Q0_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q1_DESC_CONTEXT_OFFSET                        0x2344    //16B for Host Tx Q Desc context
+#define HOST_Q1_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q2_DESC_CONTEXT_OFFSET                        0x2354    //16B for Host Tx Q Desc context
+#define HOST_Q2_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q3_DESC_CONTEXT_OFFSET                        0x2364    //16B for Host Tx Q Desc context
+#define HOST_Q3_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q4_DESC_CONTEXT_OFFSET                        0x2374    //16B for Host Tx Q Desc context
+#define HOST_Q4_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q5_DESC_CONTEXT_OFFSET                        0x2384    //16B for Host Tx Q Desc context
+#define HOST_Q5_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q6_DESC_CONTEXT_OFFSET                        0x2394    //16B for Host Tx Q Desc context
+#define HOST_Q6_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_Q7_DESC_CONTEXT_OFFSET                        0x23A4    //16B for Host Tx Q Desc context
+#define HOST_Q7_DESC_CONTEXT_OFFSET_SIZE                   (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_RX_Q_PRE_DESC_CONTEXT_OFFSET                  0x23B4    //16B for Host Egress Q (pre-emptible) Desc context
+#define HOST_RX_Q_PRE_DESC_CONTEXT_OFFSET_SIZE             (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define HOST_RX_Q_EXP_DESC_CONTEXT_OFFSET                  0x23C4    //16B for Host Egress Q (Express) Desc context. redundant
+#define HOST_RX_Q_EXP_DESC_CONTEXT_OFFSET_SIZE             (NRT_DESC_QUEUE_CONTEXT_SIZE) //0x10
+#define PORT_DESC_Q0_OFFSET                                0x23D4    //packet descriptor Q reserved memory
+#define PORT_DESC_Q0_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734
+#define PORT_DESC_Q1_OFFSET                                0x2B08    //packet descriptor Q reserved memory for Port Tx queues
+#define PORT_DESC_Q1_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734
+#define PORT_DESC_Q2_OFFSET                                0x323C    //packet descriptor Q reserved memory for Port Tx queues
+#define PORT_DESC_Q2_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734
+#define PORT_DESC_Q3_OFFSET                                0x3970    //packet descriptor Q reserved memory for Port Tx queues
+#define PORT_DESC_Q3_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734
+#define PORT_DESC_Q4_OFFSET                                0x40A4    //packet descriptor Q reserved memory for Port Tx queues
+#define PORT_DESC_Q4_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734
+#define PORT_DESC_Q5_OFFSET                                0x47D8    //packet descriptor Q reserved memory for Port Tx queues
+#define PORT_DESC_Q5_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734
+#define PORT_DESC_Q6_OFFSET                                0x4F0C    //packet descriptor Q reserved memory for Port Tx queues
+#define PORT_DESC_Q6_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734
+#define PORT_DESC_Q7_OFFSET                                0x5640    //packet descriptor Q reserved memory for Port Tx queues
+#define PORT_DESC_Q7_OFFSET_SIZE                           (NRT_PORT_DESC_QUEUE_SIZE) //0x734
+#define HOST_DESC_Q0_OFFSET                                0x5D74    //packet descriptor Q reserved memory for Host Tx queues
+#define HOST_DESC_Q0_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234
+#define HOST_DESC_Q1_OFFSET                                0x5FA8    //packet descriptor Q reserved memory for Host Tx queues
+#define HOST_DESC_Q1_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234
+#define HOST_DESC_Q2_OFFSET                                0x61DC    //packet descriptor Q reserved memory for Host Tx queues
+#define HOST_DESC_Q2_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234
+#define HOST_DESC_Q3_OFFSET                                0x6410    //packet descriptor Q reserved memory for Host Tx queues
+#define HOST_DESC_Q3_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234
+#define HOST_DESC_Q4_OFFSET                                0x6644    //packet descriptor Q reserved memory for Host Tx queues
+#define HOST_DESC_Q4_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234
+#define HOST_DESC_Q5_OFFSET                                0x6878    //packet descriptor Q reserved memory for Host Tx queues
+#define HOST_DESC_Q5_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234
+#define HOST_DESC_Q6_OFFSET                                0x6AAC    //packet descriptor Q reserved memory for Host Tx queues
+#define HOST_DESC_Q6_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234
+#define HOST_DESC_Q7_OFFSET                                0x6CE0    //packet descriptor Q reserved memory for Host Tx queues
+#define HOST_DESC_Q7_OFFSET_SIZE                           (NRT_HOST_DESC_QUEUE_SIZE) //0x234
+#define HOST_RX_DESC_Q_PRE_OFFSET                          0x6F14    //packet descriptor Q reserved memory for Host Egress (Pre-emptible) queues
+#define HOST_RX_DESC_Q_PRE_OFFSET_SIZE                     (NRT_PORT_DESC_QUEUE_SIZE) //0x734
+#define HOST_RX_DESC_Q_EXP_OFFSET                          0x7648    //packet descriptor Q reserved memory for Host Egress (Pre-emptible) queues. redundant
+#define HOST_RX_DESC_Q_EXP_OFFSET_SIZE                     (NRT_PORT_DESC_QUEUE_SIZE) //0x734
+#define SHARED_MEMORY_END_OFFSET                           0x7D7C
+
+// total SHARED_MEMORY memory usage : 31.37109375 KB from total of 64.0KB 
+
+//************************************************************************************
+//
+// Memory Usage of : MSMC
+//
+//************************************************************************************
+
+#define MSMC_START_OFFSET                                  0x0000
+#define MSMC_END_OFFSET                                    0x0000
+
+// total MSMC memory usage : 0.0 KB from total of 2048.0KB 
+
+//************************************************************************************
+//
+// Memory Usage of : DMEM0
+//
+//************************************************************************************
+
+#define DMEM0_START_OFFSET                                 0x0000
+#define PORT_Q_PRIORITY_REGEN_OFFSET                       0x0000    //Stores the table used for priority regeneration. 4B per PCP/Queue. Only 1B is used
+#define PORT_Q_PRIORITY_REGEN_OFFSET_SIZE                  0x20
+#define EXPRESS_PRE_EMPTIVE_Q_MAP                          0x0020    //For marking packet as priority/express (this feature is disabled) or cut-through/S&F. One per slice
+#define EXPRESS_PRE_EMPTIVE_Q_MAP_SIZE                     0x20
+#define TAS_CONFIG_CHANGE_TIME                             0x0040    //New list is copied at this time
+#define TAS_CONFIG_CHANGE_TIME_SIZE                        0x8
+#define TAS_CONFIG_CHANGE_ERROR_COUNTER                    0x0048    //config change error counter
+#define TAS_CONFIG_CHANGE_ERROR_COUNTER_SIZE               0x4
+#define TAS_CONFIG_PENDING                                 0x004C    //TAS List update pending flag
+#define TAS_CONFIG_PENDING_SIZE                            0x1
+#define TAS_CONFIG_CHANGE                                  0x004D    //TAS list update trigger flag
+#define TAS_CONFIG_CHANGE_SIZE                             0x1
+//Padding of 2 bytes
+#define TAS_ADMIN_CYCLE_TIME                               0x0050    //Cycle time for the new TAS schedule
+#define TAS_ADMIN_CYCLE_TIME_SIZE                          0x4
+#define TAS_CONFIG_CHANGE_CYCLE_COUNT                      0x0054    //Cycle counts remaining till the TAS list update
+#define TAS_CONFIG_CHANGE_CYCLE_COUNT_SIZE                 0x4
+#define TAS_SHADOW_EXPIRY_LIST_GATE0                       0x0100    //TAS gate expiry list for gate0
+#define TAS_SHADOW_EXPIRY_LIST_GATE0_SIZE                  0x20
+#define TAS_SHADOW_EXPIRY_LIST_GATE1                       0x0120    //TAS gate expiry list for gate1
+#define TAS_SHADOW_EXPIRY_LIST_GATE1_SIZE                  0x20
+#define TAS_SHADOW_EXPIRY_LIST_GATE2                       0x0140    //TAS gate expiry list for gate2
+#define TAS_SHADOW_EXPIRY_LIST_GATE2_SIZE                  0x20
+#define TAS_SHADOW_EXPIRY_LIST_GATE3                       0x0160    //TAS gate expiry list for gate3
+#define TAS_SHADOW_EXPIRY_LIST_GATE3_SIZE                  0x20
+#define TAS_SHADOW_EXPIRY_LIST_GATE4                       0x0180    //TAS gate expiry list for gate4
+#define TAS_SHADOW_EXPIRY_LIST_GATE4_SIZE                  0x20
+#define TAS_SHADOW_EXPIRY_LIST_GATE5                       0x01A0    //TAS gate expiry list for gate5
+#define TAS_SHADOW_EXPIRY_LIST_GATE5_SIZE                  0x20
+#define TAS_SHADOW_EXPIRY_LIST_GATE6                       0x01C0    //TAS gate expiry list for gate6
+#define TAS_SHADOW_EXPIRY_LIST_GATE6_SIZE                  0x20
+#define TAS_SHADOW_EXPIRY_LIST_GATE7                       0x01E0    //TAS gate expiry list for gate7
+#define TAS_SHADOW_EXPIRY_LIST_GATE7_SIZE                  0x20
+#define PRE_EMPTION_ENABLE_TX                              0x0200    //Memory to Enable/Disable Preemption on TX side
+#define PRE_EMPTION_ENABLE_TX_SIZE                         0x1
+#define PRE_EMPTION_ACTIVE_TX                              0x0201    //Active State of Preemption on TX side
+#define PRE_EMPTION_ACTIVE_TX_SIZE                         0x1
+#define PRE_EMPTION_ENABLE_VERIFY                          0x0202    //Memory to Enable/Disable Verify State Machine Preemption
+#define PRE_EMPTION_ENABLE_VERIFY_SIZE                     0x1
+#define PRE_EMPTION_VERIFY_STATUS                          0x0203    //Verify Status of State Machine
+#define PRE_EMPTION_VERIFY_STATUS_SIZE                     0x1
+#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE                   0x0204    //Non Final Fragment Size supported by Link Partner
+#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE_SIZE              0x2
+#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL                    0x0206    //Non Final Fragment Size supported by Firmware
+#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL_SIZE               0x1
+//Padding of 1 bytes
+#define PRE_EMPTION_VERIFY_TIME                            0x0208    //Time in ms the State machine waits for respond packet
+#define PRE_EMPTION_VERIFY_TIME_SIZE                       0x2
+#define DMEM0_END_OFFSET                                   0x020A
+
+// total DMEM0 memory usage : 0.509765625 KB from total of 8.0KB 
+
+//************************************************************************************
+//
+// Memory Usage of : DMEM1
+//
+//************************************************************************************
+
+#define DMEM1_START_OFFSET                                 0x0000
+#define ICSS_FIRMWARE_VERSION_OFFSET                       0x0000    //ICSSG Firmware version details
+#define ICSS_FIRMWARE_VERSION_OFFSET_SIZE                  0xc
+#define NRT_FRAME_PREEMPTION_ENABLE_OFFSET                 0x000C    //Memory used for Global enable and disable Frame Preemption
+#define NRT_FRAME_PREEMPTION_ENABLE_OFFSET_SIZE            0x4
+#define NRT_STASHED_Q_NUM_OFFSET                           0x0010    //Memory used for Stashing queue number during Host Egress in BG Task
+#define NRT_STASHED_Q_NUM_OFFSET_SIZE                      0x4
+#define PSI_TX_PKT_DATA_OFFSET                             0x0014    //Used Internally by FW. 
+#define PSI_TX_PKT_DATA_OFFSET_SIZE                        0x24
+#define LEARNING_WR_RD_COUNT_OFFSET                        0x0038    //Used Internally by FW to synchronize FDB Learning between RTU0 and PRU0 
+#define LEARNING_WR_RD_COUNT_OFFSET_SIZE                   0x4
+#define FDB_G0_M_G1_SLV_OFFSET                             0x003C    //Used Internally by FW to synchronize FDB Learning between two ICSSG's 
+#define FDB_G0_M_G1_SLV_OFFSET_SIZE                        0x4
+#define FDB_G1_M_G0_SLV_OFFSET                             0x0040    //Used Internally by FW to synchronize FDB Learning between two ICSSG's 
+#define FDB_G1_M_G0_SLV_OFFSET_SIZE                        0x4
+#define FDB_SYNC_ENTRY                                     0x0044    //Used to store the FDB entry one ICSSG learnt and one that needs to be communicated to other ICSSG 
+#define FDB_SYNC_ENTRY_SIZE                                0x10
+#define DEBUG_FDB_COMPARISON_MAC_VLAN                      0x0054    //Used for debugging FDB lookups, write the MAC and VLAN combination that is suspect. Currently disabled
+#define DEBUG_FDB_COMPARISON_MAC_VLAN_SIZE                 0x8
+#define DEBUG_FDB_RESULTS                                  0x005C    //The results of FBD lookup for Local injection are dumped here
+#define DEBUG_FDB_RESULTS_SIZE                             0xc
+#define FDB_AGEING_TIMEOUT_OFFSET                          0x0068    //Time after which FDB entries are checked for aged out values. Value in nanoseconds
+#define FDB_AGEING_TIMEOUT_OFFSET_SIZE                     0x8
+#define DMEM1_END_OFFSET                                   0x0100
+
+// total DMEM1 memory usage : 0.25 KB from total of 8.0KB 
+
+//************************************************************************************
+//
+// Memory Usage of : PRU0_BSRAM
+//
+//************************************************************************************
+
+#define PRU0_BSRAM_START_OFFSET                            0x0000
+#define PSI_TX_INFO_SLOT_PRU0                              0x0000    //Store PSI template for INFO chunk
+#define PSI_TX_INFO_SLOT_PRU0_SIZE                         0x1
+#define HOST_RX_PACKET_DESC_SLOT_PRU0                      0x0001    //Stores the PSI descriptor for packet being sent to Host
+#define HOST_RX_PACKET_DESC_SLOT_PRU0_SIZE                 0x1
+#define HOST_RX_PRE_CONTEXT_RD_SLOT_PRU0                   0x0002    //Contains context info for Host Egress Queue (pre-emptible). Used by read task
+#define HOST_RX_PRE_CONTEXT_RD_SLOT_PRU0_SIZE              0x1
+#define HOST_RX_PRE_CONTEXT_WR_SLOT_PRU0                   0x0003    //Contains context info for Host Egress Queue (pre-emptible). Used by write task
+#define HOST_RX_PRE_CONTEXT_WR_SLOT_PRU0_SIZE              0x1
+#define HOST_RX_EXP_CONTEXT_RD_SLOT_PRU0                   0x0004    //Contains context info for Host Egress Queue (express). redundant
+#define HOST_RX_EXP_CONTEXT_RD_SLOT_PRU0_SIZE              0x1
+#define HOST_RX_EXP_CONTEXT_WR_SLOT_PRU0                   0x0005    //Contains context info for Host Egress Queue (express). redundant
+#define HOST_RX_EXP_CONTEXT_WR_SLOT_PRU0_SIZE              0x1
+#define P0_FIRST_32B_PACKET_DATA                           0x0006    //Used to store 32B at the start of SOF
+#define P0_FIRST_32B_PACKET_DATA_SIZE                      0x1
+#define PRU0_BSRAM_END_OFFSET                              0x0007
+
+// total PRU0_BSRAM memory usage : 0.21875 KB from total of 4.0KB 
+
+//************************************************************************************
+//
+// Memory Usage of : PRU1_BSRAM
+//
+//************************************************************************************
+
+#define PRU1_BSRAM_START_OFFSET                            0x0000
+#define P1_FIRST_32B_PACKET_DATA                           0x0000    //redundant
+#define P1_FIRST_32B_PACKET_DATA_SIZE                      0x1
+#define TAS_BSRAM_EXPIRY_LIST0_GATE0                       0x0001    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST0_GATE0_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST0_GATE1                       0x0002    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST0_GATE1_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST0_GATE2                       0x0003    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST0_GATE2_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST0_GATE3                       0x0004    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST0_GATE3_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST0_GATE4                       0x0005    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST0_GATE4_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST0_GATE5                       0x0006    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST0_GATE5_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST0_GATE6                       0x0007    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST0_GATE6_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST0_GATE7                       0x0008    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST0_GATE7_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST1_GATE0                       0x0009    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST1_GATE0_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST1_GATE1                       0x000A    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST1_GATE1_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST1_GATE2                       0x000B    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST1_GATE2_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST1_GATE3                       0x000C    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST1_GATE3_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST1_GATE4                       0x000D    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST1_GATE4_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST1_GATE5                       0x000E    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST1_GATE5_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST1_GATE6                       0x000F    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST1_GATE6_SIZE                  0x1
+#define TAS_BSRAM_EXPIRY_LIST1_GATE7                       0x0010    //32B total for one gate.
+#define TAS_BSRAM_EXPIRY_LIST1_GATE7_SIZE                  0x1
+#define PORT_Q0_CONTEXT_SLOT_PRU1                          0x0011    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q0_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define PORT_Q1_CONTEXT_SLOT_PRU1                          0x0012    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q1_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define PORT_Q2_CONTEXT_SLOT_PRU1                          0x0013    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q2_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define PORT_Q3_CONTEXT_SLOT_PRU1                          0x0014    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q3_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define PORT_Q4_CONTEXT_SLOT_PRU1                          0x0015    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q4_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define PORT_Q5_CONTEXT_SLOT_PRU1                          0x0016    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q5_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define PORT_Q6_CONTEXT_SLOT_PRU1                          0x0017    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q6_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define PORT_Q7_CONTEXT_SLOT_PRU1                          0x0018    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q7_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define HOST_Q0_CONTEXT_SLOT_PRU1                          0x0019    //Combined context (MSMC + Desc) for Port Tx queue
+#define HOST_Q0_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define HOST_Q1_CONTEXT_SLOT_PRU1                          0x001A    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q1_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define HOST_Q2_CONTEXT_SLOT_PRU1                          0x001B    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q2_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define HOST_Q3_CONTEXT_SLOT_PRU1                          0x001C    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q3_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define HOST_Q4_CONTEXT_SLOT_PRU1                          0x001D    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q4_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define HOST_Q5_CONTEXT_SLOT_PRU1                          0x001E    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q5_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define HOST_Q6_CONTEXT_SLOT_PRU1                          0x001F    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q6_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define HOST_Q7_CONTEXT_SLOT_PRU1                          0x0020    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q7_CONTEXT_SLOT_PRU1_SIZE                     0x1
+#define PSI_TXTS_INFO_SLOT_PRU1                            0x0021    //Store Info chunk for Tx TS PSI transaction
+#define PSI_TXTS_INFO_SLOT_PRU1_SIZE                       0x1
+#define PRU1_BS_OFFSETS_END                                0x0022    //_Small_Description_
+#define PRU1_BSRAM_END_OFFSET                              0x0022
+
+// total PRU1_BSRAM memory usage : 1.0625 KB from total of 4.0KB 
+
+//************************************************************************************
+//
+// Memory Usage of : RTU0_BSRAM
+//
+//************************************************************************************
+
+#define RTU0_BSRAM_START_OFFSET                            0x0000
+#define PSI_MGR_INFO_SLOT_RTU0                             0x0000    //Stores Management Frame PSI Info chunk
+#define PSI_MGR_INFO_SLOT_RTU0_SIZE                        0x1
+#define PORT_Q0_CONTEXT_SLOT_RTU0                          0x0001    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q0_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define PORT_Q1_CONTEXT_SLOT_RTU0                          0x0002    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q1_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define PORT_Q2_CONTEXT_SLOT_RTU0                          0x0003    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q2_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define PORT_Q3_CONTEXT_SLOT_RTU0                          0x0004    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q3_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define PORT_Q4_CONTEXT_SLOT_RTU0                          0x0005    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q4_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define PORT_Q5_CONTEXT_SLOT_RTU0                          0x0006    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q5_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define PORT_Q6_CONTEXT_SLOT_RTU0                          0x0007    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q6_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define PORT_Q7_CONTEXT_SLOT_RTU0                          0x0008    //Combined context (MSMC + Desc) for Port Tx queue
+#define PORT_Q7_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define HOST_Q0_CONTEXT_SLOT_RTU0                          0x0009    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q0_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define HOST_Q1_CONTEXT_SLOT_RTU0                          0x000A    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q1_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define HOST_Q2_CONTEXT_SLOT_RTU0                          0x000B    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q2_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define HOST_Q3_CONTEXT_SLOT_RTU0                          0x000C    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q3_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define HOST_Q4_CONTEXT_SLOT_RTU0                          0x000D    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q4_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define HOST_Q5_CONTEXT_SLOT_RTU0                          0x000E    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q5_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define HOST_Q6_CONTEXT_SLOT_RTU0                          0x000F    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q6_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define HOST_Q7_CONTEXT_SLOT_RTU0                          0x0010    //Combined context (MSMC + Desc) for Host Tx queue
+#define HOST_Q7_CONTEXT_SLOT_RTU0_SIZE                     0x1
+#define RTU0_BSRAM_END_OFFSET                              0x0011
+
+// total RTU0_BSRAM memory usage : 0.53125 KB from total of 16.0KB 
+
+//************************************************************************************
+//
+// Memory Usage of : RTU1_BSRAM
+//
+//************************************************************************************
+
+#define RTU1_BSRAM_START_OFFSET                            0x0000
+#define RTU1_BS_OFFSETS_END                                0x0000    //_Small_Description_
+#define RTU1_BSRAM_END_OFFSET                              0x0000
+
+// total RTU1_BSRAM memory usage : 0.0 KB from total of 16.0KB 
+
+//************************************************************************************
+//
+// Memory Usage of : PA_STAT
+//
+//************************************************************************************
+
+#define PA_STAT_START_OFFSET                               0x0000
+#define PA_STAT_64b_START_OFFSET                           0x0000    //Start of 64 bits PA_STAT counters
+#define NRT_HOST_RX_BYTE_COUNT_PASTATID                    0x0000    //Number of valid bytes sent by Rx PRU to Host on PSI. Currently disabled
+#define NRT_HOST_RX_BYTE_COUNT_PASTATID_SIZE               0x2
+#define NRT_HOST_TX_BYTE_COUNT_PASTATID                    0x0002    //Number of valid bytes copied by RTU0 to Tx queues. Currently disabled
+#define NRT_HOST_TX_BYTE_COUNT_PASTATID_SIZE               0x2
+#define PA_STAT_32b_START_OFFSET                           0x0080    //Start of 32 bits PA_STAT counters
+#define NRT_HOST_RX_PKT_COUNT_PASTATID                     0x0080    //Number of valid packets sent by Rx PRU to Host on PSI
+#define NRT_HOST_RX_PKT_COUNT_PASTATID_SIZE                0x4
+#define NRT_HOST_TX_PKT_COUNT_PASTATID                     0x0084    //Number of valid packets copied by RTU0 to Tx queues
+#define NRT_HOST_TX_PKT_COUNT_PASTATID_SIZE                0x4
+#define NRT_RTU0_PACKET_DROPPED_PASTATID                   0x0088    //PRU diagnostic error counter which increments when RTU0 drops a locally injected packet due to port disabled or rule violation
+#define NRT_RTU0_PACKET_DROPPED_PASTATID_SIZE              0x4
+#define NRT_PORT_Q0_OVERFLOW_PASTATID                      0x008C    //Port Tx Q Overflow Counters
+#define NRT_PORT_Q0_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_PORT_Q1_OVERFLOW_PASTATID                      0x0090    //Port Tx Q Overflow Counters
+#define NRT_PORT_Q1_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_PORT_Q2_OVERFLOW_PASTATID                      0x0094    //Port Tx Q Overflow Counters
+#define NRT_PORT_Q2_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_PORT_Q3_OVERFLOW_PASTATID                      0x0098    //Port Tx Q Overflow Counters
+#define NRT_PORT_Q3_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_PORT_Q4_OVERFLOW_PASTATID                      0x009C    //Port Tx Q Overflow Counters
+#define NRT_PORT_Q4_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_PORT_Q5_OVERFLOW_PASTATID                      0x00A0    //Port Tx Q Overflow Counters
+#define NRT_PORT_Q5_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_PORT_Q6_OVERFLOW_PASTATID                      0x00A4    //Port Tx Q Overflow Counters
+#define NRT_PORT_Q6_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_PORT_Q7_OVERFLOW_PASTATID                      0x00A8    //Port Tx Q Overflow Counters
+#define NRT_PORT_Q7_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_HOST_Q0_OVERFLOW_PASTATID                      0x00AC    //Host Tx Q Overflow Counters
+#define NRT_HOST_Q0_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_HOST_Q1_OVERFLOW_PASTATID                      0x00B0    //Host Tx Q Overflow Counters
+#define NRT_HOST_Q1_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_HOST_Q2_OVERFLOW_PASTATID                      0x00B4    //Host Tx Q Overflow Counters
+#define NRT_HOST_Q2_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_HOST_Q3_OVERFLOW_PASTATID                      0x00B8    //Host Tx Q Overflow Counters
+#define NRT_HOST_Q3_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_HOST_Q4_OVERFLOW_PASTATID                      0x00BC    //Host Tx Q Overflow Counters
+#define NRT_HOST_Q4_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_HOST_Q5_OVERFLOW_PASTATID                      0x00C0    //Host Tx Q Overflow Counters
+#define NRT_HOST_Q5_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_HOST_Q6_OVERFLOW_PASTATID                      0x00C4    //Host Tx Q Overflow Counters
+#define NRT_HOST_Q6_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_HOST_Q7_OVERFLOW_PASTATID                      0x00C8    //Host Tx Q Overflow Counters
+#define NRT_HOST_Q7_OVERFLOW_PASTATID_SIZE                 0x4
+#define NRT_HOST_EGRESS_Q_PRE_OVERFLOW_PASTATID            0x00CC    //Host Egress Q (Pre-emptible) Overflow Counter
+#define NRT_HOST_EGRESS_Q_PRE_OVERFLOW_PASTATID_SIZE       0x4
+#define NRT_HOST_EGRESS_Q_EXP_OVERFLOW_PASTATID            0x00D0    //Host Egress Q (Express) Overflow Counter. redundant
+#define NRT_HOST_EGRESS_Q_EXP_OVERFLOW_PASTATID_SIZE       0x4
+#define NRT_PSI_ABORT_CNT_PASTATID                         0x00D4    //_Small_Description_
+#define NRT_PSI_ABORT_CNT_PASTATID_SIZE                    0x4
+#define NRT_WRONG_Q_STATUS_PASTATID                        0x00D8    //Not Used, will be removed
+#define NRT_WRONG_Q_STATUS_PASTATID_SIZE                   0x4
+#define NRT_DROPPED_PKT_PASTATID                           0x00DC    //Incremented if a packet is dropped because of a rule violation
+#define NRT_DROPPED_PKT_PASTATID_SIZE                      0x4
+#define NRT_RX_ERROR_PASTATID                              0x00E0    //Incremented if there was a CRC error or Min/Max frame error
+#define NRT_RX_ERROR_PASTATID_SIZE                         0x4
+#define RX_EOF_RTU_DS_INVALID_PASTATID                     0x00E4    //RTU diagnostic counter increments when RTU detects Data Status invalid condition
+#define RX_EOF_RTU_DS_INVALID_PASTATID_SIZE                0x4
+#define RX_B1_NRT_ENTRY_PASTATID                           0x00E8    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] PRU diagnostic counter which increments when NRT path of RX_B1 handling is invoked
+#define RX_B1_NRT_ENTRY_PASTATID_SIZE                      0x4
+#define RX_Bn_NRT_ENTRY_PASTATID                           0x00EC    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] PRU diagnostic counter which increments when NRT path of RX_Bn handling is invoked
+#define RX_Bn_NRT_ENTRY_PASTATID_SIZE                      0x4
+#define RX_EOF_NRT_ENTRY_PASTATID                          0x00F0    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] PRU diagnostic counter which increments when NRT path of RX_EOF handling is invoked
+#define RX_EOF_NRT_ENTRY_PASTATID_SIZE                     0x4
+#define NRT_TX_DROPPED_PACKET_PASTATID                     0x00F4    //Counter for packets dropped via NRT TX path
+#define NRT_TX_DROPPED_PACKET_PASTATID_SIZE                0x4
+#define NRT_TX_TS_DROPPED_PACKET_PASTATID                  0x00F8    //Counter for packets with TS flag dropped via NRT TX path
+#define NRT_TX_TS_DROPPED_PACKET_PASTATID_SIZE             0x4
+#define NRT_INF_PORT_DISABLED_PASTATID                     0x00FC    //PRU diagnostic error counter which increments when RX frame is dropped due to port is disabled
+#define NRT_INF_PORT_DISABLED_PASTATID_SIZE                0x4
+#define NRT_INF_SAV_PASTATID                               0x0100    //PRU diagnostic error counter which increments when RX frame is dropped due to SA violation
+#define NRT_INF_SAV_PASTATID_SIZE                          0x4
+#define NRT_INF_SA_BL_PASTATID                             0x0104    //PRU diagnostic error counter which increments when RX frame is dropped due to SA black listed
+#define NRT_INF_SA_BL_PASTATID_SIZE                        0x4
+#define NRT_INF_PORT_BLOCKED_PASTATID                      0x0108    //PRU diagnostic error counter which increments when RX frame is dropped due to port blocked and not a special frame
+#define NRT_INF_PORT_BLOCKED_PASTATID_SIZE                 0x4
+#define NRT_INF_AFT_DROP_TAGGED_PASTATID                   0x010C    //PRU diagnostic error counter which increments when RX frame is dropped due to tagged
+#define NRT_INF_AFT_DROP_TAGGED_PASTATID_SIZE              0x4
+#define NRT_INF_AFT_DROP_PRIOTAGGED_PASTATID               0x0110    //PRU diagnostic error counter which increments when RX frame is dropped due to priority tagged
+#define NRT_INF_AFT_DROP_PRIOTAGGED_PASTATID_SIZE          0x4
+#define NRT_INF_AFT_DROP_NOTAG_PASTATID                    0x0114    //PRU diagnostic error counter which increments when RX frame is dropped due to untagged
+#define NRT_INF_AFT_DROP_NOTAG_PASTATID_SIZE               0x4
+#define NRT_INF_AFT_DROP_NOTMEMBER_PASTATID                0x0118    //PRU diagnostic error counter which increments when RX frame is dropped due to port not member of VLAN
+#define NRT_INF_AFT_DROP_NOTMEMBER_PASTATID_SIZE           0x4
+#define NRT_FDB_NO_SPACE_TO_LEARN                          0x011C    //PRU diagnostic error counter which increments when an entry couldn't be learned
+#define NRT_FDB_NO_SPACE_TO_LEARN_SIZE                     0x4
+#define NRT_FDB_LAST_ENTRY_OVERWRITTEN_FOR_LEARNING        0x0120    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] PRU diagnostic error counter which increments when the fourth entry is overwritten to accomodate leart MAC
+#define NRT_FDB_LAST_ENTRY_OVERWRITTEN_FOR_LEARNING_SIZE   0x4
+#define NRT_PREEMPT_BAD_FRAG_PASTATID                      0x0124    //Bad fragment Error Counter
+#define NRT_PREEMPT_BAD_FRAG_PASTATID_SIZE                 0x4
+#define NRT_PREEMPT_ASSEMBLY_ERROR_PASTATID                0x0128    //Fragment assembly Error Counter
+#define NRT_PREEMPT_ASSEMBLY_ERROR_PASTATID_SIZE           0x4
+#define NRT_PREEMPT_FRAG_COUNT_TX_PASTATID                 0x012C    //Fragment count in TX
+#define NRT_PREEMPT_FRAG_COUNT_TX_PASTATID_SIZE            0x4
+#define NRT_PREEMPT_ASSEMBLY_OK_PASTATID                   0x0130    //Assembly Completed
+#define NRT_PREEMPT_ASSEMBLY_OK_PASTATID_SIZE              0x4
+#define NRT_PREEMPT_FRAG_COUNT_RX_PASTATID                 0x0134    //Fragments received
+#define NRT_PREEMPT_FRAG_COUNT_RX_PASTATID_SIZE            0x4
+#define NRT_PREEMPT_DEBUG_GLOBAL_ERROR                     0x0138    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] Global Debug Error Counter
+#define NRT_PREEMPT_DEBUG_GLOBAL_ERROR_SIZE                0x4
+#define NRT_PREEMPT_DEBUG_SMDCx_PASTATID                   0x013C    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] Debug counter SMDCx
+#define NRT_PREEMPT_DEBUG_SMDCx_PASTATID_SIZE              0x4
+#define NRT_PREEMPT_DEBUG_SMDSx_PASTATID                   0x0140    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] Debug counter SMDSx
+#define NRT_PREEMPT_DEBUG_SMDSx_PASTATID_SIZE              0x4
+#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAG0_ERROR_PASTATID    0x0144    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] Debug counter - Error in SMDSx
+#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAG0_ERROR_PASTATID_SIZE 0x4
+#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAGX_ERROR_PASTATID    0x0148    //[DEBUG_L2_DIAGNOSTICS |  not in release binary] Debug counter - Error in SMDCx
+#define NRT_PREEMPT_DEBUG_EOF_MPKT_FRAGX_ERROR_PASTATID_SIZE 0x4
+#define PA_STAT_END_OFFSET                                 0x014C
+
+// total PA_STAT memory usage : 0.32421875 KB from total of 2.0KB 
+
+
+#endif // ____switch_mem_map_h

diff --git a/firmware/icss_switch/bin/switch_mmap_defines.h b/firmware/icss_switch/bin/switch_mmap_defines.h
index 8e2a4705fe3d2d8e257cc4c82f7abe45b41111a1..e7d90b128bf648c1912dae229aeb4acecb68209c 100644 (file)
--- a/firmware/icss_switch/bin/switch_mmap_defines.h
+++ b/firmware/icss_switch/bin/switch_mmap_defines.h
@@ -1,131 +1,135 @@
-//***********************************************************************************\r
-//**+-----------------------------------------------------------------------------+**\r
-//**|                              ******                                         |**\r
-//**|                              ******     o                                   |**\r
-//**|                              *******__////__****                            |**\r
-//**|                              ***** /_ //___/ ***                            |**\r
-//**|                           ********* ////__ ******                           |**\r
-//**|                             *******(_____/ ******                           |**\r
-//**|                                 **********                                  |**\r
-//**|                                   ******                                    |**\r
-//**|                                      ***                                    |**\r
-//**|                                                                             |**\r
-//**|            Copyright (c) 2019 Texas Instruments Incorporated                |**\r
-//**|                           ALL RIGHTS RESERVED                               |**\r
-//**|                                                                             |**\r
-//**|    Permission is hereby granted to licensees of Texas Instruments           |**\r
-//**|    Incorporated (TI) products to use this computer program for the sole     |**\r
-//**|    purpose of implementing a licensee product based on TI products.         |**\r
-//**|    No other rights to reproduce, use, or disseminate this computer          |**\r
-//**|    program, whether in part or in whole, are granted.                       |**\r
-//**|                                                                             |**\r
-//**|    TI makes no representation or warranties with respect to the             |**\r
-//**|    performance of this computer program, and specifically disclaims         |**\r
-//**|    any responsibility for any damages, special or consequential,            |**\r
-//**|    connected with the use of this program.                                  |**\r
-//**|                                                                             |**\r
-//**+-----------------------------------------------------------------------------+**\r
-//***********************************************************************************\r
-// file:     switch_mmap_defines.h\r
-//\r
-// brief:    Contains common defines used in the memory map for Ethernet Switch.\r
-//           This file is shared by firmware and driver. Also includes common defines.\r
-\r
-#ifndef ____switch_mmap_defines_h\r
-#define ____switch_mmap_defines_h 1\r
-\r
-//**************************** Ethernet Switch Constants *****************************\r
-//all sizes in bytes except otherwise mentioned\r
-#define NRT_TX_Q_HIGH_OFFSET                    0x0000\r
-\r
-#define NRT_QUEUE_CONTEXT_SIZE                  (16)          \r
-#define NRT_DESC_QUEUE_CONTEXT_SIZE             (16)          \r
-#define NRT_PUSH_SIZE                           (32)\r
-#define PACKET_DESC_SIZE                        (4)\r
-#define BD_CUT_THROUGH_MAGIC_VALUE              (0xBB8)     //used to indicate cut-through. This is an illegal packet size and does not overlap\r
-#define NRT_PRE_EMPTION_SIZE_THRESHOLD          (64)\r
-\r
-#define R31_ERROR_BITS_MASK                     0x0188  //Mask for extracting CRC, Min/Max errors from R31 bits. Refer MII RT Spec\r
-\r
-#define RX_B0_QNUM_SPECIAL_VALUE                0xFF    //special pattern used to wait for IPC SPAD values from RTU0\r
-\r
-//queue numbers\r
-#define QUEUE_0                                 (0)\r
-#define QUEUE_1                                 (1)\r
-#define QUEUE_2                                 (2)\r
-#define QUEUE_3                                 (3)\r
-#define QUEUE_4                                 (4)\r
-#define QUEUE_5                                 (5)\r
-#define QUEUE_6                                 (6)\r
-#define QUEUE_7                                 (7)\r
-\r
-#define PORT_1_ID                               (1)\r
-#define PORT_2_ID                               (2)\r
-#define UNDIRECTED_PKT_ID                       (0)\r
-\r
-//MSMC queue sizes\r
-#define NRT_NUM_PORT_QUEUES                     (16)                //Number of Port Tx queues for both ports. 8 each\r
-#define NRT_NUM_HOST_QUEUES                     (16)                //Number of Host Tx queues for both ports. 8 each\r
-#define NRT_NUM_HOST_EGRESS_QUEUES              (4)                 //Number of Host Egress queues for both ports. 2 each\r
-#define NRT_PORT_QUEUE_SIZE                     (25 * 1024)         //25kB per port queue\r
-#define NRT_HOST_QUEUE_SIZE                     (6400)              //~6.5kB per host queue\r
-#define NRT_RESERVED_MEM                        (2048)\r
-\r
-//Descriptor Q sizes\r
-// See design doc. It's calculated as ((queue size) / 64) * 4 plus some additional descriptors for margin of safety\r
-#define NRT_PORT_DESC_QUEUE_SIZE                (((NRT_PORT_QUEUE_SIZE + NRT_RESERVED_MEM)/64) + 29) * 4     // for 25kB queue size\r
-#define NRT_HOST_DESC_QUEUE_SIZE                (((NRT_HOST_QUEUE_SIZE + NRT_RESERVED_MEM)/64) + 9) * 4   // for ~6kB queue size\r
-\r
-\r
-//TAS sizes\r
-#define TAS_LIST_EXPIRY_SIZE                    (8 * 8 * 4)        //8 queues * 8 expiry values (each queue has 8 expiry values) * 4 (size of expiry in bytes) = 256B\r
-\r
-#define MTU_SIZE                                (2048)\r
-\r
-//ageing interval in nanoseconds. 10ms\r
-#define FDB_AGEING_INTERVAL                      (0x989680)\r
-\r
-#define MII_INTC_RX_ERROR_MASK                  (0x13)      //Mask to extract CRC and Rx error from INCT bits 32-63\r
-//Bit 32 : PRU0_RX_ERR, 33 : PRU0_RX_ERR32, 36 : PRU0_RX_CRC\r
-\r
-//default priority for packets without VLAN tag and special packet type\r
-#define DEFAULT_P1_PRIORITY                     (0)         //default priority for P1\r
-#define DEFAULT_P2_PRIORITY                     (0)         //default priority for P2\r
-#define DEFAULT_HOST_PRIORITY                   (0)         //default priority for Host port\r
-\r
-//---------------------PSI packet types----------------------\r
-//They come in handy to match against R1, instead of comparing each bit field we do a single shot compare\r
-#define INFO_PKT_META_DATA                      (0x0f000011) //Info packet type meta data which comes in R1. It has bit 0 (sop), bit 4(lastw) set indicating it's the first and last packet of it's type\r
-\r
-#define INFO_PKT_TYPE                           (0x00)       //Info packet type in R1 metadata. R1.b2\r
-                                                             //it is first and last chunk of it's type. packet type is 0 and size is f or 15\r
-//Info packet has the following meta data inside\r
-//R2.t23 indicates if Host has inserted CRC in packet. Not used by switch\r
-//R4.b2 tells if it's a directed packet. R4.b2 = 0(undirected), R4.b2 = 1(directed. P1), R4.b2 = 2(directed. P2)\r
-                                                             \r
-#define CTRL_PKT_META_DATA                      (0x0f100011) //Control packet type meta data which comes in R1. It has bit 0 (sop), bit 4(lastw) set indicating it's the first and last packet of it's type\r
-\r
-#define CTRL_PKT_TYPE                           (0x10)       //Ctrl packet type in R1 metadata. R1.b2\r
-\r
-                                                             //it is first and last chunk of it's type. packet type is 0x10 and size is 15\r
-                                                             \r
-#define STATUS_PKT_META_DATA                    (0x0f180012) //Status packet type meta data which comes in R1. It has bit 0 (sop), bit 4(lastw) set indicating\r
-\r
-#define STATUS_PKT_TYPE                         (0x18)       //Status packet type in R1 metadata. R1.b2\r
-                                                             //it is first and last chunk of it's type. packet type is 0x18 and size is 15\r
-                                                             \r
-#define DATA_FIRST_PKT_META_DATA                (0x10140000) //Data packet type meta data which comes in R1. This is for the all chunks (except last) and \r
-                                                             //doesn't have lastw set. packet type is 0x14 and size is 15\r
-                                                             \r
-#define DATA_LAST_PKT_META_DATA                 (0x00140010) //Data packet type meta data which comes in R1. This is for the last chunk and has\r
-                                                             //lastw set. packet type is 0x14 and size is 0 because size determined by xout by widget\r
-                                                             \r
-#define DATA_LAST_PKT_META_DATA_EOP             (0x00140012) //Same as above but has eop also set\r
-                                                             \r
-#define DATA_PKT_TYPE                           (0x14)       //Data packet type in R1 metadata. R1.b2\r
-\r
-//FIXME : Temporary. Need to align with EMAC\r
-#define NRT_PACKET_DROP_TS_ERROR_CODE               (0xBAADF00D)\r
-\r
-#endif //____switch_mmap_defines_h\r
-\r
+//***********************************************************************************
+//**+-----------------------------------------------------------------------------+**
+//**|                              ******                                         |**
+//**|                              ******     o                                   |**
+//**|                              *******__////__****                            |**
+//**|                              ***** /_ //___/ ***                            |**
+//**|                           ********* ////__ ******                           |**
+//**|                             *******(_____/ ******                           |**
+//**|                                 **********                                  |**
+//**|                                   ******                                    |**
+//**|                                      ***                                    |**
+//**|                                                                             |**
+//**|            Copyright (c) 2019 Texas Instruments Incorporated                |**
+//**|                           ALL RIGHTS RESERVED                               |**
+//**|                                                                             |**
+//**|    Permission is hereby granted to licensees of Texas Instruments           |**
+//**|    Incorporated (TI) products to use this computer program for the sole     |**
+//**|    purpose of implementing a licensee product based on TI products.         |**
+//**|    No other rights to reproduce, use, or disseminate this computer          |**
+//**|    program, whether in part or in whole, are granted.                       |**
+//**|                                                                             |**
+//**|    TI makes no representation or warranties with respect to the             |**
+//**|    performance of this computer program, and specifically disclaims         |**
+//**|    any responsibility for any damages, special or consequential,            |**
+//**|    connected with the use of this program.                                  |**
+//**|                                                                             |**
+//**+-----------------------------------------------------------------------------+**
+//***********************************************************************************
+// file:     switch_mmap_defines.h
+//
+// brief:    Contains common defines used in the memory map for Ethernet Switch.
+//           This file is shared by firmware and driver. Also includes common defines.
+
+#ifndef ____switch_mmap_defines_h
+#define ____switch_mmap_defines_h 1
+
+//**************************** Ethernet Switch Constants *****************************
+//all sizes in bytes except otherwise mentioned
+#define NRT_TX_Q_HIGH_OFFSET                    0x0000
+
+#define NRT_QUEUE_CONTEXT_SIZE                  (16)          
+#define NRT_DESC_QUEUE_CONTEXT_SIZE             (16)          
+#define NRT_PUSH_SIZE                           (32)
+#define PACKET_DESC_SIZE                        (4)
+#define BD_CUT_THROUGH_MAGIC_VALUE              (0xBB8)     //used to indicate cut-through. This is an illegal packet size and does not overlap
+#define NRT_PRE_EMPTION_SIZE_THRESHOLD          (64)
+
+#define R31_ERROR_BITS_MASK                     0x0188  //Mask for extracting CRC, Min/Max errors from R31 bits. Refer MII RT Spec
+
+#define RX_B0_QNUM_SPECIAL_VALUE                0xFF    //special pattern used to wait for IPC SPAD values from RTU0
+
+//queue numbers
+#define QUEUE_0                                 (0)
+#define QUEUE_1                                 (1)
+#define QUEUE_2                                 (2)
+#define QUEUE_3                                 (3)
+#define QUEUE_4                                 (4)
+#define QUEUE_5                                 (5)
+#define QUEUE_6                                 (6)
+#define QUEUE_7                                 (7)
+
+#define PORT_1_ID                               (1)
+#define PORT_2_ID                               (2)
+#define UNDIRECTED_PKT_ID                       (0)
+
+//if bucket size is changed in firmware then this too should be changed
+//because it directly impacts FDB ageing calculation
+#define NUMBER_OF_FDB_BUCKET_ENTRIES            (4)
+#define SIZE_OF_FDB                             (2048)  //This is fixed in ICSSG
+//ageing interval in nanoseconds. 30s
+#define DEFAULT_FDB_AGEING_INTERVAL             (0x6FC23AC00)
+
+//MSMC queue sizes
+#define NRT_NUM_PORT_QUEUES                     (16)                //Number of Port Tx queues for both ports. 8 each
+#define NRT_NUM_HOST_QUEUES                     (16)                //Number of Host Tx queues for both ports. 8 each
+#define NRT_NUM_HOST_EGRESS_QUEUES              (4)                 //Number of Host Egress queues for both ports. 2 each
+#define NRT_PORT_QUEUE_SIZE                     (25 * 1024)         //25kB per port queue
+#define NRT_HOST_QUEUE_SIZE                     (6400)              //~6.5kB per host queue
+#define NRT_RESERVED_MEM                        (2048)
+
+//Descriptor Q sizes
+// See design doc. It's calculated as ((queue size) / 64) * 4 plus some additional descriptors for margin of safety
+#define NRT_PORT_DESC_QUEUE_SIZE                (((NRT_PORT_QUEUE_SIZE + NRT_RESERVED_MEM)/64) + 29) * 4     // for 25kB queue size
+#define NRT_HOST_DESC_QUEUE_SIZE                (((NRT_HOST_QUEUE_SIZE + NRT_RESERVED_MEM)/64) + 9) * 4   // for ~6kB queue size
+
+
+//TAS sizes
+#define TAS_LIST_EXPIRY_SIZE                    (8 * 8 * 4)        //8 queues * 8 expiry values (each queue has 8 expiry values) * 4 (size of expiry in bytes) = 256B
+
+#define MTU_SIZE                                (2048)
+
+#define MII_INTC_RX_ERROR_MASK                  (0x13)      //Mask to extract CRC and Rx error from INCT bits 32-63
+//Bit 32 : PRU0_RX_ERR, 33 : PRU0_RX_ERR32, 36 : PRU0_RX_CRC
+
+//default priority for packets without VLAN tag and special packet type
+#define DEFAULT_P1_PRIORITY                     (0)         //default priority for P1
+#define DEFAULT_P2_PRIORITY                     (0)         //default priority for P2
+#define DEFAULT_HOST_PRIORITY                   (0)         //default priority for Host port
+
+//---------------------PSI packet types----------------------
+//They come in handy to match against R1, instead of comparing each bit field we do a single shot compare
+#define INFO_PKT_META_DATA                      (0x0f000011) //Info packet type meta data which comes in R1. It has bit 0 (sop), bit 4(lastw) set indicating it's the first and last packet of it's type
+
+#define INFO_PKT_TYPE                           (0x00)       //Info packet type in R1 metadata. R1.b2
+                                                             //it is first and last chunk of it's type. packet type is 0 and size is f or 15
+//Info packet has the following meta data inside
+//R2.t23 indicates if Host has inserted CRC in packet. Not used by switch
+//R4.b2 tells if it's a directed packet. R4.b2 = 0(undirected), R4.b2 = 1(directed. P1), R4.b2 = 2(directed. P2)
+                                                             
+#define CTRL_PKT_META_DATA                      (0x0f100011) //Control packet type meta data which comes in R1. It has bit 0 (sop), bit 4(lastw) set indicating it's the first and last packet of it's type
+
+#define CTRL_PKT_TYPE                           (0x10)       //Ctrl packet type in R1 metadata. R1.b2
+
+                                                             //it is first and last chunk of it's type. packet type is 0x10 and size is 15
+                                                             
+#define STATUS_PKT_META_DATA                    (0x0f180012) //Status packet type meta data which comes in R1. It has bit 0 (sop), bit 4(lastw) set indicating
+
+#define STATUS_PKT_TYPE                         (0x18)       //Status packet type in R1 metadata. R1.b2
+                                                             //it is first and last chunk of it's type. packet type is 0x18 and size is 15
+                                                             
+#define DATA_FIRST_PKT_META_DATA                (0x10140000) //Data packet type meta data which comes in R1. This is for the all chunks (except last) and 
+                                                             //doesn't have lastw set. packet type is 0x14 and size is 15
+                                                             
+#define DATA_LAST_PKT_META_DATA                 (0x00140010) //Data packet type meta data which comes in R1. This is for the last chunk and has
+                                                             //lastw set. packet type is 0x14 and size is 0 because size determined by xout by widget
+                                                             
+#define DATA_LAST_PKT_META_DATA_EOP             (0x00140012) //Same as above but has eop also set
+                                                             
+#define DATA_PKT_TYPE                           (0x14)       //Data packet type in R1 metadata. R1.b2
+
+//FIXME : Temporary. Need to align with EMAC
+#define NRT_PACKET_DROP_TS_ERROR_CODE               (0xBAADF00D)
+
+#endif //____switch_mmap_defines_h
+

diff --git a/firmware/icss_switch/bin/version.txt b/firmware/icss_switch/bin/version.txt
new file mode 100644 (file)
index 0000000..bf4bdb7
--- /dev/null
+++ b/firmware/icss_switch/bin/version.txt
@@ -0,0 +1,3 @@
+ICSSG switch Firmware build info:       Jenkins Build Number: 799-2019-09-12_10-25-07
+ICSSG switch Firmware memory map files: industrial_communications_dev.git: commit id: 1ff9d46f9ab76b2c28b2954666e87399309b0514
+