1 #include <stdio.h>
2 #include <string.h>
3 #include <c6x.h>
4 #include <ti/csl/csl_psc.h>
5 #include <ti/csl/csl_pscAux.h>
6 #include <ti/csl/csl_edma3.h>
7 #include <ti/csl/csl_edma3Aux.h>
8 #include <ti/csl/cslr_tcp3d_cfg.h>
9 #include <ti/csl/cslr_tcp3d_dma.h>
10 #include <ti/csl/cslr_tcp3d_dma_offsets.h>
12 #include "tcp3dDrv.h"
13 #include "tcp3d_utils.h"
15 #define MAP_L2toGLB(a,coreId) (0x10000000+a+(coreId<<24))
18 #define TCP3D_CFG0 (CSL_TCP3D_A_DATA_REGS + CSL_TCP3D_DMA_TCP3D_IC_CFG0_P0_OFFSET)
19 #define TCP3D_LLR0 (CSL_TCP3D_A_DATA_REGS + CSL_TCP3D_DMA_TCP3D_SYS_P0_OFFSET)
20 #define TCP3D_OUT0 (CSL_TCP3D_A_DATA_REGS + CSL_TCP3D_DMA_TCP3D_OUT_HD0_OFFSET)
22 #define TCP3D_CFG1 (CSL_TCP3D_A_DATA_REGS + CSL_TCP3D_DMA_TCP3D_IC_CFG0_P1_OFFSET)
23 #define TCP3D_LLR1 (CSL_TCP3D_A_DATA_REGS + CSL_TCP3D_DMA_TCP3D_SYS_P1_OFFSET)
24 #define TCP3D_OUT1 (CSL_TCP3D_A_DATA_REGS + CSL_TCP3D_DMA_TCP3D_OUT_HD1_OFFSET)
26 #define LLR_DSTCIDX (CSL_TCP3D_DMA_TCP3D_PAR0_P0_OFFSET - CSL_TCP3D_DMA_TCP3D_SYS_P0_OFFSET)
27 #define LLR_DSTBIDX (CSL_TCP3D_DMA_TCP3D_PAR0_P0_OFFSET - CSL_TCP3D_DMA_TCP3D_SYS_P0_OFFSET)
29 Uint32 tcp3d_cfg[2][16];
30 Int8 tcp3d_llr[2][6144*3];
31 Uint32 tcp3d_hd [2][6144/32+1];
35 /*
36 dummy TRIGGER -> CFG0 -> LLR0(sys stream) -> LLR0(par1 stream) -> LLR0(par2 stream) -> dummy
37 dummy TRIGGER -> CFG1 -> LLR1(sys stream) -> LLR1(par1 stream) -> LLR1(par2 stream) -> dummy
38 REVT0 -> HD0
39 REVT1 -> HD1
40 */
41 // In the following table, CFG means configurable,
42 DEMO_SEdmaTbl DEMO_EdmaTbl[MAXNUM_EDMA_PHYCH + MAXNUM_EDMA_LINKCH]={
43 /* ChIdx link syncDim tcchEn tcc aCnt bCnt cCnt srcAddr dstAddr srcBidx dstBidx srcCidx dstCidx chHandler PaRAM_Addr*/
44 /* 0 dummy REVT0 */ { 0, 70, A_SYMC, 1, 0, 0, 1, 1, NULL, NULL, 0, 0, 0, 0, NULL, NULL},
45 /* 1 dummy REVT1 */ { 1, 72, A_SYMC, 1, 1, 0, 1, 1, NULL, NULL, 0, 0, 0, 0, NULL, NULL},
46 /* 2 dummy TRIGGER */ { 2, 64, A_SYMC, 1, 2, 0, 1, 1, NULL, NULL, 0, 0, 0, 0, NULL, NULL},
47 /* 3 LINK_CFG0 */ {64, 65, A_SYMC, 1, 2, 60, 1, 1, (Uint32)tcp3d_cfg[0], TCP3D_CFG0, 0, 0, 0, 0, NULL, NULL},
48 /* 4 LINK_LLR0 */ {65, 66, A_SYMC, 0, 2, CFG, 3, 1, (Uint32)tcp3d_llr[0], TCP3D_LLR0, CFG, LLR_DSTBIDX, CFG, LLR_DSTCIDX, NULL, NULL},
49 /* 5 END_LLR0 */ {66, 67, A_SYMC, 1, 2, 0, 1, 1, NULL, NULL, 0, 0, 0, 0, NULL, NULL},
50 /* 6 LINK_CFG1 */ {67, 68, A_SYMC, 1, 2, 60, 1, 1, (Uint32)tcp3d_cfg[1], TCP3D_CFG1, 0, 0, 0, 0, NULL, NULL},
51 /* 7 LINK_LLR1 */ {68, 69, A_SYMC, 0, 2, CFG, 3, 1, (Uint32)tcp3d_llr[1], TCP3D_LLR1, CFG, LLR_DSTBIDX, CFG, LLR_DSTCIDX, NULL, NULL},
52 /* 8 END_LLR1 */ {69, 64, A_SYMC, 1, 2, 0, 1, 1, NULL, NULL, 0, 0, 0, 0, NULL, NULL},
53 /* 9 LINK_HD0 */ {70, 71, A_SYMC, 0, 0, CFG, 1, 1, TCP3D_OUT0, (Uint32)tcp3d_hd[0], 0, 0, 0, 0, NULL, NULL},
54 /*10 END_HD0 */ {71, 70, A_SYMC, 1, 0, 0, 1, 1, NULL, NULL, 0, 0, 0, 0, NULL, NULL},
55 /*11 LINK_HD1 */ {72, 73, A_SYMC, 0, 1, CFG, 1, 1, TCP3D_OUT0, (Uint32)tcp3d_hd[1], 0, 0, 0, 0, NULL, NULL},
56 /*12 END_HD1 */ {73, 72, A_SYMC, 1, 1, 0, 1, 1, NULL, NULL, 0, 0, 0, 0, NULL, NULL},
57 };
59 CSL_Edma3ChannelObj glbEdmaChObj[MAXNUM_EDMA_PHYCH];
61 void DEMO_initEDMA()
62 {
63 CSL_Edma3Obj edmaObj;
64 Uint8 instNum = CSL_TPCC_2;
65 CSL_Status status;
66 CSL_Edma3Handle hModule;
67 CSL_Edma3ChannelHandle hEdmaCh;
68 CSL_Edma3ChannelAttr chAttr;
69 Uint32 i, PaRAM_Addr;
70 CSL_Edma3Context context;
72 if (CSL_edma3Init(&context) != CSL_SOK)
73 {
74 printf ("EDMA module initialization failed\n");
75 }
77 /* Open EDMA3 */
78 hModule = CSL_edma3Open (&edmaObj, instNum, NULL, &status);
79 if ((hModule == NULL) || (status != CSL_SOK))
80 {
81 printf("Open EDMA3 failed");
82 }
83 for( i = 0; i < MAXNUM_EDMA_PHYCH; i++ )
84 {
85 /* Open EDMA channel */
86 chAttr.regionNum = CSL_EDMA3_REGION_GLOBAL;
87 chAttr.chaNum = DEMO_EdmaTbl[i].ChIdx;
88 hEdmaCh = CSL_edma3ChannelOpen (&glbEdmaChObj[i], instNum, &chAttr, &status);
89 if ((hEdmaCh == NULL) || (status != CSL_SOK))
90 {
91 printf("Open EDMA channel failed");
92 }
93 else
94 {
95 DEMO_EdmaTbl[i].chHandler = (Uint32)hEdmaCh;
96 printf("EDMA CH obj %08x\n",hEdmaCh);
97 }
99 /* Enable EDMA channel */
100 if ((status = CSL_edma3HwChannelControl (hEdmaCh, CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL)) != CSL_SOK)
101 {
102 printf("Enable EDMA channel failed");
103 }
105 /* Map EDMA channel to PaRAM set */
106 CSL_edma3MapDMAChannelToParamBlock (hModule, DEMO_EdmaTbl[i].ChIdx, DEMO_EdmaTbl[i].ChIdx);
107 }
109 /* Get the PaRAM set address */
110 for( i = 0; i < (MAXNUM_EDMA_PHYCH + MAXNUM_EDMA_LINKCH); i++ )
111 {
112 hEdmaCh = (CSL_Edma3ChannelHandle)DEMO_EdmaTbl[0].chHandler;
113 PaRAM_Addr = (Uint32)CSL_edma3GetParamHandle (hEdmaCh, DEMO_EdmaTbl[i].ChIdx, &status);
114 if (PaRAM_Addr == NULL)
115 {
116 printf("Get PaRAM failed");
117 }
118 else
119 {
120 DEMO_EdmaTbl[i].PaRAM_Addr = PaRAM_Addr;
121 printf("PaRAM address %08x\n",PaRAM_Addr);
122 }
123 }
124 }
126 void DEMO_setupEDMA()
127 {
128 Uint32 i, j;
129 Uint32 tmpBuf[8];
130 Uint32 * wordPtr;
131 EDMA_PARAM_SET * par;
132 /* Program PaRAM set */
133 for( i = 0; i < (MAXNUM_EDMA_PHYCH + MAXNUM_EDMA_LINKCH); i++ )
134 {
135 //par = (EDMA_PARAM_SET *)DEMO_EdmaTbl[i].PaRAM_Addr;
136 for( j = 0; j < 8; j++ )
137 tmpBuf[j] = 0;
138 par = (EDMA_PARAM_SET *)tmpBuf;
139 par->sam = 0;
140 par->dam = 0;
141 par->syncDim = DEMO_EdmaTbl[i].syncDim;
142 par->stat = 0;
143 par->fwid = 0;
144 par->tccMode = 0;
145 par->tcc = DEMO_EdmaTbl[i].tcc;
146 par->tcintEn = 0;
147 par->itcintEn = 0;
148 par->tcchEn = DEMO_EdmaTbl[i].tcchEn;
149 if( (i==4) || (i==7) )
150 {
151 par->itcchEn = 1;
152 }
153 else
154 {
155 par->itcchEn = 0;
156 }
157 par->privId = 0;
158 par->priv = 0;
159 if( (DEMO_EdmaTbl[i].srcAddr >= 0x800000) && (DEMO_EdmaTbl[i].srcAddr < 0x900000) )
160 {
161 par->src = MAP_L2toGLB(DEMO_EdmaTbl[i].srcAddr,glbCoreId);
162 }
163 else
164 {
165 par->src = DEMO_EdmaTbl[i].srcAddr;
166 }
167 par->aCnt = DEMO_EdmaTbl[i].aCnt;
168 par->bCnt = DEMO_EdmaTbl[i].bCnt;
169 if( (DEMO_EdmaTbl[i].dstAddr >= 0x800000) && (DEMO_EdmaTbl[i].dstAddr < 0x900000) )
170 {
171 par->dst = MAP_L2toGLB(DEMO_EdmaTbl[i].dstAddr,glbCoreId);
172 }
173 else
174 {
175 par->dst = DEMO_EdmaTbl[i].dstAddr;
176 }
177 par->srcBidx = DEMO_EdmaTbl[i].srcBidx;
178 par->dstBidx = DEMO_EdmaTbl[i].dstBidx;
179 par->link = DEMO_EdmaTbl[i].link*32+0x4000;
180 par->bCntRld = 0;
181 par->srcCidx = DEMO_EdmaTbl[i].srcCidx;
182 par->dstCidx = DEMO_EdmaTbl[i].dstCidx;
183 par->cCnt = DEMO_EdmaTbl[i].cCnt;
185 wordPtr = (Uint32 *)DEMO_EdmaTbl[i].PaRAM_Addr;
186 for( j = 0; j < 8; j++ )
187 {
188 wordPtr[j] = tmpBuf[j];
189 }
190 }
192 // post_write_uart("EDMA Setup for TCP3d Done\n");
193 }
196 Void tcp3d_config (Uint8 instanceNum)
197 {
198 Uint32 reg = 0;
199 CSL_Tcp3d_cfgRegs * hTCP3dACfgReg;
201 if(instanceNum == 0)
202 hTCP3dACfgReg = ((CSL_Tcp3d_cfgRegs *) CSL_TCP3D_A_CFG_REGS);
203 else
204 hTCP3dACfgReg = ((CSL_Tcp3d_cfgRegs *) CSL_TCP3D_B_CFG_REGS);
206 /* Soft Reset the TCP3D */
207 hTCP3dACfgReg->TCP3_SOFT_RESET = 1;
208 hTCP3dACfgReg->TCP3_SOFT_RESET = 0;
210 /* Mode 3=SPLIT MODE HSUPA */
211 CSL_FINS (reg, TCP3D_CFG_TCP3_MODE_MODE_SEL, 3);
213 /* Input memory, 0 = double buffer disable */
214 CSL_FINS (reg, TCP3D_CFG_TCP3_MODE_IN_MEM_DB_EN, 0);
216 /* 1 = Internal Generation of Interleaver table enabled */
217 CSL_FINS (reg, TCP3D_CFG_TCP3_MODE_ITG_EN, CSL_TCP3D_CFG_TCP3_MODE_ITG_EN_ENABLE);
219 /* Error Ignore bit, 1 = Don't stop TCP3D on enabled errors */
220 CSL_FINS (reg, TCP3D_CFG_TCP3_MODE_ERROR_IGNORE_EN, CSL_TCP3D_CFG_TCP3_MODE_ERROR_IGNORE_EN_DONT_STOP);
222 /* 1 = Auto trigger enabled */
223 CSL_FINS (reg, TCP3D_CFG_TCP3_MODE_AUTO_TRIG_EN, CSL_TCP3D_CFG_TCP3_MODE_AUTO_TRIG_EN_ENABLE);
225 /* LTE CRC value selection - 0 for LTE */
226 CSL_FINS (reg, TCP3D_CFG_TCP3_MODE_LTE_CRC_ISEL, 0);
228 hTCP3dACfgReg->TCP3_MODE = reg;
230 /* Set ENDIAN register parameters */
231 reg = 0;
232 #ifdef _BIG_ENDIAN
233 CSL_FINS (reg, TCP3D_CFG_TCP3_END_ENDIAN_INTR, CSL_TCP3D_CFG_TCP3_END_ENDIAN_INTR_16_BIT_NATIVE);
234 CSL_FINS (reg, TCP3D_CFG_TCP3_END_ENDIAN_INDATA, CSL_TCP3D_CFG_TCP3_END_ENDIAN_INDATA_8_BIT_NATIVE);
235 #else
236 CSL_FINS (reg, TCP3D_CFG_TCP3_END_ENDIAN_INTR, CSL_TCP3D_CFG_TCP3_END_ENDIAN_INTR_32_BIT_PACKED);
237 CSL_FINS (reg, TCP3D_CFG_TCP3_END_ENDIAN_INDATA, CSL_TCP3D_CFG_TCP3_END_ENDIAN_INDATA_32_BIT_PACKED);
238 #endif
240 hTCP3dACfgReg->TCP3_END = reg;
242 /* Set EXECUTE P0 register parameters 1 = Normal mode */
243 CSL_FINS (hTCP3dACfgReg->TCP3_EXE_P0, TCP3D_CFG_TCP3_EXE_P0_EXE_CMD, CSL_TCP3D_CFG_TCP3_EXE_P0_EXE_CMD_ENABLE);
245 /* Set EXECUTE P1 register parameters 1 = Normal mode */
246 CSL_FINS (hTCP3dACfgReg->TCP3_EXE_P1, TCP3D_CFG_TCP3_EXE_P1_EXE_CMD, CSL_TCP3D_CFG_TCP3_EXE_P1_EXE_CMD_ENABLE);
248 return;
249 }
251 /** TCP3D SW0 nominal values */
252 Int32 tcp3d_sw0_Tab[] = {16, 32, 48, 64, 96, 128};
254 /** Used for getting the sw0LenSel index values */
255 Int32 TAB[] = {0, 1, 2, 3, 3, 4, 4, 5};
257 /** Table used for division optimization logic */
258 Int32 shiftValTab [] = {4, 5, 4, 6, 5, 7};
260 /** Table used for division optimization logic */
261 Uint32 mulValTab [] = {32768, 32768, 10923, 32768, 10923, 32768};
263 /** Table used for checking bounds */
264 Uint32 frameLenTab[2][2] = {40,5114,40,6144};
267 Int32 TCP3D_codeBlkSeg (
268 UInt32 blockLengthK,
269 UInt8 numMAP,
270 UInt8 *sw0NomLen,
271 UInt8 *sw0LenSel,
272 UInt8 *sw1Len,
273 UInt8 *sw2LenSel,
274 UInt8 *numsw0)
275 {
276 Int32 status = 0;
277 Int32 K, Kext;
278 Int32 numSWrem;
279 Int32 subFrameLen;
280 Int32 sw0LenSelTmp;
281 Int32 sw1LenTmp;
282 Int32 sw2LenSelTmp;
283 Int32 numsw0Tmp;
284 Int32 numSW;
285 Int32 shiftVal, mulVal;
286 Int32 sw0Len = *sw0NomLen;
288 /**
289 * Check the bounds based on numMAP value. frameLenTab is for the bound values
290 * numMAP - mode - block length bounds
291 * 1 - 3GPP - [40,5114]
292 * 2 - LTE/WIMAX - [40,6144]
293 */
294 if ( (blockLengthK < frameLenTab[numMAP-1][0]) ||
295 (blockLengthK > frameLenTab[numMAP-1][1]) )
296 {
297 status = 1;
298 return (status);
299 }
301 K = blockLengthK;
302 Kext = ((K + 0x3)>>2)<<2;
304 //Calculate sw0LenSelTmp, SW1Len, SW2LenSel, numsw0Tmp
305 subFrameLen = Kext >> numMAP; //Kext / (2*numMAP);
307 sw0LenSelTmp = TAB[((sw0Len>>4)-1)&0x7];
309 //Check that this holds: (reg->NumInfoBits <= 128 * sparms->tcp3_SW0_length * numMap)
310 while((Kext > 128 * sw0Len * numMAP) && sw0LenSelTmp<6)
311 {
312 sw0LenSelTmp++;
313 sw0Len = tcp3d_sw0_Tab[sw0LenSelTmp];
314 }
316 //numSW = subFrameLen/sw0Len; Replaced by:
317 shiftVal = shiftValTab[sw0LenSelTmp];
318 mulVal = mulValTab[sw0LenSelTmp];
319 numSW = _mpysu((subFrameLen >> shiftVal), mulVal)>>15;
321 numSWrem = subFrameLen - numSW*sw0Len;
322 if(numSWrem)
323 {
324 numSW++;
325 }
327 if(numSW == 1)
328 {
329 numsw0Tmp = 0;
330 sw1LenTmp = subFrameLen-1; //stored value is (sw1_length -1)
331 sw2LenSelTmp = 0; //SW2 is Off.
332 }
333 else if(numSW == 2)
334 {
335 numsw0Tmp = 0;
336 if(subFrameLen & 0x3)
337 {
338 sw1LenTmp = 2*(subFrameLen>>2) + 1; //stored value is (sw1_length -1)
339 sw2LenSelTmp = 2; //sw1LenTmp > SW2Len
340 }
341 else
342 {
343 sw1LenTmp = (subFrameLen>>1) - 1; //stored value is (sw1_length -1)
344 sw2LenSelTmp = 1; //sw1LenTmp = SW2Len
345 }
346 }
347 else if( numSWrem <= (sw0Len>>1) )
348 {
349 numsw0Tmp = numSW-2;
350 numSWrem = subFrameLen - (numSW-2)*sw0Len;
351 if((numSWrem) & 0x3)
352 {
353 sw1LenTmp = 2*(numSWrem>>2) + 1; //stored value is (sw1_length -1)
354 sw2LenSelTmp = 2; //sw1LenTmp > SW2Len
355 }
356 else
357 {
358 sw1LenTmp = (numSWrem>>1) - 1; //stored value is (sw1_length -1)
359 sw2LenSelTmp = 1; //sw1LenTmp = SW2Len
360 }
361 }
362 else
363 {
364 numsw0Tmp = numSW-1;
365 sw1LenTmp = numSWrem - 1; //stored value is (sw1_length -1)
366 sw2LenSelTmp = 0; //SW2 is Off.
367 }
370 *sw0LenSel = (Uint8) sw0LenSelTmp;
371 *sw1Len = (Uint8) sw1LenTmp;
372 *sw2LenSel = (Uint8) sw2LenSelTmp;
373 *numsw0 = (Uint8) numsw0Tmp;
374 *sw0NomLen = (Uint8) sw0Len;
376 return ( status );
378 }
380 CSL_PscRegs * dbghPscRegs = ((CSL_PscRegs *) (CSL_PSC_REGS));
382 Int32 enable_tcp3dA()
383 {
384 #ifndef SIMULATOR_SUPPORT
386 /* TCP3d A power domain is turned OFF by default. It
387 * needs to be turned on before doing any TCP3d A device
388 * register access.
389 */
390 /* Set TCP3d A Power domain to ON */
391 CSL_PSC_enablePowerDomain (CSL_PSC_PD_TCP3D_A);
393 /* Enable the clocks too for TCP3d A */
394 CSL_PSC_setModuleNextState (CSL_PSC_LPSC_TCP3D_A, PSC_MODSTATE_ENABLE);
397 /* Start the state transition */
398 CSL_PSC_startStateTransition (CSL_PSC_PD_TCP3D_A);
400 /* Wait until the state transition process is completed. */
401 while (!CSL_PSC_isStateTransitionDone (CSL_PSC_PD_TCP3D_A));
402 /* Return TCP3d A PSC status */
403 if ((CSL_PSC_getPowerDomainState(CSL_PSC_PD_TCP3D_A) == PSC_PDSTATE_ON) &&
404 (CSL_PSC_getModuleState (CSL_PSC_LPSC_TCP3D_A) == PSC_MODSTATE_ENABLE))
405 {
406 /* TCP3d A ON. Ready for use */
407 return 0;
408 }
409 else
410 {
411 /* TCP3d A Power on failed. Return error */
412 return -1;
413 }
414 #else
415 /* No power up needed on Sim */
416 return 0;
417 #endif
418 }
420 CSL_Tcp3d_cfgRegs *tcp3dA_CfgRegs = (CSL_Tcp3d_cfgRegs *) CSL_TCP3D_A_CFG_REGS;
421 CSL_Tcp3d_cfgRegs *tcp3dB_CfgRegs = (CSL_Tcp3d_cfgRegs *) CSL_TCP3D_B_CFG_REGS;
423 Int32 enable_tcp3dB()
424 {
425 #ifndef SIMULATOR_SUPPORT
427 /* TCP3d B power domain is turned OFF by default. It
428 * needs to be turned on before doing any FFTC device
429 * register access.
430 */
431 /* Set TCP3d B Power domain to ON */
432 CSL_PSC_enablePowerDomain (CSL_PSC_PD_TCP3D_B);
434 /* Enable the clocks too for TCP3d B */
435 CSL_PSC_setModuleNextState (CSL_PSC_LPSC_TCP3D_B, PSC_MODSTATE_ENABLE);
438 /* Start the state transition */
439 CSL_PSC_startStateTransition (CSL_PSC_PD_TCP3D_B);
441 /* Wait until the state transition process is completed. */
442 while (!CSL_PSC_isStateTransitionDone (CSL_PSC_PD_TCP3D_B));
443 /* Return FFTC PSC status */
444 if ((CSL_PSC_getPowerDomainState(CSL_PSC_PD_TCP3D_B) == PSC_PDSTATE_ON) &&
445 (CSL_PSC_getModuleState (CSL_PSC_LPSC_TCP3D_B) == PSC_MODSTATE_ENABLE))
446 {
447 /* TCP3d B ON. Ready for use */
448 return 0;
449 }
450 else
451 {
452 /* TCP3d B Power on failed. Return error */
453 return -1;
454 }
455 #else
456 /* No power up needed on Sim */
457 return 0;
458 #endif
459 }
463 void prepare_user_info (BCP_userInfo *userInfo, Int8 *tailBits, Uint16 cblen)
464 {
465 UInt32 reg;
466 UInt8 mode, sw0LenSel, sw2LenSel, sw1Len, numsw0;
467 cbConfig param;
468 Int32 signChange;
469 Int32 Kt;
470 Int8 beta0[8], beta1[8];
472 memset ((void *) ¶m, 0, sizeof (cbConfig));
474 /* Assigning values for configuration. */
475 param.sw0Length = 96;
476 param.maxStar = 0;
477 param.outStsRead = 0;
478 param.extScale = 1;
479 param.softOutRead = 0;
480 param.softOutFrmtSel = 1;
481 param.minIter = 1;
482 param.maxIter = 8;
483 param.snrVal = 14;
484 param.snrReport = 1;
485 param.stopSel = 0;
486 param.crcIterSel = 1;
487 param.crcPolySel = 0;
488 param.maxStarThres = 4;
489 param.maxStarValue = 2;
490 param.extrScale_0 = 24;
491 param.extrScale_1 = 24;
492 param.extrScale_2 = 24;
493 param.extrScale_3 = 24;
494 param.extrScale_4 = 24;
495 param.extrScale_5 = 24;
496 param.extrScale_6 = 24;
497 param.extrScale_7 = 24;
498 param.extrScale_8 = 24;
499 param.extrScale_9 = 24;
500 param.extrScale_10 = 24;
501 param.extrScale_11 = 24;
502 param.extrScale_12 = 24;
503 param.extrScale_13 = 24;
504 param.extrScale_14 = 24;
505 param.extrScale_15 = 24;
507 mode = CSL_TCP3D_CFG_TCP3_MODE_MODE_SEL_HSUPA;
509 //userInfo->cblength = cblen;
510 //userInfo->cblengthover2 = cblen >> 1;
511 //userInfo->cblengthover2_1 = userInfo->cblengthover2;
512 //userInfo->cblengthplus4 = cblen + 4;
513 //userInfo->llroffset = (((cblen + 4) + 15) >> 4 ) * 16;
514 //userInfo->betaStateLoc = (userInfo->llroffset) * 3;
515 //userInfo->cblengthover8 = cblen >> 3;
516 //userInfo->reserved = 0;
517 TCP3D_codeBlkSeg (cblen, 1,
518 ¶m.sw0Length,
519 &sw0LenSel,
520 &sw1Len,
521 &sw2LenSel,
522 &numsw0);
524 /* Number of SW0 and block size (Range: 39 to 8191; block size - 1) */
525 reg = 0;
526 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG0_P0_NUM_SW0, numsw0);
527 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG0_P0_BLK_LN, cblen - 1);
529 userInfo->TCP3D_IC_CFG0 = reg;
531 /* SW0, SW1, SW2 length */
532 reg = 0;
533 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG1_P0_SW0_LN_SEL, sw0LenSel);
534 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG1_P0_SW2_LN_SEL, sw2LenSel);
535 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG1_P0_SW1_LN, sw1Len);
538 userInfo->TCP3D_IC_CFG1 = reg;
540 /* Interleaver table load, Max star, output status register,
541 * swap HD bit ordering, extrinsic scaling, soft output flag,
542 * soft output format, number of iterations, SNR reporting,
543 * stopping criteria, CRC selection */
544 reg = 0;
545 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_INTER_LOAD_SEL, CSL_TCP3D_DMA_TCP3D_IC_CFG2_P0_INTER_LOAD_SEL_SET);
546 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_MAXST_EN, param.maxStar);
547 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_OUT_FLAG_EN, param.outStsRead);
548 #ifdef _BIG_ENDIAN
549 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_OUT_ORDER_SEL, CSL_TCP3D_DMA_TCP3D_IC_CFG2_P0_OUT_ORDER_SEL_SWAP);
550 #else
551 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_OUT_ORDER_SEL, CSL_TCP3D_DMA_TCP3D_IC_CFG2_P0_OUT_ORDER_SEL_NO_SWAP);
552 #endif
553 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_EXT_SCALE_EN, param.extScale);
554 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_SOFT_OUT_FLAG_EN, param.softOutRead);
555 #ifdef _BIG_ENDIAN
556 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_SOFT_OUT_ORDER_SEL, CSL_TCP3D_DMA_TCP3D_IC_CFG2_P0_SOFT_OUT_ORDER_SEL_8_BIT);
557 #else
558 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_SOFT_OUT_ORDER_SEL, CSL_TCP3D_DMA_TCP3D_IC_CFG2_P0_SOFT_OUT_ORDER_SEL_32_BIT);
559 #endif
560 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_SOFT_OUT_FMT, param.softOutFrmtSel);
561 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_MIN_ITR, param.minIter);
562 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_MAX_ITR, param.maxIter);
563 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_SNR_VAL, param.snrVal);
564 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_SNR_REP, param.snrReport);
565 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_STOP_SEL, param.stopSel);
566 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_CRC_ITER_PASS, param.crcIterSel);
567 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG2_P0_CRC_SEL, param.crcPolySel);
569 userInfo->TCP3D_IC_CFG2 = reg;
571 /* Max star threshold and value */
572 reg = 0;
573 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG3_P0_MAXST_THOLD, param.maxStarThres);
574 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG3_P0_MAXST_VALUE, param.maxStarValue);
576 userInfo->TCP3D_IC_CFG3 = reg;
578 Kt = COMPUTE_KT(cblen);
579 signChange = 1;
580 /* Beta states */
581 Tcp3d_betaStates(tailBits, signChange, Kt, beta0, beta1);
583 /*
584 7:0 beta_st0_map0
585 15:8 beta_st1_map0
586 23:16 beta_st2_map0
587 31:24 beta_st3_map0
588 */
589 //userInfo->TCP3D_IC_CFG4 = _rotl(_swap4(_mem4(&beta0[0])),16); // beta_st0_map0 | beta_st1_map0 | beta_st2_map0 | beta_st3_map0
590 //userInfo->TCP3D_IC_CFG5 = _rotl(_swap4(_mem4(&beta0[4])),16); // beta_st4_map0 | beta_st5_map0 | beta_st6_map0 | beta_st7_map0
591 //userInfo->TCP3D_IC_CFG6 = _rotl(_swap4(_mem4(&beta1[0])),16);
592 //userInfo->TCP3D_IC_CFG7 = _rotl(_swap4(_mem4(&beta1[4])),16);
593 reg = 0;
594 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG4_P0_BETA_ST0_MAP0, beta0[0]);
595 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG4_P0_BETA_ST1_MAP0, beta0[1]);
596 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG4_P0_BETA_ST2_MAP0, beta0[2]);
597 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG4_P0_BETA_ST3_MAP0, beta0[3]);
599 userInfo->TCP3D_IC_CFG4 = reg;//_mem4(&beta0[0]);
601 reg = 0;
602 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG5_P0_BETA_ST4_MAP0, beta0[4]);
603 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG5_P0_BETA_ST5_MAP0, beta0[5]);
604 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG5_P0_BETA_ST6_MAP0, beta0[6]);
605 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG5_P0_BETA_ST7_MAP0, beta0[7]);
607 userInfo->TCP3D_IC_CFG5 = reg;
609 reg = 0;
610 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG6_P0_BETA_ST0_MAP1, beta1[0]);
611 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG6_P0_BETA_ST1_MAP1, beta1[1]);
612 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG6_P0_BETA_ST2_MAP1, beta1[2]);
613 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG6_P0_BETA_ST3_MAP1, beta1[3]);
615 userInfo->TCP3D_IC_CFG6 = reg;//_mem4(&beta0[0]);
617 reg = 0;
618 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG7_P0_BETA_ST4_MAP1, beta1[4]);
619 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG7_P0_BETA_ST5_MAP1, beta1[5]);
620 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG7_P0_BETA_ST6_MAP1, beta1[6]);
621 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG7_P0_BETA_ST7_MAP1, beta1[7]);
623 userInfo->TCP3D_IC_CFG7 = reg;
624 //userInfo->TCP3D_IC_CFG5 = _mem4(&beta0[4]);
625 //userInfo->TCP3D_IC_CFG6 = _mem4(&beta1[0]);
626 //userInfo->TCP3D_IC_CFG7 = _mem4(&beta1[4]);
629 /* Extrinsic scale value 0-3 */
630 reg = 0;
631 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG8_P0_EXT_SCALE_0, param.extrScale_0);
632 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG8_P0_EXT_SCALE_1, param.extrScale_1);
633 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG8_P0_EXT_SCALE_2, param.extrScale_2);
634 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG8_P0_EXT_SCALE_3, param.extrScale_3);
635 userInfo->TCP3D_IC_CFG8 = reg;
637 /* Extrinsic scale value 4-7 */
638 reg = 0;
639 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG9_P0_EXT_SCALE_4, param.extrScale_4);
640 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG9_P0_EXT_SCALE_5, param.extrScale_5);
641 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG9_P0_EXT_SCALE_6, param.extrScale_6);
642 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG9_P0_EXT_SCALE_7, param.extrScale_7);
643 userInfo->TCP3D_IC_CFG9 = reg;
645 /* Extrinsic scale value 8-11 */
646 reg = 0;
647 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG10_P0_EXT_SCALE_8, param.extrScale_8);
648 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG10_P0_EXT_SCALE_9, param.extrScale_9);
649 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG10_P0_EXT_SCALE_10, param.extrScale_10);
650 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG10_P0_EXT_SCALE_11, param.extrScale_11);
651 userInfo->TCP3D_IC_CFG10 = reg;
653 /* Extrinsic scale value 12-15 */
654 reg = 0;
655 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG11_P0_EXT_SCALE_12, param.extrScale_12);
656 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG11_P0_EXT_SCALE_13, param.extrScale_13);
657 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG11_P0_EXT_SCALE_14, param.extrScale_14);
658 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG11_P0_EXT_SCALE_15, param.extrScale_15);
659 userInfo->TCP3D_IC_CFG11 = reg;
661 /* LTE or WIMAX */
662 if (mode == CSL_TCP3D_CFG_TCP3_MODE_MODE_SEL_LTE )
663 {
664 Int32 frameLenInd = LTE_interleaver_index(cblen);
666 /* ITG param 0-1 */
667 reg = 0;
669 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG12_P0_ITG_PARAM0,
670 (UInt16) ((2*TCP3_LteInterleaverTable[frameLenInd][2]) % TCP3_LteInterleaverTable[frameLenInd][0]));
671 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG12_P0_ITG_PARAM1, TCP3_LteInterleaverTable[frameLenInd][6]);
672 userInfo->TCP3D_IC_CFG12 = reg;
674 /* ITG param 2-3 */
675 reg = 0;
676 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG13_P0_ITG_PARAM2, TCP3_LteInterleaverTable[frameLenInd][3]);
677 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG13_P0_ITG_PARAM3, TCP3_LteInterleaverTable[frameLenInd][4]);
678 userInfo->TCP3D_IC_CFG13 = reg;
680 /* ITG param 4 */
681 reg = 0;
682 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG14_P0_ITG_PARAM4, TCP3_LteInterleaverTable[frameLenInd][5]);
683 userInfo->TCP3D_IC_CFG14 = reg;
684 }
685 else if (mode == CSL_TCP3D_CFG_TCP3_MODE_MODE_SEL_WIMAX)
686 {
687 Int32 frameLenInd = WIMAX_interleaver_index (cblen);
688 /* ITG param 0-1 */
689 reg = 0;
691 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG12_P0_ITG_PARAM0, 0);
692 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG12_P0_ITG_PARAM1, TCP3_WimaxInterleaverTable[frameLenInd][0]);
693 userInfo->TCP3D_IC_CFG12 = reg;
695 /* ITG param 2-3 */
696 reg = 0;
697 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG13_P0_ITG_PARAM2, TCP3_WimaxInterleaverTable[frameLenInd][1]);
698 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG13_P0_ITG_PARAM3, TCP3_WimaxInterleaverTable[frameLenInd][2]);
699 userInfo->TCP3D_IC_CFG13 = reg;
701 /* ITG param 4 */
702 reg = 0;
703 CSL_FINS (reg, TCP3D_DMA_TCP3D_IC_CFG14_P0_ITG_PARAM4, TCP3_WimaxInterleaverTable[frameLenInd][3]);
704 userInfo->TCP3D_IC_CFG14 = reg;
705 }
706 else
707 {
708 /* ITG Params are not required for 3GPP */
709 userInfo->TCP3D_IC_CFG12 = 0;
710 userInfo->TCP3D_IC_CFG13 = 0;
711 userInfo->TCP3D_IC_CFG14 = 0;
712 }
714 userInfo->TCP3D_TRIG = 1;
715 return;
716 }