1 /** \r
2 * @file fftc_lld.h\r
3 *\r
4 * @brief \r
5 * Header file with data structure and API declarations for FFTC Low\r
6 * Level Driver (LLD).\r
7 * \r
8 * \par\r
9 * ============================================================================\r
10 * @n (C) Copyright 2009, Texas Instruments, Inc.\r
11 * \r
12 * Redistribution and use in source and binary forms, with or without \r
13 * modification, are permitted provided that the following conditions \r
14 * are met:\r
15 *\r
16 * Redistributions of source code must retain the above copyright \r
17 * notice, this list of conditions and the following disclaimer.\r
18 *\r
19 * Redistributions in binary form must reproduce the above copyright\r
20 * notice, this list of conditions and the following disclaimer in the \r
21 * documentation and/or other materials provided with the \r
22 * distribution.\r
23 *\r
24 * Neither the name of Texas Instruments Incorporated nor the names of\r
25 * its contributors may be used to endorse or promote products derived\r
26 * from this software without specific prior written permission.\r
27 *\r
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
39 *\r
40 */\r
41 \r
42 /** @defgroup FFTC_LLD_API FFTC LLD Data Structures & APIs\r
43 *\r
44 * @section Introduction\r
45 *\r
46 * @subsection xxx Overview\r
47 * The FFT Coprocessor (FFTC) is an accelerator that can be used to perform\r
48 * FFT and IFFT on data. Using the FFTC to perform computations that otherwise\r
49 * would have been done in software frees up CPU cycles for other tasks. The \r
50 * FFTC module has been designed to be compatible with various OFDM based\r
51 * wireless standards like WiMax and LTE. \r
52 *\r
53 * The FFTC hardware provides the following features:\r
54 * -# IFFT and FFT.\r
55 * -# Sizes\r
56 * -# 2^a * 3^b for 2 >= a >= 13, 0 >= b >= 1 - maximum 8192.\r
57 * -# 12 * 2^a * 3^b * 5^c for sizes between 12 and 1296.\r
58 * -# LTE 7.5KHz frequency shift.\r
59 * -# 16 bits I / 16 bits Q input and output.\r
60 * -# 444 Msubcarriers/sec throughput.\r
61 * -# 77 dB SNR.\r
62 * -# Dynamic and Programmable Scaling modes.\r
63 * -# Dynamic scaling mode returns block exponent.\r
64 * -# Support for "FFT Shift" (switch left/right halves)\r
65 * -# Support for cyclic prefix (addition/removal)\r
66 * -# Ping/Pong input, output buffers.\r
67 * -# Input data scaling with shift.\r
68 * -# Output data scaling.\r
69 *\r
70 * This section of the documentation covers the FFTC Low Level Driver (LLD)\r
71 * APIs that include FFTC MMR access APIs and some utility APIs for formatting\r
72 * control headers and compiling FFT configuration for the hardware.\r
73 *\r
74 * @subsection References\r
75 * -# FFTC User Guide\r
76 */\r
77 #ifndef _FFTC_LLD_H_\r
78 #define _FFTC_LLD_H_\r
79 \r
80 /* FFTC CSL Register file and CSL definitions include */\r
81 #include <ti/csl/csl.h>\r
82 #include <ti/csl/cslr_fftc.h>\r
83 #include <ti/csl/soc.h>\r
84 \r
85 /**\r
86 @defgroup FFTC_LLD_SYMBOL FFTC LLD Symbols Defined\r
87 @ingroup FFTC_LLD_API\r
88 */\r
89 \r
90 /**\r
91 @defgroup FFTC_LLD_DATASTRUCT FFTC LLD Data Structures\r
92 @ingroup FFTC_LLD_API\r
93 */\r
94 \r
95 /**\r
96 @defgroup FFTC_LLD_FUNCTION FFTC LLD Functions\r
97 @ingroup FFTC_LLD_API\r
98 */\r
99 \r
100 #ifdef __cplusplus\r
101 extern "C"\r
102 {\r
103 #endif\r
104 \r
105 /**\r
106 @addtogroup FFTC_LLD_SYMBOL\r
107 @{\r
108 */\r
109 \r
110 /** @brief\r
111 * The Maximum number of butterfly stages supported. \r
112 */ \r
113 #define FFTC_MAX_NUM_BUTTERFLY_STAGES (7) \r
114 \r
115 /** @brief\r
116 * The number of internal buffers used by FFTC for \r
117 * simultaneous input, output and calculation operations.\r
118 * A complete FFTC Engine status snapshot can hence be obtained \r
119 * by putting together the status of all the three buffers.\r
120 */\r
121 #define FFTC_NUM_INTERNAL_BUFFERS (3) \r
122 \r
123 /** @brief\r
124 * The maximum number of FFT block sizes that can be\r
125 * specified to the FFTC engine hardware.\r
126 */\r
127 #define FFTC_MAX_NUM_BLOCKS (128) \r
128 \r
129 /** @brief\r
130 * The number of Transmit queues dedicated for FFTC from \r
131 * the CPPI-Queue Manager (QM).\r
132 */\r
133 #define FFTC_MAX_NUM_TXQUEUES (4) \r
134 \r
135 /** @brief\r
136 * Default value for CPPI Destination queue number.\r
137 *\r
138 * Configure the destination CPPI queue number for \r
139 * any given FFTC queue as this value, and the default CPPI \r
140 * queue number from the CPPI DMA channel configuration is \r
141 * used. \r
142 */ \r
143 #define FFTC_DEF_CPPI_QUEUE_NUM (0x3FFF) \r
144 \r
145 /** @brief\r
146 * Default DFT size.\r
147 *\r
148 * Configure the 'DFT_size' field of the Queue X Control\r
149 * Register to this value to indicate to the engine to\r
150 * use DFT Size list to pick up block sizes.\r
151 */ \r
152 #define FFTC_DEF_DFT_SIZE (0x3F) \r
153 \r
154 /** @brief\r
155 * Maximum number of PS Info words (32 bit words ) supported \r
156 * by the FFTC engine.\r
157 */ \r
158 #define FFTC_MAX_NUM_PS_WORDS (4) \r
159 \r
160 /**\r
161 @}\r
162 */\r
163 \r
164 /** @addtogroup FFTC_DATASTRUCT\r
165 @{ */\r
166 \r
167 typedef CSL_FftcRegs* CSL_FftcRegsOvly; \r
168 \r
169 typedef struct _Fftc_LldObj\r
170 {\r
171 /** FFTC Peripheral instance number */\r
172 uint8_t instNum;\r
173 \r
174 /** Register overlay pointer to access MMR for this FFTC instance */\r
175 CSL_FftcRegsOvly cfgRegs;\r
176 } Fftc_LldObj;\r
177 \r
178 /** \r
179 * @brief Fftc_DFTMode\r
180 *\r
181 * Enumeration for specifying the DFT/IDFT selection.\r
182 */ \r
183 typedef enum \r
184 {\r
185 /** IDFT/IFFT mode */ \r
186 Fftc_DFTMode_IDFT = 0,\r
187 /** DFT/FFT mode */ \r
188 Fftc_DFTMode_DFT = 1\r
189 } Fftc_DFTMode;\r
190 \r
191 /** \r
192 * @brief Fftc_ZeroPadMode\r
193 *\r
194 * Enumeration for specifying the zero pad mode.\r
195 */ \r
196 typedef enum \r
197 {\r
198 /** Addition Mode */ \r
199 Fftc_ZeroPadMode_ADD = 0,\r
200 /** Multiplication Mode */ \r
201 Fftc_ZeroPadMode_MULTIPLY = 1\r
202 } Fftc_ZeroPadMode;\r
203 \r
204 /** \r
205 * @brief Fftc_FreqShiftDir\r
206 *\r
207 * Enumeration for specifying the LTE Frequency\r
208 * Shift Direction, 0 for -1 and 1 for +1.\r
209 */ \r
210 typedef enum \r
211 {\r
212 /** LTE Frequency Shift Direction - Plus */ \r
213 Fftc_FreqShiftDir_PLUS = 0,\r
214 /** LTE Frequency Shift Direction - Minus */ \r
215 Fftc_FreqShiftDir_MINUS = 1\r
216 } Fftc_FreqShiftDir;\r
217 \r
218 /** \r
219 * @brief Fftc_FreqShiftIndex\r
220 *\r
221 * Enumeration for specifying the LTE Frequency Shift\r
222 * Table Index, M. There are only 2 valid values in the table,\r
223 * i.e., 8192 * 2 (16384) and 6144 * 2 (12288). Set to 0\r
224 * for M = 16384, and 1 for M = 12288.\r
225 */ \r
226 typedef enum \r
227 {\r
228 /** LTE Frequency Shift Index - 8192 * 2 */ \r
229 Fftc_FreqShiftIndex_16384 = 0,\r
230 /** LTE Frequency Shift Index - 6144 * 2 */ \r
231 Fftc_FreqShiftIndex_12288 = 1\r
232 } Fftc_FreqShiftIndex;\r
233 \r
234 /** \r
235 * @brief Fftc_QueueId\r
236 *\r
237 * Enumeration for specifying the 4 FFTC CPPI/QM Queues.\r
238 */ \r
239 typedef enum \r
240 {\r
241 /** FFTC Tx Queue 0 */\r
242 Fftc_QueueId_0 = 0,\r
243 /** FFTC Tx Queue 1 */\r
244 Fftc_QueueId_1 = 1,\r
245 /** FFTC Tx Queue 2 */\r
246 Fftc_QueueId_2 = 2,\r
247 /** FFTC Tx Queue 3 */\r
248 Fftc_QueueId_3 = 3\r
249 } Fftc_QueueId;\r
250 \r
251 /** \r
252 * @brief Fftc_DestQRegCfg\r
253 *\r
254 * Structure to specify/hold the CPPI Destination queue\r
255 * information stored in the FFTC hardware's Queue X \r
256 * Destination Queue Register for a given FFTC queue.\r
257 */ \r
258 typedef struct _Fftc_DestQRegCfg\r
259 {\r
260 /** Boolean Flag, set to 1 to enable FFT shift at output\r
261 * (reverse left/right halves)\r
262 *\r
263 * Corresponds to the 'FFT_shift_left_right_output' bit field \r
264 * of the FFTC Queue x Destination Queue Register.\r
265 */\r
266 uint8_t bOutputFFTShift; \r
267 \r
268 /** Boolean Flag, set to 1 to enable FFT shift at input\r
269 * (reverse left/right halves)\r
270 *\r
271 * Corresponds to the 'FFT_shift_left_right_input' bit field \r
272 * of the FFTC Queue x Destination Queue Register.\r
273 */\r
274 uint8_t bInputFFTShift;\r
275 \r
276 /** Input shift value to use.\r
277 *\r
278 * Corresponds to the 'FFT_variable_shift_input' bitfield of the FFTC\r
279 * Queue x Scaling & Shifting Register.\r
280 */\r
281 uint32_t inputShiftVal; \r
282 \r
283 /** CPPI Destination queue number where the \r
284 * FFT computation result needs to be put.\r
285 *\r
286 * Corresponds to 'dest_queue' bit field in the\r
287 * FFTC Queue X Destination Queue Register.\r
288 *\r
289 * MUST be set to '0x3FFF' if using FFTC higher\r
290 * layer APIs to configure queue.\r
291 */\r
292 uint32_t cppiDestQNum;\r
293 } Fftc_DestQRegCfg;\r
294 \r
295 \r
296 /** \r
297 * @brief Fftc_ScalingShiftingRegCfg\r
298 *\r
299 * Structure to specify/hold the FFTC Queue X Scaling and \r
300 * Shifting Register configuration info for a given \r
301 * FFTC queue.\r
302 */ \r
303 typedef struct _Fftc_ScalingShiftingRegCfg\r
304 {\r
305 /** Boolean flag, set to 1 to enable dynamic scaling, \r
306 * 0 for static scaling.\r
307 *\r
308 * Corresponds to the 'dynamic_scaling_en' bit field of the\r
309 * FFTC Queue x Scaling & Shifting Register.\r
310 */\r
311 uint8_t bDynamicScaleEnable; \r
312 \r
313 /** 8 bit number used as scaling factor, set to 0x80 to \r
314 * disable scaling.\r
315 *\r
316 * Corresponds to the 'output_scaling' bitfield of the FFTC\r
317 * Queue x Scaling & Shifting Register.\r
318 */\r
319 uint32_t outputScaleVal; \r
320 \r
321 /** Applicable for static scaling mode only, the shift value \r
322 * to use for each stage.\r
323 *\r
324 * Corresponds to the 'stage_6_scaling' ... 'stage_0_scaling'\r
325 * bit fields of the FFTC Queue x scaling and shifting register.\r
326 */\r
327 uint32_t radixScalingVal [FFTC_MAX_NUM_BUTTERFLY_STAGES];\r
328 \r
329 /** For static scaling mode only, shift to use at the\r
330 * output stage.\r
331 *\r
332 * Corresponds to the 'stage_out_scaling' bit field of the \r
333 * FFTC Queue x scaling and shifting register.\r
334 */\r
335 uint32_t radixScalingValLast; \r
336 \r
337 /** For static scaling mode only, the shift value to use \r
338 * when doing an LTE frequency shift. Used only when LTE \r
339 * Frequency Shift is enabled.\r
340 *\r
341 * Corresponds to the 'stage_lte_shift_scaling' bitfield\r
342 * of the FFTC Queue x scaling and shifting register.\r
343 */\r
344 uint32_t freqShiftScaleVal;\r
345 \r
346 } Fftc_ScalingShiftingRegCfg;\r
347 \r
348 \r
349 /** \r
350 * @brief Fftc_CyclicPrefixRegCfg\r
351 *\r
352 * Structure to specify/hold the FFTC Queue X Cyclic Prefix \r
353 * Register configuration info for a given FFTC queue.\r
354 */ \r
355 typedef struct _Fftc_CyclicPrefixRegCfg\r
356 {\r
357 /** Boolean Flag, set to 1 to enable Cyclic Prefix\r
358 * addition. Useful when sending data to antenna\r
359 * interface (AIF) directly.\r
360 */\r
361 uint8_t bCyclicPrefixAddEnable;\r
362 \r
363 /** Number of samples to use for cyclic prefix addition.\r
364 *\r
365 * Corresponds to 'cyclic_prefix_addition' bit field of the\r
366 * FFTC Queue X Cyclic Prefix Register.\r
367 *\r
368 * If cyclic prefix needs to be added to more than one\r
369 * block of the packet, then this value MUST be a \r
370 * multiple of 4.\r
371 */\r
372 uint32_t cyclicPrefixAddNum;\r
373 \r
374 /** Boolean Flag, set to 1 to program FFTC to ignore\r
375 * samples in the beginning of a packet data sent to FFTC.\r
376 * Useful when receiving data from Antenna Interface (AIF).\r
377 *\r
378 * Corresponds to 'cyclic_prefix_remove_en' bit field of the\r
379 * FFTC Queue X Cyclic Prefix Register.\r
380 */\r
381 uint8_t bCyclicPrefixRemoveEnable;\r
382 \r
383 /** Number of samples to ignore when Cyclic Prefix \r
384 * removal is enabled.\r
385 *\r
386 * Corresponds to 'cyclic_prefix_remove_offset' bit field of the\r
387 * FFTC Queue X Cyclic Prefix Register.\r
388 */\r
389 uint32_t cyclicPrefixRemoveNum;\r
390 \r
391 } Fftc_CyclicPrefixRegCfg;\r
392 \r
393 \r
394 /** \r
395 * @brief Fftc_ControlRegCfg\r
396 *\r
397 * Structure to specify/hold the FFTC Queue X Control \r
398 * Register configuration info for a given FFTC queue.\r
399 */ \r
400 typedef struct _Fftc_ControlRegCfg\r
401 {\r
402 /** DFT Block size in bytes - size of the transform \r
403 * \r
404 * Corresponds to the 'DFT_size' bit field of the FFTC \r
405 * Queue X Control Register. A list of the DFT block sizes\r
406 * supported by the FFTC hardware is documented in the \r
407 * FFTC User Guide.\r
408 */\r
409 uint32_t dftSize; \r
410 \r
411 /** DFT/IDFT selection configuration.\r
412 *\r
413 * Mode can be either 0 for an IFFT/IDFT, 1 for FFT/DFT. \r
414 * \r
415 * Corresponds to the 'DFT_IDFT_select' bit field of the FFTC \r
416 * Queue X Control Register.\r
417 */\r
418 Fftc_DFTMode dftMode;\r
419 \r
420 /** Not used on FFTC, always set to zero. */\r
421 uint8_t bEmulateDSP16x16;\r
422 \r
423 /** Boolean Flag, set to 1 to enable zero padding. */\r
424 uint8_t bZeroPadEnable;\r
425 \r
426 /** Zero Pad Mode. Mode can be either "add" or "multiply" \r
427 *\r
428 * Corresponds to the 'zero_pad_mode' bit field of the FFTC\r
429 * Queue X Control Register.\r
430 */\r
431 Fftc_ZeroPadMode zeroPadMode; \r
432 \r
433 /** The number of samples to use for zero padding in "Add" mode \r
434 * or the multiplication factor by which the oversampling needs\r
435 * to be done in "Multiply" mode for zero padding.\r
436 * Setting this to "0" disables zero padding in both modes.\r
437 *\r
438 * In "add" mode, this value must be a multiple of 4. In "multiply"\r
439 * mode, this value must be set such that the data length is a\r
440 * multiple of 4. Please consult the user guide for a table of\r
441 * legal values.\r
442 *\r
443 * Corresponds to the 'zero_pad_val' bit field of the FFTC\r
444 * Queue X Control Register.\r
445 */\r
446 uint32_t zeroPadFactor;\r
447 \r
448 /** Boolean flag, set to 1 to supress FFTC side info such as\r
449 * block exponent, clipping detection, error and tag being \r
450 * output.\r
451 *\r
452 * Corresponds to the 'supress_side_info' bit field of the FFTC\r
453 * Queue X Control Register.\r
454 */\r
455 uint8_t bSupressSideInfo;\r
456 \r
457 /** Boolean flag, set to 1 to reverse I/Q order assumend on the input.\r
458 *\r
459 * Corresponds to the 'iq_order' bit field of the FFTC\r
460 * Queue X Control Register.\r
461 */\r
462 uint8_t bIqOrder;\r
463 \r
464 /** Boolean flag, set to 1 to use 8-bit I/Q format. The order convention\r
465 * is followed using iq_order.\r
466 *\r
467 * The 8-bit sample mode has some restrictions\r
468 * 1) Cyclic prefix removal is not supported.\r
469 * 2) DFT size must be a multiple of 8 samples.\r
470 * DFT sizes NOT supported are 4, 12, 36, 60, 108, 180, 324,\r
471 * 972, 540, 300, 900\r
472 * 3) The resulting data length from zero padding must be a multiple of 8.\r
473 *\r
474 * Corresponds to the 'iq_size' bit field of the FFTC\r
475 * Queue X Control Register.\r
476 */\r
477 uint8_t bIqSize;\r
478 \r
479 } Fftc_ControlRegCfg;\r
480 \r
481 \r
482 /** \r
483 * @brief Fftc_FreqShiftRegCfg\r
484 *\r
485 * Structure to specify/hold the FFTC Queue X LTE Frequency \r
486 * Shift Register configuration info for a given FFTC queue.\r
487 */ \r
488 typedef struct _Fftc_FreqShiftRegCfg\r
489 {\r
490 /** Boolean Flag, set to 1 to enable LTE Frequency Shifting of \r
491 * the sample at input.\r
492 *\r
493 * Corresponds to the 'lte_freq_shift_en' bit field of the\r
494 * FFTC Queue X LTE Frequency Shift Register.\r
495 */\r
496 uint8_t bFreqShiftEnable;\r
497 \r
498 /** Twiddle factor to use. Valid values are 6144 * 2 / 8192 * 2 (M)\r
499 * Set to 0 for M = 16384 and 1 for M = 12288\r
500 *\r
501 * Corresponds to the 'lte_freq_shift_index' bit field of the\r
502 * FFTC Queue X LTE Frequency Shift Register.\r
503 */\r
504 Fftc_FreqShiftIndex freqShiftIndex;\r
505 \r
506 /** LTE Frequency Shift multiplication factor (a)\r
507 *\r
508 * Corresponds to the 'lte_freq_shift_factor' bit field of the\r
509 * FFTC Queue X LTE Frequency Shift Register.\r
510 */\r
511 uint32_t freqShiftMultFactor;\r
512 \r
513 /** LTE Frequency Shift Phase offset (n0)\r
514 *\r
515 * Corresponds to the 'lte_freq_shift_phase' bit field of the\r
516 * FFTC Queue X LTE Frequency Shift Register.\r
517 */\r
518 uint32_t freqShiftInitPhase;\r
519 \r
520 /** LTE Frequency Shift Direction (+ :- 0 / - :- 1).\r
521 *\r
522 * Corresponds to the 'lte_freq_shift_dir' bit field of the\r
523 * FFTC Queue X LTE Frequency Shift Register.\r
524 */\r
525 Fftc_FreqShiftDir freqShiftDirection;\r
526 \r
527 } Fftc_FreqShiftRegCfg;\r
528 \r
529 \r
530 /** \r
531 * @brief Fftc_QLocalCfg\r
532 *\r
533 * Structure to specify/hold the queue specific configuration \r
534 * for a given FFTC queue.\r
535 */ \r
536 typedef struct _Fftc_QLocalCfg\r
537 {\r
538 /** Destination Queue register configuration instance. */ \r
539 Fftc_DestQRegCfg destQRegConfig;\r
540 \r
541 /** Scaling and Shifting register configuration instance. */ \r
542 Fftc_ScalingShiftingRegCfg scalingShiftingRegConfig;\r
543 \r
544 /** Cyclic Prefix register configurartion instance. */\r
545 Fftc_CyclicPrefixRegCfg cyclicPrefixRegConfig;\r
546 \r
547 /** Control register configuration instance. */\r
548 Fftc_ControlRegCfg controlRegConfig;\r
549 \r
550 /** LTE Frequency Shift register configuration instance. */\r
551 Fftc_FreqShiftRegCfg freqShiftRegConfig;\r
552 \r
553 } Fftc_QLocalCfg;\r
554 \r
555 /** \r
556 * @brief Fftc_GlobalCfg\r
557 * \r
558 * FFTC Global configuration structure to be used to\r
559 * hold/specify the configuration for the FFTC Configuration\r
560 * Register.\r
561 */ \r
562 typedef struct _Fftc_GlobalCfg\r
563 {\r
564 /** Flow ID to use for overriding CPPI packets received\r
565 * from FFTC queue n.\r
566 *\r
567 * Corresponds to the 'qn_flowid_overwrite' bit field of\r
568 * the FFTC Configuration Register.\r
569 */\r
570 uint32_t queueFlowidOverwrite [FFTC_MAX_NUM_TXQUEUES]; \r
571 \r
572 /** The maximum amount of time beyond which the\r
573 * FFTC scheduler must service a queue. Values can\r
574 * range between "0x1" and "0xff". When set to "0"\r
575 * the starvation preventing mechanism in the scheduler\r
576 * will be disabled.\r
577 *\r
578 * Corresponds to the 'starvation_period' bit field of\r
579 * the FFTC Configuration Register.\r
580 */\r
581 uint32_t starvationPeriodVal;\r
582 \r
583 /** FFTC Queue priority.\r
584 * Valid values are between "0" and "3", "0" being\r
585 * the highest.\r
586 *\r
587 * Corresponds to the 'queue_n_priority' bit field of\r
588 * the FFTC Configuration Register where 0 <= n <= 3.\r
589 */ \r
590 uint32_t queuePriority [FFTC_MAX_NUM_TXQUEUES];\r
591 \r
592 /** Boolean flag, set to 1 to disable the FFT calculation. \r
593 * Useful for debugging.\r
594 *\r
595 * Corresponds to the 'FFT_disabled' bit field of the\r
596 * FFTC Configuration Register.\r
597 */\r
598 uint8_t bDisableFFT;\r
599 \r
600 } Fftc_GlobalCfg;\r
601 \r
602 \r
603 /** \r
604 * @brief Fftc_ControlHdr\r
605 * \r
606 * Configuration structure that can be \r
607 * used by the application/driver to setup\r
608 * a FFTC control header using the LLD APIs.\r
609 */ \r
610 typedef struct _Fftc_ControlHdr\r
611 {\r
612 /** Length of the protocol specific field that \r
613 * should be forwarded to the receiver in 32-bit words. \r
614 * Valid values can be between "1" and "4".\r
615 */\r
616 uint32_t psFieldLen;\r
617 \r
618 /** DFT size list length in 32-bit words. Can be between \r
619 * "1" and "128".\r
620 */\r
621 uint32_t dftSizeListLen;\r
622 \r
623 /** Boolean Flag, set to 1 to indicate that there is\r
624 * a protocol specific field that must be forwarded to\r
625 * the receiver.\r
626 */\r
627 uint8_t bPSPassThruPresent;\r
628 \r
629 /** Boolean flag, set to 1 to indicate that the DFT \r
630 * size list is configured.\r
631 */\r
632 uint8_t bDFTSizeListPresent;\r
633 \r
634 /** Boolean flag, set to 1 to indicate that the five\r
635 * local control registers are present, configuration\r
636 * that follows must be five 32-bit words long only.\r
637 */\r
638 uint8_t bLocalConfigPresent;\r
639 \r
640 } Fftc_ControlHdr;\r
641 \r
642 \r
643 /** \r
644 * @brief Fftc_QLocalCfgParams\r
645 * \r
646 * Configuration structure that is used by the FFTC\r
647 * LLD *internally* to format the FFTC queue configuration\r
648 * provided by an application/driver to an acceptable\r
649 * format by the FFT Hardware.\r
650 */\r
651 typedef struct _Fftc_QLocalCfgParams\r
652 {\r
653 /** Holds the data that needs to be written to\r
654 * FFTC Queue x Destination Queue Register.\r
655 */\r
656 uint32_t queuexDestQ;\r
657 \r
658 /** Holds the data that needs to be written to\r
659 * FFTC Queue x Scaling & Shifting Register.\r
660 */\r
661 uint32_t queuexScaleShift;\r
662 \r
663 /** Holds the data that needs to be written to\r
664 * FFTC Queue x Cyclic Prefix Register.\r
665 */\r
666 uint32_t queuexCyclicPrefix;\r
667 \r
668 /** Holds the data that needs to be written to\r
669 * FFTC Queue x Control Register.\r
670 */\r
671 uint32_t queuexControl;\r
672 \r
673 /** Holds the data that needs to be written to\r
674 * FFTC Queue x LTE Frequency Shift Register.\r
675 */\r
676 uint32_t queuexLteFreq; \r
677 } Fftc_QLocalCfgParams;\r
678 \r
679 /** \r
680 * @brief Fftc_PeripheralIdParams\r
681 * \r
682 * Configuration structure that can be used\r
683 * to setup the FFTC Peripheral ID Register.\r
684 */\r
685 typedef struct _Fftc_PeripheralIdParams\r
686 {\r
687 /** Fixed module ID. */ \r
688 uint32_t function;\r
689 \r
690 /** RTL Version Number (R) */\r
691 uint32_t rtlVersion;\r
692 \r
693 /** Major Version Number (X) */\r
694 uint32_t majorNum;\r
695 \r
696 /** Custom Version Number */\r
697 uint32_t customNum;\r
698 \r
699 /** Minor Version Number (Y) */\r
700 uint32_t minorNum;\r
701 } Fftc_PeripheralIdParams;\r
702 \r
703 /** \r
704 * @brief Fftc_EmulationControlParams\r
705 * \r
706 * Configuration structure that can be used to\r
707 * setup the FFTC Emulation Control Parameters.\r
708 */\r
709 typedef struct _Fftc_EmulationControlParams\r
710 {\r
711 /** This bit specifies whether the FFTC H/w should\r
712 * monitor the "emususp" or "emususp_rt" signal for\r
713 * emulation suspend.\r
714 * When set to:\r
715 * 0 - FFTC monitors "emususp" signal (and ignores "emususp_rt")\r
716 * 1 - FFTC monitors "emususp_rt" signal (and ignores "emususp")\r
717 */\r
718 uint8_t bEmuRtSel;\r
719 \r
720 /** This bit indicates whether FFTC should perform a \r
721 * hard stop / soft stop when emulation halt signal is asserted.\r
722 * Set to 1 for emulation soft stop and 0 for emulation hard stop.\r
723 */\r
724 uint8_t bEmuSoftStop;\r
725 \r
726 /** This bit controls FFTC's response to Emulation suspend\r
727 * signal that it has been programmed to monitor.\r
728 * When set to:\r
729 * 0 - FFTC suspends according to mode specified by bEmuSoftStop \r
730 * field.\r
731 * 1 - FFTC ignores suspend signal and operates normally.\r
732 */\r
733 uint8_t bEmuFreeRun;\r
734 \r
735 } Fftc_EmulationControlParams;\r
736 \r
737 /** \r
738 * @brief Fftc_ErrorParams\r
739 * \r
740 * Configuration structure that can be used to\r
741 * hold/setup the FFTC Emulation Control Parameters.\r
742 */\r
743 typedef struct _Fftc_ErrorParams\r
744 {\r
745 /** Interrupt on EOP is triggered when a CPPI descriptor\r
746 * that has the bit 2 of its PS field set is completed\r
747 * and written to Rx destination queue of FFTC in QM.\r
748 */\r
749 uint8_t bIsIntOnEOP;\r
750 \r
751 /** Debug Halt is triggered when a CPPI descriptor that\r
752 * has bit 1 of its PS field set and is received by the\r
753 * FFTC.\r
754 */\r
755 uint8_t bIsDebugHalt;\r
756 \r
757 /** This bit is set when FFTC detects an error in\r
758 * configuration of the incoming FFT block.\r
759 */\r
760 uint8_t bIsConfigWordError;\r
761 \r
762 /** This bit is set when FFTC runs out free buffers to use\r
763 * when trying to send a packet.\r
764 */\r
765 uint8_t bIsDescBufferError;\r
766 \r
767 /** This bit is set when the packet length is not a multiple\r
768 * of the FFT block length size.\r
769 */\r
770 uint8_t bIsEopError;\r
771 \r
772 /** This bit is set when the length of the configuration \r
773 * field in the PS field is not as per the length specified\r
774 * in the FFTC control header.\r
775 */\r
776 uint8_t bIsConfigInvalError;\r
777 } Fftc_ErrorParams;\r
778 \r
779 typedef Fftc_DestQRegCfg Fftc_DestQStatusReg;\r
780 typedef Fftc_ScalingShiftingRegCfg Fftc_ScalingShiftingStatusReg;\r
781 typedef Fftc_CyclicPrefixRegCfg Fftc_CyclicPrefixStatusReg;\r
782 \r
783 /** \r
784 * @brief Fftc_ControlStatusReg\r
785 *\r
786 * Structure to hold the contents of Block\r
787 * X Control Status Register.\r
788 */ \r
789 typedef struct _Fftc_ControlStatusReg\r
790 {\r
791 /** Reflects the DFT size used. In case a DFT list is\r
792 * used, this field will reflect the size used from the \r
793 * DFT list. In case there is only one block, this size\r
794 * will be same as the size configured in FFTC Queue X\r
795 * Control register.\r
796 * \r
797 * Corresponds to the 'DFT_size_stat' bit field of the Block\r
798 * X Control Status register.\r
799 */\r
800 uint32_t dftSize; \r
801 \r
802 /** DFT/IDFT selection status.\r
803 *\r
804 * Mode can be either 0 for an IFFT/IDFT, 1 for FFT/DFT. \r
805 * \r
806 * Corresponds to the 'DFT_IDFT_select' bit field of the Block\r
807 * X Control Status register.\r
808 */\r
809 Fftc_DFTMode dftMode;\r
810 \r
811 /** Boolean flag, is set to 1 to indicate that FFTC is programmed to\r
812 * supress FFTC side info such as block exponent, clipping detection, \r
813 * error and tag being output.\r
814 *\r
815 * Corresponds to the 'supress_side_info' bit field of the Block\r
816 * X Control Status register.\r
817 */\r
818 uint8_t bSupressSideInfo;\r
819 \r
820 /** Indicates the queue number from which this block has \r
821 * originated.\r
822 *\r
823 * Corresponds to the 'input_queue_num' bit of Block X Control\r
824 * Status Register.\r
825 */\r
826 Fftc_QueueId inputQNum; \r
827 \r
828 /** Boolean flag, indicates if this block was the first block \r
829 * of the packet.\r
830 *\r
831 * Corresponds to the 'SOP' bit of Block X Control\r
832 * Status Register.\r
833 */\r
834 uint8_t bIsSOP;\r
835 \r
836 /** Boolean flag, indicates if this block was the last block \r
837 * of the packet.\r
838 *\r
839 * Corresponds to the 'EOP' bit of Block X Control\r
840 * Status Register.\r
841 */\r
842 uint8_t bIsEOP;\r
843 \r
844 /** Boolean flag, indicates whether this block for which the status \r
845 * is being retrieved contains an error.\r
846 *\r
847 * Corresponds to the 'block_error' field of the Block X\r
848 * Control Status Register.\r
849 */\r
850 uint8_t bIsBlockError;\r
851 \r
852 /** The number of samples used for zero padding in "Add" mode \r
853 * or the multiplication factor by which the oversampling \r
854 * was done in "Multiply" mode for zero padding on this block.\r
855 * "0" indicates that zero padding was disabled for the block.\r
856 *\r
857 * Corresponds to the 'zero_pad_val' bit field of the Block X \r
858 * Control Status Register.\r
859 */\r
860 uint32_t zeroPadFactor;\r
861 \r
862 /** Zero Pad Mode. Mode can be either "add" or "multiply".\r
863 *\r
864 * Corresponds to the 'zero_pad_mode' bit field of the Block X\r
865 * Control Status Register.\r
866 */\r
867 Fftc_ZeroPadMode zeroPadMode; \r
868 \r
869 } Fftc_ControlStatusReg;\r
870 \r
871 typedef Fftc_FreqShiftRegCfg Fftc_FreqShiftStatusReg;\r
872 \r
873 \r
874 /** \r
875 * @brief Fftc_PktSizeStatusReg\r
876 *\r
877 * Structure to hold the contents of Block\r
878 * X Packet Size Status Register.\r
879 */ \r
880 typedef struct _Fftc_PktSizeStatusReg\r
881 {\r
882 /** The entire packet size for this block.\r
883 *\r
884 * Corresponds to the 'Packet_size' bit of the\r
885 * Block X Packet Size Status Register.\r
886 */\r
887 uint32_t pktSize; \r
888 \r
889 }Fftc_PktSizeStatusReg;\r
890 \r
891 /** \r
892 * @brief Fftc_TagStatusReg\r
893 *\r
894 * Structure to hold the contents of Block\r
895 * X Tag Status Register.\r
896 */ \r
897 typedef struct _Fftc_TagStatusReg\r
898 {\r
899 /** Destination tag used to identify packets\r
900 * for FFTC.\r
901 *\r
902 * Corresponds to the 'dest_tag' bit of the\r
903 * Block X Tag Status Register.\r
904 */\r
905 uint32_t destTag; \r
906 \r
907 /** Flow Id associated with this block.\r
908 *\r
909 * Corresponds to the 'flow_id' bit of the\r
910 * Block X Tag Status Register.\r
911 */\r
912 uint32_t flowId; \r
913 \r
914 /** Source Id associated with this block.\r
915 *\r
916 * Corresponds to the 'src_id' bit of the\r
917 * Block X Tag Status Register.\r
918 */\r
919 uint32_t srcId; \r
920 \r
921 }Fftc_TagStatusReg;\r
922 \r
923 \r
924 /**\r
925 @}\r
926 */\r
927 \r
928 extern int32_t Fftc_mapDFTSizeToIndex (\r
929 uint32_t dftBlockSize\r
930 );\r
931 \r
932 extern int32_t Fftc_compileQueueLocalConfigParams (\r
933 Fftc_QLocalCfg* pFFTLocalCfg, \r
934 uint8_t* pData,\r
935 uint32_t* pLen\r
936 );\r
937 \r
938 extern int32_t Fftc_recompileQueueLocalDFTParams (\r
939 int32_t dftSize, \r
940 Fftc_DFTMode dftMode, \r
941 uint8_t* pData\r
942 );\r
943 \r
944 extern int32_t Fftc_recompileQueueLocalCyclicPrefixParams (\r
945 int32_t cyclicPrefixLen, \r
946 uint8_t* pData\r
947 );\r
948 \r
949 extern int32_t Fftc_createControlHeader (\r
950 Fftc_ControlHdr* pFFTCfgCtrlHdr, \r
951 uint8_t* pData,\r
952 uint32_t* pLen\r
953 );\r
954 \r
955 extern int32_t Fftc_modifyLocalCfgPresentControlHeader (\r
956 int32_t bLocalConfigPresent, \r
957 uint8_t* pData\r
958 );\r
959 \r
960 extern int32_t Fftc_createDftSizeList (\r
961 uint16_t* pDftSizeList, \r
962 uint32_t dftSizeListLen, \r
963 uint8_t* pData, \r
964 uint32_t* pLen\r
965 );\r
966 \r
967 extern int32_t Fftc_lldOpen \r
968 (\r
969 uint8_t instNum,\r
970 void* cfgRegs,\r
971 Fftc_LldObj* pFFTCLldObj\r
972 );\r
973 \r
974 extern int32_t Fftc_lldClose \r
975 (\r
976 Fftc_LldObj* pFFTCLldObj\r
977 );\r
978 \r
979 extern int32_t Fftc_readPidReg (\r
980 Fftc_LldObj* pFFTCLldObj,\r
981 Fftc_PeripheralIdParams* pPIDCfg\r
982 );\r
983 \r
984 extern int32_t Fftc_readGlobalConfigReg (\r
985 Fftc_LldObj* pFFTCLldObj,\r
986 Fftc_GlobalCfg* pFFTGlobalCfg\r
987 );\r
988 \r
989 extern int32_t Fftc_writeGlobalConfigReg (\r
990 Fftc_LldObj* pFFTCLldObj,\r
991 Fftc_GlobalCfg* pFFTGlobalCfg\r
992 );\r
993 \r
994 extern void Fftc_doSoftwareReset (\r
995 Fftc_LldObj* pFFTCLldObj\r
996 );\r
997 \r
998 extern void Fftc_doSoftwareContinue (\r
999 Fftc_LldObj* pFFTCLldObj\r
1000 );\r
1001 \r
1002 extern int32_t Fftc_isHalted (\r
1003 Fftc_LldObj* pFFTCLldObj\r
1004 );\r
1005 \r
1006 extern int32_t Fftc_writeEmulationControlReg (\r
1007 Fftc_LldObj* pFFTCLldObj,\r
1008 Fftc_EmulationControlParams* pEmulationCfg\r
1009 );\r
1010 \r
1011 extern int32_t Fftc_readEmulationControlReg (\r
1012 Fftc_LldObj* pFFTCLldObj,\r
1013 Fftc_EmulationControlParams* pEmulationCfg\r
1014 );\r
1015 \r
1016 extern int32_t Fftc_writeEoiReg (\r
1017 Fftc_LldObj* pFFTCLldObj,\r
1018 int32_t eoiVal\r
1019 );\r
1020 \r
1021 extern int32_t Fftc_readEoiReg (\r
1022 Fftc_LldObj* pFFTCLldObj\r
1023 );\r
1024 \r
1025 extern void Fftc_clearQueueClippingDetectReg (\r
1026 Fftc_LldObj* pFFTCLldObj,\r
1027 Fftc_QueueId qNum\r
1028 );\r
1029 \r
1030 extern int32_t Fftc_readQueueClippingDetectReg (\r
1031 Fftc_LldObj* pFFTCLldObj,\r
1032 Fftc_QueueId qNum\r
1033 );\r
1034 \r
1035 extern int32_t Fftc_writeQueueConfigRegs (\r
1036 Fftc_LldObj* pFFTCLldObj,\r
1037 Fftc_QueueId qNum, \r
1038 Fftc_QLocalCfg* pFFTLocalCfg\r
1039 );\r
1040 \r
1041 extern int32_t Fftc_readQueueConfigRegs (\r
1042 Fftc_LldObj* pFFTCLldObj,\r
1043 Fftc_QueueId qNum, \r
1044 Fftc_QLocalCfg* pFFTLocalCfg\r
1045 );\r
1046 \r
1047 extern int32_t Fftc_writeDftSizeListGroupReg (\r
1048 Fftc_LldObj* pFFTCLldObj,\r
1049 uint16_t* pDftSizeList, \r
1050 uint32_t dftSizeListLen\r
1051 );\r
1052 \r
1053 extern int32_t Fftc_readDftSizeListGroupReg (\r
1054 Fftc_LldObj* pFFTCLldObj,\r
1055 uint16_t* pDftSizeList\r
1056 );\r
1057 \r
1058 extern int32_t Fftc_readBlockDestQStatusReg (\r
1059 Fftc_LldObj* pFFTCLldObj,\r
1060 Fftc_DestQStatusReg* pFFTDestQStatus\r
1061 );\r
1062 \r
1063 extern int32_t Fftc_readBlockShiftStatusReg (\r
1064 Fftc_LldObj* pFFTCLldObj,\r
1065 Fftc_ScalingShiftingStatusReg* pFFTShiftStatus\r
1066 );\r
1067 \r
1068 extern int32_t Fftc_readBlockCyclicPrefixStatusReg (\r
1069 Fftc_LldObj* pFFTCLldObj,\r
1070 Fftc_CyclicPrefixStatusReg* pFFTCyclicStatus\r
1071 );\r
1072 \r
1073 extern int32_t Fftc_readBlockControlStatusReg (\r
1074 Fftc_LldObj* pFFTCLldObj,\r
1075 Fftc_ControlStatusReg* pFFTControlStatus\r
1076 );\r
1077 \r
1078 extern int32_t Fftc_readBlockFreqShiftStatusReg (\r
1079 Fftc_LldObj* pFFTCLldObj,\r
1080 Fftc_FreqShiftStatusReg* pFFTFreqShiftStatus\r
1081 );\r
1082 \r
1083 extern int32_t Fftc_readBlockPktSizeStatusReg (\r
1084 Fftc_LldObj* pFFTCLldObj,\r
1085 Fftc_PktSizeStatusReg* pFFTPktSizeStatus\r
1086 );\r
1087 \r
1088 extern int32_t Fftc_readBlockTagStatusReg (\r
1089 Fftc_LldObj* pFFTCLldObj,\r
1090 Fftc_TagStatusReg* pFFTTagStatus\r
1091 );\r
1092 \r
1093 extern int32_t Fftc_readErrorIntRawStatusReg (\r
1094 Fftc_LldObj* pFFTCLldObj,\r
1095 Fftc_QueueId qNum, \r
1096 Fftc_ErrorParams* pErrorCfg\r
1097 );\r
1098 \r
1099 extern int32_t Fftc_clearErrorIntRawStatusReg (\r
1100 Fftc_LldObj* pFFTCLldObj,\r
1101 Fftc_QueueId qNum, \r
1102 Fftc_ErrorParams* pErrorCfg\r
1103 );\r
1104 \r
1105 extern int32_t Fftc_writeErrorIntEnableSetReg (\r
1106 Fftc_LldObj* pFFTCLldObj,\r
1107 Fftc_QueueId qNum, \r
1108 Fftc_ErrorParams* pErrorCfg\r
1109 );\r
1110 \r
1111 extern int32_t Fftc_readErrorIntEnableSetReg (\r
1112 Fftc_LldObj* pFFTCLldObj,\r
1113 Fftc_QueueId qNum, \r
1114 Fftc_ErrorParams* pErrorCfg\r
1115 );\r
1116 \r
1117 extern int32_t Fftc_clearErrorIntEnableReg (\r
1118 Fftc_LldObj* pFFTCLldObj,\r
1119 Fftc_QueueId qNum, \r
1120 Fftc_ErrorParams* pErrorCfg\r
1121 );\r
1122 \r
1123 extern int32_t Fftc_writeHaltOnErrorReg (\r
1124 Fftc_LldObj* pFFTCLldObj,\r
1125 Fftc_QueueId qNum, \r
1126 Fftc_ErrorParams* pErrorCfg\r
1127 );\r
1128 \r
1129 extern int32_t Fftc_readHaltOnErrorReg (\r
1130 Fftc_LldObj* pFFTCLldObj,\r
1131 Fftc_QueueId qNum, \r
1132 Fftc_ErrorParams* pErrorCfg\r
1133 );\r
1134 \r
1135 #ifdef __cplusplus\r
1136 }\r
1137 #endif\r
1138 \r
1139 #endif /* __FFTC_LLD_H__ */\r