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author | Murtaza Gaadiwala <murtaza@ti.com> | |
Sat, 8 Dec 2012 02:12:10 +0000 (21:12 -0500) | ||
committer | Murtaza Gaadiwala <murtaza@ti.com> | |
Sat, 8 Dec 2012 02:12:10 +0000 (21:12 -0500) |
25 files changed:
diff --git a/device/k2l/src/fftc_device_cfg.c b/device/k2l/src/fftc_device_cfg.c
--- /dev/null
@@ -0,0 +1,119 @@
+/**
+ * @file fftc_device_cfg.c
+ *
+ * @brief
+ * This file contains APIs that are used by the driver to retrieve
+ * SoC specific configuration for FFTC.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2012, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+/* FFTC types include */
+#include <fftc_types.h>
+
+/* SoC definitions file */
+#include <ti/csl/soc.h>
+
+/* CHIP module include */
+#include <ti/csl/csl_chip.h>
+
+/** @addtogroup FFTC_FUNCTION
+ @{ */
+
+/**
+* ============================================================================
+* @n@b Fftc_getDeviceAccumulatorConfig
+*
+* @b brief
+* @n Given an FFTC instance number, this function retrieves any SoC specific
+* QM accumulator configuration such as accumulator channel number, queue
+* number to use for the FFTC interrupt setup by the driver.
+*
+* @param[in]
+* instNum FFTC instance number for which the configuration needs
+* to be retrieved.
+*
+* @param[out]
+* pAccChannelNum Pointer to hold the accumulator channel returned by
+* this function.
+*
+* @param[out]
+* pAccRxQNum Pointer to hold the Rx queue number returned by
+* this function.
+*
+* @return Int32
+* -1 - Error populating accumulator configuration.
+* 0 - Success. Configuration successfully populated
+* in output parameter handles.
+*
+* @pre
+* @n None.
+*
+* @post
+* @n SoC specific accumulator configuration returned.
+* ============================================================================
+*/
+Int32 Fftc_getDeviceAccumulatorConfig
+(
+ uint8_t instNum,
+ uint8_t* pAccChannelNum,
+ uint16_t* pAccRxQNum
+)
+{
+ uint8_t coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);
+
+ /* Pick the accumulator channel and a Rx queue number to
+ * use for the FFTC instance specified on this core.
+ */
+ if (instNum == CSL_FFTC_0)
+ {
+ *pAccChannelNum = 8;
+ *pAccRxQNum = 712;
+ }
+ else
+ {
+ *pAccChannelNum = 24;
+ *pAccRxQNum = 724;
+ }
+ *pAccChannelNum += coreNum;
+ *pAccRxQNum += coreNum;
+
+ /* Return success. */
+ return 0;
+}
+
+/**
+@}
+*/
+
+
index 82a23b8b31fc071d6a6531cedaa55db46f330b03..7447ef2c71ec850f86a708a5145eaa191dd0368c 100755 (executable)
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diff --git a/example/MultiCore/k2l/c66/bios/fftc.cfg b/example/MultiCore/k2l/c66/bios/fftc.cfg
--- /dev/null
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2009 by Texas Instruments Incorporated.
+ *
+ * All rights reserved. Property of Texas Instruments Incorporated.
+ * Restricted rights to use, duplicate or disclose this code are
+ * granted through contract.
+ *
+ */
+
+/* THIS FILE WAS GENERATED BY ti.sysbios.genx */
+
+/*
+ * ======== fftc.cfg ========
+ *
+ */
+
+/* Load all required BIOS/XDC runtime packages */
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var Log = xdc.useModule('xdc.runtime.Log');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
+var ECM = xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
+
+/* Load the FFTC package */
+var Fftc = xdc.useModule('ti.drv.fftc.Settings');
+
+/* Load the CSL package */
+var Csl = xdc.useModule('ti.csl.Settings');
+
+/* Load the CPPI package */
+var Cppi = xdc.useModule('ti.drv.cppi.Settings');
+
+/* Load the QMSS package */
+var Qmss = xdc.useModule('ti.drv.qmss.Settings');
+
+/* Device specific configuration */
+var devName = "k2l";
+Csl.deviceType = devName;
+
+var System = xdc.useModule('xdc.runtime.System');
+SysStd = xdc.useModule('xdc.runtime.SysStd');
+System.SupportProxy = SysStd;
+
+
+/* Create a default system heap using ti.bios.HeapMem. */
+var heapMemParams1 = new HeapMem.Params;
+heapMemParams1.size = 8192 * 30;
+heapMemParams1.sectionName = "systemHeap";
+Program.global.heap0 = HeapMem.create(heapMemParams1);
+
+/* This is the default memory heap. */
+Memory.defaultHeapInstance = Program.global.heap0;
+
+Program.sectMap["systemHeap"] = Program.platform.stackMemory;
+
+/****** IPC - Shared Memory Settings ********/
+/* IPC packages */
+var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');
+var Settings = xdc.module('ti.sdo.ipc.family.Settings');
+var ListMP = xdc.useModule('ti.sdo.ipc.ListMP');
+var GateMP = xdc.useModule('ti.sdo.ipc.GateMP');
+var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
+var HeapMemMP = xdc.useModule('ti.sdo.ipc.heaps.HeapMemMP');
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+var memmap = Program.cpu.memoryMap;
+
+Startup = xdc.useModule('xdc.runtime.Startup');
+Startup.firstFxns.$add('&myStartupFxn');
+
+/* Configure the shared memory heap for shared memory allocations required by the
+ * CPPI and QMSS Libraries */
+SharedRegion.translate = false;
+
+/* Create a shared memory heap */
+MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2", "CORE3"]);
+
+/* Synchronize all processors (this will be done in Ipc_start) */
+Ipc.procSync = Ipc.ProcSync_ALL;
+
+/* To avoid wasting shared memory for Notify and MessageQ transports */
+for (var i = 0; i < MultiProc.numProcessors; i++) {
+ Ipc.setEntryMeta({
+ remoteProcId: i,
+ setupNotify: false,
+ setupMessageQ: false,
+ });
+}
+
+/* Create a shared memory */
+SharedRegion.setEntryMeta(0,
+ { base: 0x0C010000,
+ len: 0x00100000,
+ ownerProcId: 0,
+ isValid: true,
+ name: "sharemem",
+ });
+
+/* Enable BIOS Task Scheduler */
+BIOS.taskEnabled = true;
+
+/*
+ * Enable Event Groups here and registering of ISR for specific GEM INTC is done
+ * using EventCombiner_dispatchPlug() and Hwi_eventMap() APIs
+ */
+
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+/*
+ * @(#) ti.sysbios.genx; 2, 0, 0, 0,275; 4-29-2009 15:45:06; /db/vtree/library/trees/avala/avala-k25x/src/
+ */
+
diff --git a/example/MultiCore/k2l/c66/bios/fftcMCK2LC66BiosExampleProject.txt b/example/MultiCore/k2l/c66/bios/fftcMCK2LC66BiosExampleProject.txt
--- /dev/null
@@ -0,0 +1,8 @@
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/example/MultiCore/src/multicore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/example/MultiCore/k2l/c66/bios/multicore_osal.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/example/MultiCore/k2l/c66/bios/fftc_linker.cmd"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/example/MultiCore/k2l/c66/bios/fftc.cfg"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2l/src/cppi_device.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2l/src/qmss_device.c"
+-ccs.setCompilerOptions "-mv6600 -g -DDEVICE_K2L --diag_warning=225 -I${PDK_INSTALL_PATH} -I${FFTC_INSTALL_PATH} -I${FFTC_INSTALL_PATH}/ti/drv/fftc/example/MultiCore/src"
+-rtsc.enableRtsc
diff --git a/example/MultiCore/k2l/c66/bios/fftc_linker.cmd b/example/MultiCore/k2l/c66/bios/fftc_linker.cmd
--- /dev/null
@@ -0,0 +1,7 @@
+SECTIONS
+{
+ .qmss: load >> MSMCSRAM
+ .cppi: load >> MSMCSRAM
+ .fftc: load >> MSMCSRAM
+ .init_array: load >> L2SRAM
+}
diff --git a/example/MultiCore/k2l/c66/bios/multicore_osal.c b/example/MultiCore/k2l/c66/bios/multicore_osal.c
--- /dev/null
@@ -0,0 +1,1184 @@
+/**
+ * @file multicore_osal.c
+ *
+ * @brief
+ * This is a sample OS Abstraction Layer (AL) file implemented
+ * using XDC/BIOS APIs.
+ *
+ * System integrator is advised to review these implementations and
+ * modify them to suit it to application requirements.
+ *
+ * This OSAL implementation uses the <b> Approach 1 </b> documented.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2009, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+/* Standard C-native includes */
+#include <stdlib.h>
+#include <string.h>
+
+/* XDC/BIOS includes */
+#include <xdc/std.h>
+#include <xdc/runtime/IHeap.h>
+#include <xdc/runtime/System.h>
+#include <xdc/runtime/Memory.h>
+#include <xdc/runtime/Error.h>
+
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/hal/Hwi.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/heaps/HeapBuf.h>
+#include <ti/sysbios/heaps/HeapMem.h>
+#include <ti/sysbios/knl/Semaphore.h>
+
+#include <xdc/cfg/global.h>
+
+/* IPC includes */
+#include <ti/ipc/GateMP.h>
+#include <ti/ipc/Ipc.h>
+#include <ti/ipc/ListMP.h>
+#include <ti/ipc/SharedRegion.h>
+
+/* CSL CHIP, SEM Functional layer includes */
+#include <ti/csl/csl_chip.h>
+#include <ti/csl/csl_chipAux.h>
+#include <ti/csl/csl_semAux.h>
+
+/* CSL Cache module includes */
+#include <ti/csl/csl_cache.h>
+#include <ti/csl/csl_cacheAux.h>
+
+/* CSL XMC includes */
+#include <ti/csl/csl_xmc.h>
+#include <ti/csl/csl_xmcAux.h>
+
+/**********************************************************************
+ ****************************** Defines *******************************
+ **********************************************************************/
+
+/* Number of cores on c6498 */
+#define NUM_CORES 4
+
+/* Hardware Semaphore to synchronize access from
+ * multiple FFTC applications across different cores to
+ * the FFTC driver.
+ */
+#define FFTC_HW_SEM 2
+
+/* Hardware Semaphore to synchronize access from
+ * multiple applications (FFTC applications and non-FFTC applications)
+ * across different cores to the QMSS library.
+ */
+#define QMSS_HW_SEM 3
+
+/* Hardware Semaphore to synchronize access from
+ * multiple applications (FFTC applications and non-FFTC applications)
+ * across different cores to the CPPI library.
+ */
+#define CPPI_HW_SEM 4
+
+
+/**********************************************************************
+ ************************** Global Variables **************************
+ **********************************************************************/
+UInt32 fftcMallocCounter = 0;
+UInt32 fftcFreeCounter = 0;
+UInt32 fftcCppiMallocCounter = 0;
+UInt32 fftcCppiFreeCounter = 0;
+UInt32 fftcQmssMallocCounter = 0;
+UInt32 fftcQmssFreeCounter = 0;
+
+UInt32 coreKey [NUM_CORES];
+
+#undef FFTC_TEST_DEBUG
+
+/**********************************************************************
+ *********************** FFTC OSAL Functions **************************
+ **********************************************************************/
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcLocal2Global
+ *
+ * @b brief
+ * @n Utility function which converts a core local address to a global
+ * address.
+ *
+ * @param[in] addr
+ * Local address to be converted
+ *
+ * @return
+ * Global Address
+ * =============================================================================
+ */
+static UInt32 Osal_fftcLocal2Global (UInt32 addr)
+{
+ UInt32 corenum;
+
+ /* Get the core number. */
+ corenum = CSL_chipReadReg(CSL_CHIP_DNUM);
+
+ /* Compute the global address. */
+ return (addr + (0x10000000 + (corenum * 0x01000000)));
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcGlobal2Local
+ *
+ * @b brief
+ * @n Utility function which converts a global to core local address.
+ *
+ * @param[in] gaddr
+ * Global address to be converted
+ *
+ * @return
+ * Local Address
+ * =============================================================================
+ */
+static UInt32 Osal_fftcGlobal2Local (UInt32 gaddr)
+{
+ UInt32 corenum;
+
+ /* Get the core number. */
+ corenum = CSL_chipReadReg(CSL_CHIP_DNUM);
+
+ /* Compute the global address. */
+ return (gaddr & ~((1 << 28) | (corenum << 24)));
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcMalloc
+ *
+ * @b brief
+ * @n This API allocates a memory block of a given
+ * size specified by input parameter 'num_bytes'.
+ *
+ * @param[in] num_bytes
+ * Number of bytes to be allocated.
+ *
+ * @param[in] bGlobalAddress
+ * Indicates whether the address returned by this API should be
+ * a global address or a core local address. Global addresses are
+ * required when allocating CPPI descriptors and buffers.
+ *
+ * @return
+ * Allocated block address
+ * =============================================================================
+ */
+Ptr Osal_fftcMalloc (UInt32 num_bytes, Bool bGlobalAddress)
+{
+ Error_Block errorBlock;
+ Ptr destPtr;
+
+ /* Increment the allocation counter. */
+ fftcMallocCounter++;
+
+ /* Allocate memory from the heap */
+ if (destPtr = Memory_alloc(NULL, num_bytes, 0, &errorBlock))
+ {
+ /* Convert the core local address obtained from
+ * Memory_alloc API to a Global Address. The
+ * CPPI/QMSS libraries cannot handle buffers and
+ * descriptors that are core local addresses.
+ */
+ if (bGlobalAddress)
+ return ((Ptr) Osal_fftcLocal2Global ((UInt32) destPtr));
+ else
+ return ((Ptr) destPtr);
+ }
+ else
+ return destPtr;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcFree
+ *
+ * @b brief
+ * @n This API frees and restores a given memory location
+ * pointer 'dataPtr' of size 'num_bytes' to its
+ * original heap location.
+ *
+ * @param[in] dataPtr
+ * Pointer to the memory block to be cleaned up.
+ *
+ * @param[in] num_bytes
+ * Size of the memory block to be cleaned up.
+ *
+ * @param[in] bGlobalAddress
+ * Indicates that the address passed here to this function is
+ * a Global address.
+ *
+ * @return
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_fftcFree (Ptr dataPtr, UInt32 num_bytes, Bool bGlobalAddress)
+{
+ /* Increment the free counter. */
+ fftcFreeCounter++;
+
+ /* Free up the memory */
+ if (dataPtr)
+ {
+ /* Convert the global address to local address since
+ * thats what the heap understands.
+ */
+ if (bGlobalAddress)
+ Memory_free(NULL, (Ptr) Osal_fftcGlobal2Local ((UInt32) dataPtr), num_bytes);
+ else
+ Memory_free(NULL, (Ptr) dataPtr, num_bytes);
+ }
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcMultiCoreCsEnter
+ *
+ * @b brief
+ * @n This API ensures multi-core and multi-threaded
+ * synchronization to the caller.
+ *
+ * This is a BLOCKING API.
+ *
+ * This API ensures multi-core synchronization between
+ * multiple processes trying to access FFTC shared
+ * library at the same time.
+ *
+ * @param[in] None
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_fftcMultiCoreCsEnter (Void)
+{
+ /* Get the hardware semaphore.
+ *
+ * Acquire Multi core synchronization lock
+ */
+ while ((CSL_semAcquireDirect (FFTC_HW_SEM)) == 0);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcMultiCoreCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_fftcFftcCsEnter ()
+ * API. It resets the multi-core and multi-threaded lock,
+ * enabling another process/core to grab it.
+ *
+ * @param[in] None
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_fftcMultiCoreCsExit (Void)
+{
+ /* Release the hardware semaphore
+ *
+ * Release multi-core lock.
+ */
+ CSL_semReleaseSemaphore (FFTC_HW_SEM);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcInterruptCsEnter
+ *
+ * @b brief
+ * @n This API ensures protection against interrupts to the caller. It prevents
+ * the caller from switching to interrupt context from the application
+ * thread/process context.
+ *
+ * @param[in] None
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_fftcInterruptCsEnter ()
+{
+ /* Disable all interrupts.
+ *
+ * Acquire interrupt lock to protect from any context switches
+ * from application thread/process context.
+ */
+ coreKey [CSL_chipReadDNUM ()] = Hwi_disable();
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcInterruptCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_fftcInterruptCsEnter ()
+ * API. It restores the saved interrupt context and enables back the
+ * interrupts.
+ *
+ * @param[in] None
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_fftcInterruptCsExit ()
+{
+ /* Enable all interrupts.
+ *
+ * Release interrupt lock.
+ */
+ Hwi_restore(coreKey [CSL_chipReadDNUM ()]);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcLog
+ *
+ * @b brief
+ * @n
+ * The function is the FFTC OSAL Logging API which logs
+ * the messages on the console.
+ *
+ * @param[in] fmt
+ * Formatted String.
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_fftcLog ( String fmt, ... )
+{
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcCreateSem
+ *
+ * @b brief
+ * @n This API creates a software semaphore.
+ *
+ * @param[in] Void
+ *
+ * @return
+ * @n Void* - Semaphore handle.
+ *
+ * =============================================================================
+ */
+Void* Osal_fftcCreateSem (Void)
+{
+ return ((Void *) Semaphore_create (0, NULL, NULL));
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcDeleteSem
+ *
+ * @b brief
+ * @n This API deletes a semaphore created earlier using
+ * @a Osal_fftcCreateSem () API.
+ *
+ * @param[in]
+ * hSem - Semaphore handle obtained using @a Osal_fftcCreateSem ()
+ * API.
+ *
+ * @return
+ * @n Void
+ * =============================================================================
+ */
+Void Osal_fftcDeleteSem (Void* hSem)
+{
+ Semaphore_delete (hSem);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcPendSem
+ *
+ * @b brief
+ * @n This API acquires a software semaphore created earlier using
+ * @a Osal_fftcCreateSem () API.
+ *
+ * @param[in]
+ * hSem - Semaphore handle obtained using @a Osal_fftcCreateSem ()
+ * API.
+ *
+ * @return
+ * @n Void
+ * =============================================================================
+ */
+Void Osal_fftcPendSem (Void* hSem)
+{
+ Semaphore_pend (hSem, BIOS_WAIT_FOREVER);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcPostSem
+ *
+ * @b brief
+ * @n This API releases a semaphore acquired earlier using @a
+ * Osal_fftcPendSem () API.
+ *
+ * @param[in]
+ * hSem - Semaphore handle obtained using @a Osal_fftcCreateSem ()
+ * API.
+ *
+ * @return
+ * @n Void
+ * =============================================================================
+ */
+Void Osal_fftcPostSem (Void* hSem)
+{
+ Semaphore_post (hSem);
+
+ return;
+}
+
+/* ============================================================================
+ * @n@b Osal_fftcBeginMemAccess
+ *
+ * @b brief
+ * @n This function invalidates the cached copy of the memory block being
+ * accessed, so as to ensure that any reads to it result in valid data
+ * fetches from the actual physical memory.
+ *
+ * @param[in] blockPtr
+ * Address of the block which is to be read
+ *
+ * @param[in] size
+ * Size of the block to be read
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_fftcBeginMemAccess (Void *blockPtr, UInt32 size)
+{
+ /* Recommended sequence for cache operations is:
+ * 1) Disable all interrupts
+ * 2) Perform the cache block operation
+ * 3) Wait until the cache operation is done either by polling
+ * the corresponding WC register or using _mfence ()
+ * instruction.
+ * 4) Enable interrupts back.
+ */
+ /* Disable all interrupts */
+ Osal_fftcInterruptCsEnter ();
+
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled
+ */
+ CACHE_invL1d (blockPtr, size, CACHE_FENCE_WAIT);
+
+ /* Invalidate the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+ /* Enable back interrupts */
+ Osal_fftcInterruptCsExit ();
+
+ return;
+}
+
+/* ============================================================================
+ * @n@b Osal_fftcEndMemAccess
+ *
+ * @b brief
+ * @n This function issues a writeback operation to ensure that the contents
+ * of cached copy of the memory block are updated in the actual physical
+ * memory too.
+ *
+ * @param[in] blockPtr
+ * Address of the block which is to be read
+ *
+ * @param[in] size
+ * Size of the block to be read
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_fftcEndMemAccess (Void *blockPtr, UInt32 size)
+{
+ /* Recommended sequence for cache operations is:
+ * 1) Disable all interrupts
+ * 2) Perform the cache block operation
+ * 3) Wait until the cache operation is done either by polling
+ * the corresponding WC register or using _mfence ()
+ * instruction.
+ * 4) Enable interrupts back.
+ */
+ /* Disable all interrupts */
+ Osal_fftcInterruptCsEnter ();
+
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled
+ */
+ CACHE_wbL1d (blockPtr, size, CACHE_FENCE_WAIT);
+
+ /* Enable back interrupts */
+ Osal_fftcInterruptCsExit ();
+
+ return;
+}
+
+/* ============================================================================
+ * @n@b Osal_fftcBeginDataBufMemAccess
+ *
+ * @b brief
+ * @n This function invalidates the cached copy of the data buffer memory block
+ * being accessed, so as to ensure that any reads to it result in valid data
+ * fetches from the actual physical memory.
+ *
+ * @param[in] dataBufPtr
+ * Address of the data buffer block which is to be read
+ *
+ * @param[in] size
+ * Size of the block to be read
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_fftcBeginDataBufMemAccess (Void *dataBufPtr, UInt32 size)
+{
+ /* The example program allocates data buffers by default from LL2 and
+ * L2 caches are not enabled by default. Hence, no cache synchronization is needed here. */
+ return;
+}
+
+/* ============================================================================
+ * @n@b Osal_fftcEndDataBufMemAccess
+ *
+ * @b brief
+ * @n This function issues a writeback operation to ensure that the contents
+ * of cached copy of the data buffer memory block are updated in the actual
+ * physical memory too.
+ *
+ * @param[in] dataBufPtr
+ * Address of the data buffer block which is to be read
+ *
+ * @param[in] size
+ * Size of the block to be read
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_fftcEndDataBufMemAccess (Void *dataBufPtr, UInt32 size)
+{
+ /* The example program allocates data buffers by default from LL2 and
+ * L2 caches are not enabled by default. Hence, no cache synchronization is needed here. */
+ return;
+}
+
+/* ============================================================================
+ * @n@b Osal_fftcBeginDescMemAccess
+ *
+ * @b brief
+ * @n This function invalidates the cached copy of the descriptor
+ * being accessed, so as to ensure that any reads to it result in valid data
+ * fetches from the actual physical memory.
+ *
+ * @param[in] hRx
+ * Rx object handle to identify the size of descriptor correctly if descriptors
+ * are application managed for this Rx object.
+ *
+ * @param[in] descPtr
+ * Descriptor address which is to be read
+ *
+ * @param[in] size
+ * Size of the descriptor to be read
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_fftcBeginDescMemAccess (Void* hRx, Void *descPtr, UInt32 size)
+{
+ /* Descriptors in the example program are allocated by default from LL2 and the
+ * L2 cache is disabled by default. Hence, no cache synchronization is needed
+ * here. This hook needs a valid implementation if descriptors are placed in
+ * cacheable memory region. */
+ return;
+}
+
+/* ============================================================================
+ * @n@b Osal_fftcEndDescMemAccess
+ *
+ * @b brief
+ * @n This function issues a writeback operation to ensure that the contents
+ * of cached copy of the descriptor are updated in the actual physical memory
+ * too.
+ *
+ * @param[in] descPtr
+ * Descriptor address thats been updated
+ *
+ * @param[in] size
+ * Size of the descriptor to be written back
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_fftcEndDescMemAccess (Void *descPtr, UInt32 size)
+{
+ /* Descriptors in the example program are allocated by default from LL2 and the
+ * L2 cache is disabled by default. Hence, no cache synchronization is needed
+ * here. This hook needs a valid implementation if descriptors are placed in
+ * cacheable memory region. */
+ return;
+}
+
+/**********************************************************************
+ *********************** CPPI OSAL Functions **************************
+ **********************************************************************/
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiCsEnter
+ *
+ * @b brief
+ * @n This API ensures multi-core and multi-threaded
+ * synchronization to the caller.
+ *
+ * This is a BLOCKING API.
+ *
+ * This API ensures multi-core synchronization between
+ * multiple processes trying to access CPPI shared
+ * library at the same time.
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return
+ * @n Handle used to lock critical section
+ * =============================================================================
+ */
+Ptr Osal_cppiCsEnter (Void)
+{
+ /* Get the hardware semaphore.
+ *
+ * Acquire Multi core CPPI synchronization lock
+ */
+ while ((CSL_semAcquireDirect (CPPI_HW_SEM)) == 0);
+
+ /* Disable all interrupts and OS scheduler.
+ *
+ * Acquire Multi threaded / process synchronization lock.
+ */
+ coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)] = Hwi_disable();
+
+ return NULL;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_cppiCsEnter ()
+ * API. It resets the multi-core and multi-threaded lock,
+ * enabling another process/core to grab CPPI access.
+ *
+ * @param[in] CsHandle
+ * Handle for unlocking critical section.
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_cppiCsExit (Ptr CsHandle)
+{
+ /* Enable all interrupts and enables the OS scheduler back on.
+ *
+ * Release multi-threaded / multi-process lock on this core.
+ */
+ Hwi_restore(coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)]);
+
+ /* Release the hardware semaphore
+ *
+ * Release multi-core lock.
+ */
+ CSL_semReleaseSemaphore (CPPI_HW_SEM);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiMalloc
+ *
+ * @b brief
+ * @n This API allocates a memory block of a given
+ * size specified by input parameter 'num_bytes'.
+ *
+ * This API should allocate memory from shared memory if the test applications
+ * are to be run on multiple cores.
+ *
+ * @param[in] num_bytes
+ * Number of bytes to be allocated.
+ *
+ * @return
+ * Allocated block address
+ * =============================================================================
+ */
+Ptr Osal_cppiMalloc (UInt32 num_bytes)
+{
+ Error_Block errorBlock;
+
+ /* Increment the allocation counter. */
+ fftcCppiMallocCounter++;
+
+ /* Allocate memory. */
+ return Memory_alloc((xdc_runtime_IHeap_Handle) SharedRegion_getHeap(0), num_bytes, 0, &errorBlock);
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiFree
+ *
+ * @b brief
+ * @n This API frees and restores a given memory location
+ * pointer 'dataPtr' of size 'num_bytes' to its
+ * original heap location. Frees up memory allocated using
+ * @a Osal_cppiMalloc ()
+ *
+ * @param[in] dataPtr
+ * Pointer to the memory block to be cleaned up.
+ *
+ * @param[in] num_bytes
+ * Size of the memory block to be cleaned up.
+ *
+ * @return
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_cppiFree (Ptr dataPtr, UInt32 num_bytes)
+{
+ /* Increment the free counter. */
+ fftcCppiFreeCounter++;
+
+ /* Free up the memory */
+ if (dataPtr)
+ {
+ /* Convert the global address to local address since
+ * thats what the heap understands.
+ */
+ Memory_free ((xdc_runtime_IHeap_Handle) SharedRegion_getHeap(0), dataPtr, num_bytes);
+ }
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiBeginMemAccess
+ *
+ * @b brief
+ * @n The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ *
+ * @param[in] ptr
+ * Address of memory block
+ *
+ * @param[in] size
+ * Size of memory block
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+void Osal_cppiBeginMemAccess (void *ptr, uint32_t size)
+{
+ /* Recommended sequence for cache operations is:
+ * 1) Disable all interrupts
+ * 2) Perform the cache block operation
+ * 3) Wait until the cache operation is done either by polling
+ * the corresponding WC register or using _mfence ()
+ * instruction.
+ * 4) Enable interrupts back.
+ */
+ /* Disable all interrupts */
+ Osal_fftcInterruptCsEnter ();
+
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled
+ */
+ CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
+
+ /* Invalidate the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+ /* Enable back interrupts */
+ Osal_fftcInterruptCsExit ();
+
+ return;
+}
+
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiEndMemAccess
+ *
+ * @b brief
+ * @n The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory.
+ *
+ * @param[in] ptr
+ * Address of memory block
+ *
+ * @param[in] size
+ * Size of memory block
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+void Osal_cppiEndMemAccess (void *ptr, uint32_t size)
+{
+ /* Recommended sequence for cache operations is:
+ * 1) Disable all interrupts
+ * 2) Perform the cache block operation
+ * 3) Wait until the cache operation is done either by polling
+ * the corresponding WC register or using _mfence ()
+ * instruction.
+ * 4) Enable interrupts back.
+ */
+ /* Disable all interrupts */
+ Osal_fftcInterruptCsEnter ();
+
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled
+ */
+ CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+
+ /* Enable back interrupts */
+ Osal_fftcInterruptCsExit ();
+
+ return;
+}
+
+/**********************************************************************
+ *********************** QMSS OSAL Functions **************************
+ **********************************************************************/
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssCsEnter
+ *
+ * @b brief
+ * @n This API ensures multi-core and multi-threaded
+ * synchronization to the caller.
+ *
+ * This is a BLOCKING API.
+ *
+ * This API ensures multi-core synchronization between
+ * multiple processes trying to access QMSS shared
+ * library at the same time.
+ *
+ * @param[in] None
+ *
+ * @return
+ * Handle used to lock critical section
+ * =============================================================================
+ */
+Ptr Osal_qmssCsEnter (Void)
+{
+ /* Get the hardware semaphore.
+ *
+ * Acquire Multi core QMSS synchronization lock
+ */
+ while ((CSL_semAcquireDirect (QMSS_HW_SEM)) == 0);
+
+ /* Disable all interrupts and OS scheduler.
+ *
+ * Acquire Multi threaded / process synchronization lock.
+ */
+ coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)] = Hwi_disable();
+
+ return NULL;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_fftcQmssCsEnter ()
+ * API. It resets the multi-core and multi-threaded lock,
+ * enabling another process/core to grab QMSS access.
+ *
+ * @param[in] CsHandle
+ * Handle for unlocking critical section.
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_qmssCsExit (Ptr CsHandle)
+{
+ /* Enable all interrupts and enables the OS scheduler back on.
+ *
+ * Release multi-threaded / multi-process lock on this core.
+ */
+ Hwi_restore(coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)]);
+
+ /* Release the hardware semaphore
+ *
+ * Release multi-core lock.
+ */
+ CSL_semReleaseSemaphore (QMSS_HW_SEM);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssMtCsEnter
+ *
+ * @b brief
+ * @n This API ensures ONLY multi-threaded
+ * synchronization to the QMSS user.
+ *
+ * This is a BLOCKING API.
+ *
+ * @param[in] None
+ *
+ * @return
+ * Handle used to lock critical section
+ * =============================================================================
+ */
+Ptr Osal_qmssMtCsEnter (Void)
+{
+ /* Disable all interrupts and OS scheduler.
+ *
+ * Acquire Multi threaded / process synchronization lock.
+ */
+ //coreKey [CSL_chipReadReg (CSL_CHIP_DNUM)] = Hwi_disable();
+
+ return NULL;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssMtCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_fftcQmssMtCsEnter ()
+ * API. It resets the multi-threaded lock, enabling another process
+ * on the current core to grab it.
+ *
+ * @param[in] CsHandle
+ * Handle for unlocking critical section.
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_qmssMtCsExit (Ptr CsHandle)
+{
+ /* Enable all interrupts and enables the OS scheduler back on.
+ *
+ * Release multi-threaded / multi-process lock on this core.
+ */
+ //Hwi_restore(key);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssMalloc
+ *
+ * @b brief
+ * @n This API allocates a memory block of a given
+ * size specified by input parameter 'num_bytes'.
+ *
+ * @param[in] num_bytes
+ * Number of bytes to be allocated.
+ *
+ * @return
+ * Allocated block address
+ * =============================================================================
+ */
+Ptr Osal_qmssMalloc (UInt32 num_bytes)
+{
+ Error_Block errorBlock;
+
+ /* Increment the allocation counter. */
+ fftcQmssMallocCounter++;
+
+ /* Allocate memory. */
+ return Memory_alloc(NULL, num_bytes, 0, &errorBlock);
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssFree
+ *
+ * @b brief
+ * @n This API frees and restores a given memory location
+ * pointer 'dataPtr' of size 'num_bytes' to its
+ * original heap location. Frees up memory allocated using
+ * @a Osal_qmssMalloc ()
+ *
+ * @param[in] dataPtr
+ * Pointer to the memory block to be cleaned up.
+ *
+ * @param[in] num_bytes
+ * Size of the memory block to be cleaned up.
+ *
+ * @return
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_qmssFree (Ptr dataPtr, UInt32 num_bytes)
+{
+ /* Increment the free counter. */
+ fftcQmssFreeCounter++;
+
+ /* Free up the memory */
+ if (dataPtr)
+ {
+ /* Convert the global address to local address since
+ * thats what the heap understands.
+ */
+ Memory_free(NULL, dataPtr, num_bytes);
+ }
+}
+
+/* ============================================================================
+ * @n@b Osal_qmssBeginMemAccess
+ *
+ * @b brief
+ * @n The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ *
+ * @param[in] ptr
+ * Address of memory block
+ *
+ * @param[in] size
+ * Size of memory block
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+void Osal_qmssBeginMemAccess (void *ptr, uint32_t size)
+{
+ /* Recommended sequence for cache operations is:
+ * 1) Disable all interrupts
+ * 2) Perform the cache block operation
+ * 3) Wait until the cache operation is done either by polling
+ * the corresponding WC register or using _mfence ()
+ * instruction.
+ * 4) Enable interrupts back.
+ */
+ /* Disable all interrupts */
+ Osal_fftcInterruptCsEnter ();
+
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled
+ */
+ CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
+
+ /* Invalidate the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+ /* Enable back interrupts */
+ Osal_fftcInterruptCsExit ();
+
+ return;
+}
+
+/* ============================================================================
+ * @n@b Osal_qmssEndMemAccess
+ *
+ * @b brief
+ * @n The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory..
+ *
+ * @param[in] ptr
+ * Address of memory block
+ *
+ * @param[in] size
+ * Size of memory block
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+void Osal_qmssEndMemAccess (void *ptr, uint32_t size)
+{
+ /* Recommended sequence for cache operations is:
+ * 1) Disable all interrupts
+ * 2) Perform the cache block operation
+ * 3) Wait until the cache operation is done either by polling
+ * the corresponding WC register or using _mfence ()
+ * instruction.
+ * 4) Enable interrupts back.
+ */
+ /* Disable all interrupts */
+ Osal_fftcInterruptCsEnter ();
+
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled
+ */
+ CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+
+ /* Enable back interrupts */
+ Osal_fftcInterruptCsExit ();
+
+ return;
+}
index 00e3f70f96aa92d6faa581c5ba85b28bd283f927..c0bca9ae94e78238498065928429d1d1141cecd2 100755 (executable)
fftcGlobalCfg.bDisableFFT = 0;\r
\r
/* Initialize FFTC driver for instance number specified. */\r
- fftcDevCfg.cpdmaNum = Cppi_CpDma_FFTC_A_CPDMA;\r
+ fftcDevCfg.cpdmaNum = Cppi_CpDma_FFTC_0_CPDMA;\r
fftcDevCfg.baseQueueNum = QMSS_FFTC_A_QUEUE_BASE; \r
fftcDevCfg.cfgRegs = (Void *) (CSL_FFTC_0_CFG_REGS);\r
retVal = Fftc_init (fftcInstNum, &fftcGlobalCfg, &fftcDevCfg);\r
diff --git a/package.xdc b/package.xdc
index 4cc967060ba891066a338c98cd014f0711944193..e3b75e471772d7b8099ee807d281bfe9bee88e72 100755 (executable)
--- a/package.xdc
+++ b/package.xdc
* Copyright (C) 2012, Texas Instruments, Inc.\r
*****************************************************************************/\r
\r
-package ti.drv.fftc[2, 00, 00, 02] {\r
+package ti.drv.fftc[2, 00, 00, 03] {\r
module Settings;\r
}\r
\r
diff --git a/setupenv.bat b/setupenv.bat
index 9c2e71ef82a1bb40917c90d6de3c8b3117bf5db9..79739458dc9f7a745f773748a59f0cdb6a448546 100755 (executable)
--- a/setupenv.bat
+++ b/setupenv.bat
@REM * DESCRIPTION: \r
@REM * Configures and sets up the Build Environment\r
@REM *\r
-@REM * Copyright (C) 2009, Texas Instruments, Inc.\r
+@REM * Copyright (C) 2012, Texas Instruments, Inc.\r
@REM *****************************************************************************\r
\r
@echo ------------------------------------------------\r
@echo Configuring FFTC Driver Build Environment\r
@echo off\r
\r
-REM set the PDK install path\r
-set PDK_INSTALL_PATH=C:\ti\csl_lld_keystone2_1_0_0_3\packages\r
-\r
-REM Set the Part number for which the driver needs to be built\r
+IF DEFINED PARTNO GOTO partno_defined\r
+@REM Configure the Part Number\r
set PARTNO=keystone2\r
+:partno_Defined\r
+\r
+IF DEFINED PDK_INSTALL_PATH GOTO pdk_defined\r
+set PDK_INSTALL_PATH=C:\ti\pdk_keystone2_1_00_00_04\packages\r
+:pdk_defined\r
+\r
\r
-REM This is the base location for the various tools. \r
-set XDCCGROOT=c:/ti/ccsv5/tools/compiler/c6000\r
-set C6X_GEN_INSTALL_PATH=%XDCCGROOT:/=\%\r
+@REM This is the base location for the various tools. \r
+set XDCCGROOT=T:/c6xx/cgen7_3_02/c6000/cgtools\r
+set C6X_GEN_INSTALL_PATH=T:\c6xx\cgen7_3_02\c6000\cgtools\r
\r
+REM *******************************************************************************\r
+REM *************************** XDC PATH Configuration ****************************\r
+REM *******************************************************************************\r
REM FFTC Driver depends upon the following packages:-\r
REM - CSL Package for the FFTC CSL Register Layer\r
REM - CPPI & QMSS LLD\r
REM These packages should be installed before trying to build the driver else \r
REM compilations will fail.\r
+REM PDK Package: CSL, CPPI and QMSS are a part of the PDK package.\r
\r
@REM Specify the XDC Tool Path\r
-set XDC_INSTALL_PATH=C:/ti/xdctools_3_23_03_53\r
+set XDC_INSTALL_PATH=C:/ti/xdctools_3_23_04_60\r
set XDCPATH=../../..;%XDC_INSTALL_PATH%/packages\r
\r
@REM Configure the XDCPATH\r
set XDCPATH=%XDCPATH%;%PDK_INSTALL_PATH%;%C6X_GEN_INSTALL_PATH%/include\r
\r
-REM Eclipse Help Plugin (Not required by customers)\r
+@REM Eclipse Help Plugin (Not required by customers)\r
set XDC_ECLIPSE_PLUGIN_INSTALL_PATH=T:/gen/xdc/xdc_eclipse_plugin_gen/20091203\r
set XDC_FILTER_INSTALL_PATH=T:/gen/xdc/xdcFilter/20100428\r
set XDCPATH=%XDCPATH%;%XDC_ECLIPSE_PLUGIN_INSTALL_PATH%\r
REM Set to ON for running static analysis when needed.\r
set STATIC_ANALYZE=OFF\r
\r
-REM Set the Title Window appropiately.\r
+@REM Set the Title Window appropriately.\r
Title FFTC Driver Build Environment\r
\r
@echo FFTC Driver Build Environment Configured \r
diff --git a/src/Module.xs b/src/Module.xs
index aec7824a7a917a231c97201f1255101c68166685..f974c39706fae1fbfbe1c5e09ed1e2535ffc4b84 100755 (executable)
--- a/src/Module.xs
+++ b/src/Module.xs
"src/fftc_lld.c",\r
];\r
\r
-var devicesCCOpt = [ " -DDEVICE_K2K" ];\r
+var devicesCCOpt = [ " -DDEVICE_K2L" ];\r
\r
/**************************************************************************\r
* FUNCTION NAME : modBuild\r
diff --git a/test/k2h/c66/bios/fftcMCK2HC66BiosTestProject.txt b/test/k2h/c66/bios/fftcMCK2HC66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,24 @@
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_multipleinst.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_poll.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_flowshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_dftlist.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_shift.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_queueshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_multicore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_main.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2h/c66/bios/fftc_linker.cmd"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2h/c66/bios/test_osal.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2h/c66/bios/fftc_test.cfg"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/listlib.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/device/k2h/src/fftc_device_cfg.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2h/src/cppi_device.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2h/src/qmss_device.c"
+-ccs.setCompilerOptions "-DTEST_MULTICORE -mv6600 -g -DDEVICE_K2H --diag_warning=225 -I${FFTC_INSTALL_PATH} -I${PDK_INSTALL_PATH} -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/src -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/k2h/c66/bios"
+-rtsc.enableRtsc
diff --git a/test/k2h/c66/bios/fftcMIK2HC66BiosTestProject.txt b/test/k2h/c66/bios/fftcMIK2HC66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,24 @@
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_multipleinst.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_poll.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_flowshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_dftlist.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_shift.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_queueshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_multicore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_main.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2h/c66/bios/fftc_linker.cmd"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2h/c66/bios/test_osal.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2h/c66/bios/fftc_test.cfg"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/listlib.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/device/k2h/src/fftc_device_cfg.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2h/src/cppi_device.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2h/src/qmss_device.c"
+-ccs.setCompilerOptions "-DTEST_MULTIPLE_INSTANCES -mv6600 -g -DDEVICE_K2H --diag_warning=225 -I${FFTC_INSTALL_PATH} -I${PDK_INSTALL_PATH} -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/src -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/k2h/c66/bios"
+-rtsc.enableRtsc
diff --git a/test/k2h/c66/bios/fftcSimpleK2HC66BiosTestProject.txt b/test/k2h/c66/bios/fftcSimpleK2HC66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,24 @@
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_multipleinst.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_flowshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_dftlist.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_poll.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_shift.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_queueshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_main.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_multicore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2h/c66/bios/test_osal.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2h/c66/bios/fftc_test.cfg"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2h/c66/bios/fftc_linker.cmd"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/listlib.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/device/k2h/src/fftc_device_cfg.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2h/src/cppi_device.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2h/src/qmss_device.c"
+-ccs.setCompilerOptions "-mv6600 -g -DDEVICE_K2H --diag_warning=225 -I${FFTC_INSTALL_PATH} -I${PDK_INSTALL_PATH} -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/src -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/k2h/c66/bios"
+-rtsc.enableRtsc
diff --git a/test/k2k/c66/bios/fftcMCK2KC66BiosTestProject.txt b/test/k2k/c66/bios/fftcMCK2KC66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,24 @@
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_multipleinst.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_poll.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_flowshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_dftlist.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_shift.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_queueshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_multicore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_main.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2k/c66/bios/fftc_linker.cmd"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2k/c66/bios/test_osal.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2k/c66/bios/fftc_test.cfg"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/listlib.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/device/k2k/src/fftc_device_cfg.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2k/src/cppi_device.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2k/src/qmss_device.c"
+-ccs.setCompilerOptions "-DTEST_MULTICORE -mv6600 -g -DDEVICE_K2K --diag_warning=225 -I${FFTC_INSTALL_PATH} -I${PDK_INSTALL_PATH} -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/src -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/k2k/c66/bios"
+-rtsc.enableRtsc
diff --git a/test/k2k/c66/bios/fftcMIK2KC66BiosTestProject.txt b/test/k2k/c66/bios/fftcMIK2KC66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,24 @@
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_multipleinst.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_poll.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_flowshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_dftlist.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_shift.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_queueshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_multicore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_main.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2k/c66/bios/fftc_linker.cmd"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2k/c66/bios/test_osal.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2k/c66/bios/fftc_test.cfg"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/listlib.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/device/k2k/src/fftc_device_cfg.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2k/src/cppi_device.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2k/src/qmss_device.c"
+-ccs.setCompilerOptions "-DTEST_MULTIPLE_INSTANCES -mv6600 -g -DDEVICE_K2K --diag_warning=225 -I${FFTC_INSTALL_PATH} -I${PDK_INSTALL_PATH} -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/src -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/k2k/c66/bios"
+-rtsc.enableRtsc
diff --git a/test/k2k/c66/bios/fftcSimpleK2KC66BiosTestProject.txt b/test/k2k/c66/bios/fftcSimpleK2KC66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,24 @@
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_multipleinst.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_flowshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_dftlist.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_poll.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_shift.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_queueshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_main.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_multicore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2k/c66/bios/test_osal.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2k/c66/bios/fftc_test.cfg"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2k/c66/bios/fftc_linker.cmd"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/listlib.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/device/k2k/src/fftc_device_cfg.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2k/src/cppi_device.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2k/src/qmss_device.c"
+-ccs.setCompilerOptions "-mv6600 -g -DDEVICE_K2K --diag_warning=225 -I${FFTC_INSTALL_PATH} -I${PDK_INSTALL_PATH} -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/src -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/k2k/c66/bios"
+-rtsc.enableRtsc
diff --git a/test/k2l/c66/bios/fftcMCK2LC66BiosTestProject.txt b/test/k2l/c66/bios/fftcMCK2LC66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,24 @@
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_multipleinst.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_poll.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_flowshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_dftlist.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_shift.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_queueshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_multicore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_main.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2l/c66/bios/fftc_linker.cmd"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2l/c66/bios/test_osal.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2l/c66/bios/fftc_test.cfg"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/listlib.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/device/k2l/src/fftc_device_cfg.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2l/src/cppi_device.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2l/src/qmss_device.c"
+-ccs.setCompilerOptions "-DTEST_MULTICORE -mv6600 -g -DDEVICE_K2L --diag_warning=225 -I${FFTC_INSTALL_PATH} -I${PDK_INSTALL_PATH} -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/src -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/k2l/c66/bios"
+-rtsc.enableRtsc
diff --git a/test/k2l/c66/bios/fftcMIK2LC66BiosTestProject.txt b/test/k2l/c66/bios/fftcMIK2LC66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,24 @@
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_multipleinst.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_poll.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_flowshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_dftlist.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_shift.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_queueshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_multicore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_main.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2l/c66/bios/fftc_linker.cmd"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2l/c66/bios/test_osal.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2l/c66/bios/fftc_test.cfg"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/listlib.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/device/k2l/src/fftc_device_cfg.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2l/src/cppi_device.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2l/src/qmss_device.c"
+-ccs.setCompilerOptions "-DTEST_MULTIPLE_INSTANCES -mv6600 -g -DDEVICE_K2L --diag_warning=225 -I${FFTC_INSTALL_PATH} -I${PDK_INSTALL_PATH} -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/src -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/k2l/c66/bios"
+-rtsc.enableRtsc
diff --git a/test/k2l/c66/bios/fftcSimpleK2LC66BiosTestProject.txt b/test/k2l/c66/bios/fftcSimpleK2LC66BiosTestProject.txt
--- /dev/null
@@ -0,0 +1,24 @@
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_mono_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_multipleinst.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_flowshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_dftlist.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_poll.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_shift.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_psinfo.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_singlecore_queueshare.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_main.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/src/test_multicore.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2l/c66/bios/test_osal.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2l/c66/bios/fftc_test.cfg"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/test/k2l/c66/bios/fftc_linker.cmd"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/listlib.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc_lld.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/src/fftc.c"
+-ccs.linkFile "FFTC_INSTALL_PATH/ti/drv/fftc/device/k2l/src/fftc_device_cfg.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/cppi/device/k2l/src/cppi_device.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/qmss/device/k2l/src/qmss_device.c"
+-ccs.setCompilerOptions "-mv6600 -g -DDEVICE_K2L --diag_warning=225 -I${FFTC_INSTALL_PATH} -I${PDK_INSTALL_PATH} -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/src -I${FFTC_INSTALL_PATH}/ti/drv/fftc/test/k2l/c66/bios"
+-rtsc.enableRtsc
diff --git a/test/k2l/c66/bios/fftc_linker.cmd b/test/k2l/c66/bios/fftc_linker.cmd
--- /dev/null
@@ -0,0 +1,7 @@
+SECTIONS
+{
+ .qmss: load >> MSMCSRAM
+ .cppi: load >> MSMCSRAM
+ .fftc: load >> MSMCSRAM
+ .init_array: load >> L2SRAM
+}
diff --git a/test/k2l/c66/bios/fftc_osal.h b/test/k2l/c66/bios/fftc_osal.h
--- /dev/null
@@ -0,0 +1,94 @@
+/**
+ * @file fftc_osal.h
+ *
+ * @brief
+ * OS Adaptation Layer (OSAL) header file for FFTC Test application.
+ * Contains the FFTC OSAL API prototype definitions.
+ *
+ * This is a sample OSAL file ported to XDC/BIOS for demonstration
+ * purposes only. This would need to be ported by System integrator
+ * to a suitable OS and implemented accordingly.
+ *
+ * Uses <b> Approach 2 </b> for OSAL implementation, i.e, the
+ * FFTC library sources would have to be re-compiled with the
+ * new OSAL implementations.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2009, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+#ifndef _FFTC_OSAL_H_
+#define _FFTC_OSAL_H_
+
+/* FFTC Test application types include */
+#include <fftc_types.h>
+
+/* XDC/BIOS include */
+#include <xdc/runtime/System.h>
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Semaphore.h>
+
+extern Void* Osal_biosMalloc (UInt32 num_bytes, Bool bGlobalAddress);
+extern Void Osal_biosFree (Void* dataPtr, UInt32 num_bytes, Bool bGlobalAddress);
+extern Void Osal_biosMultiCoreCsEnter ();
+extern Void Osal_biosMultiCoreCsExit ();
+extern Void Osal_biosInterruptCsEnter ();
+extern Void Osal_biosInterruptCsExit ();
+extern Void Osal_fftcBeginMemAccess (Void* pBlockPtr,UInt32 byteCnt);
+extern Void Osal_fftcEndMemAccess (Void* pBlockPtr,UInt32 byteCnt);
+extern Void Osal_fftcBeginDataBufMemAccess (Void* pDataBufPtr,UInt32 byteCnt);
+extern Void Osal_fftcEndDataBufMemAccess (Void* pDataBufPtr,UInt32 byteCnt);
+extern Void Osal_fftcBeginDescMemAccess (Void* hRx, Void* pDesc,UInt32 byteCnt);
+extern Void Osal_fftcEndDescMemAccess (Void* pDesc,UInt32 byteCnt);
+
+/* Map out all FFTC OSAL APIs to BIOS implementations */
+#define Fftc_osalMalloc Osal_biosMalloc
+#define Fftc_osalFree Osal_biosFree
+#define Fftc_osalMultiCoreCsEnter Osal_biosMultiCoreCsEnter
+#define Fftc_osalMultiCoreCsExit Osal_biosMultiCoreCsExit
+#define Fftc_osalInterruptCsEnter Osal_biosInterruptCsEnter
+#define Fftc_osalInterruptCsExit Osal_biosInterruptCsExit
+#define Fftc_osalLog System_printf
+#define Fftc_osalBeginMemAccess Osal_fftcBeginMemAccess
+#define Fftc_osalEndMemAccess Osal_fftcEndMemAccess
+#define Fftc_osalBeginDataBufMemAccess Osal_fftcBeginDataBufMemAccess
+#define Fftc_osalEndDataBufMemAccess Osal_fftcEndDataBufMemAccess
+#define Fftc_osalBeginDescMemAccess Osal_fftcBeginDescMemAccess
+#define Fftc_osalEndDescMemAccess Osal_fftcEndDescMemAccess
+
+/* Map out all FFTC Semaphore APIs to corresponding BIOS implementations */
+#define Fftc_osalCreateSem() (Void *) Semaphore_create (0, NULL, NULL)
+#define Fftc_osalDeleteSem(X) Semaphore_delete (X)
+#define Fftc_osalPendSem(X) Semaphore_pend (X, BIOS_WAIT_FOREVER)
+#define Fftc_osalPostSem(X) Semaphore_post (X)
+
+#endif /* _FFTC_OSAL_H_ */
diff --git a/test/k2l/c66/bios/fftc_test.cfg b/test/k2l/c66/bios/fftc_test.cfg
--- /dev/null
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2009 by Texas Instruments Incorporated.
+ *
+ * All rights reserved. Property of Texas Instruments Incorporated.
+ * Restricted rights to use, duplicate or disclose this code are
+ * granted through contract.
+ *
+ */
+
+/* THIS FILE WAS GENERATED BY ti.sysbios.genx */
+
+/*
+ * ======== fftc_test.cfg ========
+ *
+ */
+
+/* Load all required BIOS/XDC runtime packages */
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var Log = xdc.useModule('xdc.runtime.Log');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
+var ECM = xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
+
+/* Load the CSL package */
+var Csl = xdc.useModule('ti.csl.Settings');
+
+/* Load the CPPI package */
+var Cppi = xdc.useModule('ti.drv.cppi.Settings');
+
+/* Load the QMSS package */
+var Qmss = xdc.useModule('ti.drv.qmss.Settings');
+
+/* Device specific configuration */
+var devName = "k2l";
+Csl.deviceType = devName;
+
+var System = xdc.useModule('xdc.runtime.System');
+SysStd = xdc.useModule('xdc.runtime.SysStd');
+System.SupportProxy = SysStd;
+
+/* Create a default system heap using ti.bios.HeapMem. */
+var heapMemParams1 = new HeapMem.Params;
+heapMemParams1.size = 8192 * 25;
+heapMemParams1.sectionName = "systemHeap";
+Program.global.heap0 = HeapMem.create(heapMemParams1);
+
+/* This is the default memory heap. */
+Memory.defaultHeapInstance = Program.global.heap0;
+
+Program.sectMap["systemHeap"] = Program.platform.stackMemory;
+
+/****** IPC - Shared Memory Settings ********/
+/* IPC packages */
+var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');
+var Settings = xdc.module('ti.sdo.ipc.family.Settings');
+var ListMP = xdc.useModule('ti.sdo.ipc.ListMP');
+var GateMP = xdc.useModule('ti.sdo.ipc.GateMP');
+var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
+var HeapMemMP = xdc.useModule('ti.sdo.ipc.heaps.HeapMemMP');
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+
+var memmap = Program.cpu.memoryMap;
+
+Startup = xdc.useModule('xdc.runtime.Startup');
+Startup.firstFxns.$add('&myStartupFxn');
+
+/* Configure the shared memory heap for shared memory allocations required by the
+ * CPPI and QMSS Libraries */
+SharedRegion.translate = false;
+
+/* Create a shared memory heap */
+MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2", "CORE3"]);
+
+/* Synchronize all processors (this will be done in Ipc_start) */
+Ipc.procSync = Ipc.ProcSync_ALL;
+
+/* To avoid wasting shared memory for Notify and MessageQ transports */
+for (var i = 0; i < MultiProc.numProcessors; i++) {
+ Ipc.setEntryMeta({
+ remoteProcId: i,
+ setupNotify: false,
+ setupMessageQ: false,
+ });
+}
+
+/* Create a shared memory */
+SharedRegion.setEntryMeta(0,
+ { base: 0x0C010000,
+ len: 0x00100000,
+ ownerProcId: 0,
+ isValid: true,
+ name: "sharemem",
+ });
+
+
+/* Enable BIOS Task Scheduler */
+BIOS.taskEnabled = true;
+
+/*
+ * Enable Event Groups here and registering of ISR for specific GEM INTC is done
+ * using EventCombiner_dispatchPlug() and Hwi_eventMap() APIs
+ */
+
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+/*
+ * @(#) ti.sysbios.genx; 2, 0, 0, 0,275; 4-29-2009 15:45:06; /db/vtree/library/trees/avala/avala-k25x/src/
+ */
+
diff --git a/test/k2l/c66/bios/test_osal.c b/test/k2l/c66/bios/test_osal.c
--- /dev/null
@@ -0,0 +1,1148 @@
+/**
+ * @file test_osal.c
+ *
+ * @brief
+ * This is a sample OS Abstraction Layer (AL) file implemented
+ * using XDC/BIOS APIs.
+ *
+ * System integrator is advised to review these implementations and
+ * modify them to suit it to application requirements.
+ *
+ * This OSAL implementation uses the <b> Approach 2 </b> documented.
+ *
+ * \par
+ * ============================================================================
+ * @n (C) Copyright 2009, Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+/* Standard C-native includes */
+#include <stdlib.h>
+#include <string.h>
+
+/* XDC/BIOS includes */
+#include <xdc/std.h>
+#include <xdc/runtime/IHeap.h>
+#include <xdc/runtime/System.h>
+#include <xdc/runtime/Memory.h>
+#include <xdc/runtime/Error.h>
+
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/hal/Hwi.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/heaps/HeapBuf.h>
+#include <ti/sysbios/heaps/HeapMem.h>
+
+#include <xdc/cfg/global.h>
+
+/* IPC includes */
+#include <ti/ipc/GateMP.h>
+#include <ti/ipc/Ipc.h>
+#include <ti/ipc/ListMP.h>
+#include <ti/ipc/SharedRegion.h>
+
+/* CSL CHIP, SEM Functional layer includes */
+#include <ti/csl/csl_chip.h>
+#include <ti/csl/csl_chipAux.h>
+#include <ti/csl/csl_semAux.h>
+
+/* CSL Cache module includes */
+#include <ti/csl/csl_cache.h>
+#include <ti/csl/csl_cacheAux.h>
+
+/* FFTC Test application OSAL include */
+#include <fftc_osal.h>
+
+/* CSL XMC includes */
+#include <ti/csl/csl_xmc.h>
+#include <ti/csl/csl_xmcAux.h>
+
+/**********************************************************************
+ ****************************** Defines *******************************
+ **********************************************************************/
+
+/* Number of cores on c6498 */
+#define NUM_CORES 4
+
+/* Hardware Semaphore to synchronize access from
+ * multiple FFTC applications across different cores to
+ * the FFTC driver.
+ */
+#define FFTC_HW_SEM 2
+
+/* Hardware Semaphore to synchronize access from
+ * multiple applications (FFTC applications and non-FFTC applications)
+ * across different cores to the QMSS library.
+ */
+#define QMSS_HW_SEM 3
+
+/* Hardware Semaphore to synchronize access from
+ * multiple applications (FFTC applications and non-FFTC applications)
+ * across different cores to the CPPI library.
+ */
+#define CPPI_HW_SEM 4
+
+
+/**********************************************************************
+ ************************** Global Variables **************************
+ **********************************************************************/
+UInt32 fftcMallocCounter = 0;
+UInt32 fftcFreeCounter = 0;
+UInt32 fftcCppiMallocCounter = 0;
+UInt32 fftcCppiFreeCounter = 0;
+UInt32 fftcQmssMallocCounter = 0;
+UInt32 fftcQmssFreeCounter = 0;
+
+UInt32 coreKey [NUM_CORES];
+
+#undef FFTC_TEST_DEBUG
+
+/**********************************************************************
+ *********************** FFTC OSAL Functions **************************
+ **********************************************************************/
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcLocal2Global
+ *
+ * @b brief
+ * @n Utility function which converts a core local address to a global
+ * address.
+ *
+ * @param[in] addr
+ * Local address to be converted
+ *
+ * @return
+ * Global Address
+ * =============================================================================
+ */
+static UInt32 Osal_fftcLocal2Global (UInt32 addr)
+{
+ UInt32 corenum;
+
+ /* Get the core number. */
+ corenum = CSL_chipReadDNUM ();
+
+ /* Compute the global address. */
+ return ((1 << 28) | (corenum << 24) | (addr & 0x00ffffff));
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_fftcGlobal2Local
+ *
+ * @b brief
+ * @n Utility function which converts a global to core local address.
+ *
+ * @param[in] gaddr
+ * Global address to be converted
+ *
+ * @return
+ * Local Address
+ * =============================================================================
+ */
+static UInt32 Osal_fftcGlobal2Local (UInt32 gaddr)
+{
+ UInt32 corenum;
+
+ /* Get the core number. */
+ corenum = CSL_chipReadDNUM ();
+
+ /* Compute the global address. */
+ return (gaddr & ~((1 << 28) | (corenum << 24)));
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_biosMalloc
+ *
+ * @b brief
+ * @n This API allocates a memory block of a given
+ * size specified by input parameter 'num_bytes'.
+ *
+ * @param[in] num_bytes
+ * Number of bytes to be allocated.
+ *
+ * @param[in] bGlobalAddress
+ * Indicates whether the address returned by this API should be
+ * a global address or a core local address. Global addresses are
+ * required when allocating CPPI descriptors and buffers.
+ *
+ * @return
+ * Allocated block address
+ * =============================================================================
+ */
+Void* Osal_biosMalloc (UInt32 num_bytes, Bool bGlobalAddress)
+{
+ Error_Block errorBlock;
+ Void* destPtr;
+
+ /* Increment the allocation counter. */
+ fftcMallocCounter++;
+
+ /* Allocate memory from the heap */
+ if (destPtr = Memory_alloc(NULL, num_bytes, 0, &errorBlock))
+ {
+ /* Convert the core local address obtained from
+ * Memory_alloc API to a Global Address. The
+ * CPPI/QMSS libraries cannot handle buffers and
+ * descriptors that are core local addresses.
+ */
+#ifdef FFTC_TEST_DEBUG
+ Fftc_osalLog ("fftcMalloc Alloc DataP: %p GlobalDataP: %p size: %d \n", destPtr, Osal_fftcLocal2Global ((UInt32) destPtr), num_bytes);
+#endif
+ if (bGlobalAddress)
+ return ((Ptr) Osal_fftcLocal2Global ((UInt32) destPtr));
+ else
+ return ((Ptr) destPtr);
+ }
+ else
+ return destPtr;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_biosFree
+ *
+ * @b brief
+ * @n This API frees and restores a given memory location
+ * pointer 'dataPtr' of size 'num_bytes' to its
+ * original heap location.
+ *
+ * @param[in] dataPtr
+ * Pointer to the memory block to be cleaned up.
+ *
+ * @param[in] num_bytes
+ * Size of the memory block to be cleaned up.
+ *
+ * @param[in] bGlobalAddress
+ * Indicates that the address passed here to this function is
+ * a Global address.
+ *
+ * @return
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_biosFree (Void* dataPtr, UInt32 num_bytes, Bool bGlobalAddress)
+{
+ /* Increment the free counter. */
+ fftcFreeCounter++;
+
+ /* Free up the memory */
+ if (dataPtr)
+ {
+ /* Convert the global address to local address since
+ * thats what the heap understands.
+ */
+#ifdef FFTC_TEST_DEBUG
+ Fftc_osalLog ("FftcFree DataP: %p GDP: %p size: %d\n", dataPtr, (UInt32)Osal_fftcGlobal2Local ((UInt32) dataPtr), num_bytes);
+#endif
+ if (bGlobalAddress)
+ Memory_free(NULL, (Ptr) Osal_fftcGlobal2Local ((UInt32) dataPtr), num_bytes);
+ else
+ Memory_free(NULL, (Ptr) dataPtr, num_bytes);
+ }
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_biosMultiCoreCsEnter
+ *
+ * @b brief
+ * @n This API ensures multi-core synchronization to the caller.
+ *
+ * This is a BLOCKING API.
+ *
+ * This API ensures multi-core synchronization between
+ * multiple processes trying to access FFTC shared
+ * library at the same time.
+ *
+ * @param[in] None
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_biosMultiCoreCsEnter ()
+{
+ /* Get the hardware semaphore.
+ *
+ * Acquire Multi core synchronization lock
+ */
+ while ((CSL_semAcquireDirect (FFTC_HW_SEM)) == 0);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_biosMultiCoreCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_biosMultiCoreCsEnter ()
+ * API. It resets the multi-core lock, enabling another process/core
+ * to grab it.
+ *
+ * @param[in] None
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_biosMultiCoreCsExit ()
+{
+ /* Release the hardware semaphore
+ *
+ * Release multi-core lock.
+ */
+ CSL_semReleaseSemaphore (FFTC_HW_SEM);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_biosInterruptCsEnter
+ *
+ * @b brief
+ * @n This API ensures protection against interrupts to the caller. It prevents
+ * the caller from switching to interrupt context from the application
+ * thread/process context.
+ *
+ * @param[in] None
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_biosInterruptCsEnter ()
+{
+ /* Disable all interrupts.
+ *
+ * Acquire interrupt lock to protect from any context switches
+ * from application thread/process context.
+ */
+ coreKey [CSL_chipReadDNUM ()] = Hwi_disable();
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_biosInterruptCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_biosInterruptCsEnter ()
+ * API. It restores the saved interrupt context and enables back the
+ * interrupts.
+ *
+ * @param[in] None
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_biosInterruptCsExit ()
+{
+ /* Enable all interrupts.
+ *
+ * Release interrupt lock.
+ */
+ Hwi_restore(coreKey [CSL_chipReadDNUM ()]);
+
+ return;
+}
+
+/* ============================================================================
+ * @n@b Osal_fftcBeginMemAccess
+ *
+ * @b brief
+ * @n This function invalidates the cached copy of the memory block being
+ * accessed, so as to ensure that any reads to it result in valid data
+ * fetches from the actual physical memory.
+ *
+ * @param[in] blockPtr
+ * Address of the block which is to be read
+ *
+ * @param[in] size
+ * Size of the block to be read
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_fftcBeginMemAccess (Void *blockPtr, UInt32 size)
+{
+ /* Recommended sequence for cache operations is:
+ * 1) Disable all interrupts
+ * 2) Perform the cache block operation
+ * 3) Wait until the cache operation is done either by polling
+ * the corresponding WC register or using _mfence ()
+ * instruction.
+ * 4) Enable interrupts back.
+ */
+ /* Disable all interrupts */
+ Osal_biosInterruptCsEnter ();
+
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled
+ */
+ CACHE_invL1d (blockPtr, size, CACHE_FENCE_WAIT);
+
+ /* Invalidate the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+ /* Invalidate L2 cache. This should invalidate L1D as well.
+ * Wait until operation is complete.
+ */
+ /* CACHE_invL2 (blockPtr, size, CACHE_FENCE_WAIT); */
+
+ /* Enable back interrupts */
+ Osal_biosInterruptCsExit ();
+
+ return;
+}
+
+/* ============================================================================
+ * @n@b Osal_fftcEndMemAccess
+ *
+ * @b brief
+ * @n This function issues a writeback operation to ensure that the contents
+ * of cached copy of the memory block are updated in the actual physical
+ * memory too.
+ *
+ * @param[in] blockPtr
+ * Address of the block which is to be read
+ *
+ * @param[in] size
+ * Size of the block to be read
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_fftcEndMemAccess (Void *blockPtr, UInt32 size)
+{
+ /* Recommended sequence for cache operations is:
+ * 1) Disable all interrupts
+ * 2) Perform the cache block operation
+ * 3) Wait until the cache operation is done either by polling
+ * the corresponding WC register or using _mfence ()
+ * instruction.
+ * 4) Enable interrupts back.
+ */
+ /* Disable all interrupts */
+ Osal_biosInterruptCsEnter ();
+
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled
+ */
+ CACHE_wbL1d (blockPtr, size, CACHE_FENCE_WAIT);
+
+ /* Writeback L2 cache. This should Writeback L1D as well.
+ * Wait until operation is complete.
+ */
+ /* CACHE_wbL2 (blockPtr, size, CACHE_FENCE_WAIT); */
+
+ /* Enable back interrupts */
+ Osal_biosInterruptCsExit ();
+
+ return;
+}
+
+/* ============================================================================
+ * @n@b Osal_fftcBeginDataBufMemAccess
+ *
+ * @b brief
+ * @n This function invalidates the cached copy of the data buffer memory block
+ * being accessed, so as to ensure that any reads to it result in valid data
+ * fetches from the actual physical memory.
+ *
+ * @param[in] dataBufPtr
+ * Address of the data buffer block which is to be read
+ *
+ * @param[in] size
+ * Size of the block to be read
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_fftcBeginDataBufMemAccess (Void *dataBufPtr, UInt32 size)
+{
+ /* The test program allocates data buffers by default from LL2 and
+ * L2 caches are not enabled by default. Hence, no cache synchronization is needed here. */
+ return;
+}
+
+/* ============================================================================
+ * @n@b Osal_fftcEndDataBufMemAccess
+ *
+ * @b brief
+ * @n This function issues a writeback operation to ensure that the contents
+ * of cached copy of the data buffer memory block are updated in the actual
+ * physical memory too.
+ *
+ * @param[in] dataBufPtr
+ * Address of the data buffer block which is to be read
+ *
+ * @param[in] size
+ * Size of the block to be read
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_fftcEndDataBufMemAccess (Void *dataBufPtr, UInt32 size)
+{
+ /* The test program allocates data buffers by default from LL2 and
+ * L2 caches are not enabled by default. Hence, no cache synchronization is needed. */
+ return;
+}
+
+/* ============================================================================
+ * @n@b Osal_fftcBeginDescMemAccess
+ *
+ * @b brief
+ * @n This function invalidates the cached copy of the descriptor
+ * being accessed, so as to ensure that any reads to it result in valid data
+ * fetches from the actual physical memory.
+ *
+ * @param[in] hRx
+ * Rx object handle to identify the size of descriptor correctly if descriptors
+ * are application managed for this Rx object.
+ *
+ * @param[in] descPtr
+ * Descriptor address which is to be read
+ *
+ * @param[in] size
+ * Size of the descriptor to be read
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_fftcBeginDescMemAccess (Void* hRx, Void *descPtr, UInt32 size)
+{
+ /* Descriptors in the test program are allocated by default from LL2 and the
+ * L2 cache is disabled by default. Hence, no cache synchronization is needed
+ * here. This hook needs a valid implementation if descriptors are placed in
+ * cacheable memory region. */
+ return;
+}
+
+/* ============================================================================
+ * @n@b Osal_fftcEndDescMemAccess
+ *
+ * @b brief
+ * @n This function issues a writeback operation to ensure that the contents
+ * of cached copy of the descriptor are updated in the actual physical memory
+ * too.
+ *
+ * @param[in] descPtr
+ * Descriptor address thats been updated
+ *
+ * @param[in] size
+ * Size of the descriptor to be written back
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_fftcEndDescMemAccess (Void *descPtr, UInt32 size)
+{
+ /* Descriptors in the test program are allocated by default from LL2 and the
+ * L2 cache is disabled by default. Hence, no cache synchronization is needed
+ * here. This hook needs a valid implementation if descriptors are placed in
+ * cacheable memory region. */
+ return;
+}
+
+/**********************************************************************
+ *********************** CPPI OSAL Functions **************************
+ **********************************************************************/
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiCsEnter
+ *
+ * @b brief
+ * @n This API ensures multi-core and multi-threaded
+ * synchronization to the caller.
+ *
+ * This is a BLOCKING API.
+ *
+ * This API ensures multi-core synchronization between
+ * multiple processes trying to access CPPI shared
+ * library at the same time.
+ *
+ * @param[in]
+ * @n None
+ *
+ * @return
+ * @n Handle used to lock critical section
+ * =============================================================================
+ */
+Void* Osal_cppiCsEnter (Void)
+{
+ /* Get the hardware semaphore.
+ *
+ * Acquire Multi core CPPI synchronization lock
+ */
+ while ((CSL_semAcquireDirect (CPPI_HW_SEM)) == 0);
+
+ /* Disable all interrupts and OS scheduler.
+ *
+ * Acquire Multi threaded / process synchronization lock.
+ */
+ coreKey [CSL_chipReadDNUM ()] = Hwi_disable();
+
+ return NULL;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_cppiCsEnter ()
+ * API. It resets the multi-core and multi-threaded lock,
+ * enabling another process/core to grab CPPI access.
+ *
+ * @param[in] CsHandle
+ * Handle for unlocking critical section.
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_cppiCsExit (Void* CsHandle)
+{
+ /* Enable all interrupts and enables the OS scheduler back on.
+ *
+ * Release multi-threaded / multi-process lock on this core.
+ */
+ Hwi_restore(coreKey [CSL_chipReadDNUM ()]);
+
+ /* Release the hardware semaphore
+ *
+ * Release multi-core lock.
+ */
+ CSL_semReleaseSemaphore (CPPI_HW_SEM);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiMalloc
+ *
+ * @b brief
+ * @n This API allocates a memory block of a given
+ * size specified by input parameter 'num_bytes'.
+ *
+ * This API should allocate memory from shared memory if the test applications
+ * are to be run on multiple cores.
+ *
+ * @param[in] num_bytes
+ * Number of bytes to be allocated.
+ *
+ * @return
+ * Allocated block address
+ * =============================================================================
+ */
+Void* Osal_cppiMalloc (UInt32 num_bytes)
+{
+ Error_Block errorBlock;
+ Void* dataPtr;
+
+ /* Increment the allocation counter. */
+ fftcCppiMallocCounter++;
+
+ /* Allocate a buffer from the default HeapMemMp */
+ if (SharedRegion_getHeap(0) != NULL)
+ {
+ dataPtr = Memory_alloc ((xdc_runtime_IHeap_Handle) SharedRegion_getHeap(0), num_bytes, 0, &errorBlock);
+ }
+ else
+ {
+#ifdef FFTC_TEST_DEBUG
+ Fftc_osalLog ("CppiAlloc Failed for size: %d \n", num_bytes);
+#endif
+ return NULL;
+ }
+
+#ifdef FFTC_TEST_DEBUG
+ Fftc_osalLog ("CppiAlloc DataP: %p size: %d \n", dataPtr, num_bytes);
+#endif
+
+ return dataPtr;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiFree
+ *
+ * @b brief
+ * @n This API frees and restores a given memory location
+ * pointer 'dataPtr' of size 'num_bytes' to its
+ * original heap location. Frees up memory allocated using
+ * @a Osal_cppiMalloc ()
+ *
+ * @param[in] dataPtr
+ * Pointer to the memory block to be cleaned up.
+ *
+ * @param[in] num_bytes
+ * Size of the memory block to be cleaned up.
+ *
+ * @return
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_cppiFree (Void* dataPtr, UInt32 num_bytes)
+{
+ /* Increment the free counter. */
+ fftcCppiFreeCounter++;
+
+ /* Free up the memory */
+ if (dataPtr)
+ {
+#ifdef FFTC_TEST_DEBUG
+ Fftc_osalLog ("CppiFree: DataP: %p size: %d\n", dataPtr, num_bytes);
+#endif
+
+ Memory_free ((xdc_runtime_IHeap_Handle) SharedRegion_getHeap(0), dataPtr, num_bytes);
+ }
+}
+
+#if 0
+Void Osal_cppiLog( String fmt, ... )
+{
+}
+#endif
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiBeginMemAccess
+ *
+ * @b brief
+ * @n The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ *
+ * @param[in] ptr
+ * Address of memory block
+ *
+ * @param[in] size
+ * Size of memory block
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+void Osal_cppiBeginMemAccess (void *ptr, uint32_t size)
+{
+ /* Recommended sequence for cache operations is:
+ * 1) Disable all interrupts
+ * 2) Perform the cache block operation
+ * 3) Wait until the cache operation is done either by polling
+ * the corresponding WC register or using _mfence ()
+ * instruction.
+ * 4) Enable interrupts back.
+ */
+ /* Disable all interrupts */
+ Osal_biosInterruptCsEnter ();
+
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled
+ */
+ CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
+
+ /* Invalidate L2 cache. This should invalidate L1D as well.
+ * Wait until operation is complete.
+ */
+ /* CACHE_invL2 (ptr, size, CACHE_FENCE_WAIT); */
+
+ /* Invalidate the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+ /* Enable back interrupts */
+ Osal_biosInterruptCsExit ();
+
+ return;
+}
+
+
+/**
+ * ============================================================================
+ * @n@b Osal_cppiEndMemAccess
+ *
+ * @b brief
+ * @n The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory.
+ *
+ * @param[in] ptr
+ * Address of memory block
+ *
+ * @param[in] size
+ * Size of memory block
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+void Osal_cppiEndMemAccess (void *ptr, uint32_t size)
+{
+ /* Recommended sequence for cache operations is:
+ * 1) Disable all interrupts
+ * 2) Perform the cache block operation
+ * 3) Wait until the cache operation is done either by polling
+ * the corresponding WC register or using _mfence ()
+ * instruction.
+ * 4) Enable interrupts back.
+ */
+ /* Disable all interrupts */
+ Osal_biosInterruptCsEnter ();
+
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled
+ */
+ CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+
+ /* Writeback L2 cache. This should Writeback L1D as well.
+ * Wait until operation is complete.
+ */
+ /* CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT); */
+
+ /* Enable back interrupts */
+ Osal_biosInterruptCsExit ();
+
+ return;
+}
+
+/**********************************************************************
+ *********************** QMSS OSAL Functions **************************
+ **********************************************************************/
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssCsEnter
+ *
+ * @b brief
+ * @n This API ensures multi-core and multi-threaded
+ * synchronization to the caller.
+ *
+ * This is a BLOCKING API.
+ *
+ * This API ensures multi-core synchronization between
+ * multiple processes trying to access QMSS shared
+ * library at the same time.
+ *
+ * @param[in] None
+ *
+ * @return
+ * Handle used to lock critical section
+ * =============================================================================
+ */
+Void* Osal_qmssCsEnter (Void)
+{
+ /* Get the hardware semaphore.
+ *
+ * Acquire Multi core QMSS synchronization lock
+ */
+ while ((CSL_semAcquireDirect (QMSS_HW_SEM)) == 0);
+
+ /* Disable all interrupts and OS scheduler.
+ *
+ * Acquire Multi threaded / process synchronization lock.
+ */
+ coreKey [CSL_chipReadDNUM ()] = Hwi_disable();
+
+ return NULL;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_fftcQmssCsEnter ()
+ * API. It resets the multi-core and multi-threaded lock,
+ * enabling another process/core to grab QMSS access.
+ *
+ * @param[in] CsHandle
+ * Handle for unlocking critical section.
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_qmssCsExit (Void* CsHandle)
+{
+ /* Enable all interrupts and enables the OS scheduler back on.
+ *
+ * Release multi-threaded / multi-process lock on this core.
+ */
+ Hwi_restore(coreKey [CSL_chipReadDNUM ()]);
+
+ /* Release the hardware semaphore
+ *
+ * Release multi-core lock.
+ */
+ CSL_semReleaseSemaphore (QMSS_HW_SEM);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssMtCsEnter
+ *
+ * @b brief
+ * @n This API ensures ONLY multi-threaded
+ * synchronization to the QMSS user.
+ *
+ * This is a BLOCKING API.
+ *
+ * @param[in] None
+ *
+ * @return
+ * Handle used to lock critical section
+ * =============================================================================
+ */
+Void* Osal_qmssMtCsEnter (Void)
+{
+ /* Disable all interrupts and OS scheduler.
+ *
+ * Acquire Multi threaded / process synchronization lock.
+ */
+ //coreKey [CSL_chipReadDNUM ()] = Hwi_disable();
+
+ return NULL;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssMtCsExit
+ *
+ * @b brief
+ * @n This API needs to be called to exit a previously
+ * acquired critical section lock using @a Osal_fftcQmssMtCsEnter ()
+ * API. It resets the multi-threaded lock, enabling another process
+ * on the current core to grab it.
+ *
+ * @param[in] CsHandle
+ * Handle for unlocking critical section.
+ *
+ * @return None
+ * =============================================================================
+ */
+Void Osal_qmssMtCsExit (Void* CsHandle)
+{
+ /* Enable all interrupts and enables the OS scheduler back on.
+ *
+ * Release multi-threaded / multi-process lock on this core.
+ */
+ //Hwi_restore(key);
+
+ return;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssMalloc
+ *
+ * @b brief
+ * @n This API allocates a memory block of a given
+ * size specified by input parameter 'num_bytes'.
+ *
+ * @param[in] num_bytes
+ * Number of bytes to be allocated.
+ *
+ * @return
+ * Allocated block address
+ * =============================================================================
+ */
+Void* Osal_qmssMalloc (UInt32 num_bytes)
+{
+ Error_Block errorBlock;
+ Void* dataPtr;
+
+ /* Increment the allocation counter. */
+ fftcQmssMallocCounter++;
+
+ /* Allocate memory. */
+ dataPtr = Memory_alloc(NULL, num_bytes, 0, &errorBlock);
+
+#ifdef FFTC_TEST_DEBUG
+ Fftc_osalLog ("QmssAlloc DataP: %p size: %d \n", dataPtr, num_bytes);
+#endif
+
+ return dataPtr;
+}
+
+/**
+ * ============================================================================
+ * @n@b Osal_qmssFree
+ *
+ * @b brief
+ * @n This API frees and restores a given memory location
+ * pointer 'dataPtr' of size 'num_bytes' to its
+ * original heap location. Frees up memory allocated using
+ * @a Osal_qmssMalloc ()
+ *
+ * @param[in] dataPtr
+ * Pointer to the memory block to be cleaned up.
+ *
+ * @param[in] num_bytes
+ * Size of the memory block to be cleaned up.
+ *
+ * @return
+ * Not Applicable
+ * =============================================================================
+ */
+Void Osal_qmssFree (Void* dataPtr, UInt32 num_bytes)
+{
+ /* Increment the free counter. */
+ fftcQmssFreeCounter++;
+
+ /* Free up the memory */
+ if (dataPtr)
+ {
+ /* Convert the global address to local address since
+ * thats what the heap understands.
+ */
+#ifdef FFTC_TEST_DEBUG
+ Fftc_osalLog ("QmssFree DataP: %p size: %d\n", dataPtr, num_bytes);
+#endif
+
+ Memory_free(NULL, dataPtr, num_bytes);
+ }
+}
+
+/* ============================================================================
+ * @n@b Osal_qmssBeginMemAccess
+ *
+ * @b brief
+ * @n The function is used to indicate that a block of memory is
+ * about to be accessed. If the memory block is cached then this
+ * indicates that the application would need to ensure that the
+ * cache is updated with the data from the actual memory.
+ *
+ * @param[in] ptr
+ * Address of memory block
+ *
+ * @param[in] size
+ * Size of memory block
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+void Osal_qmssBeginMemAccess (void *ptr, uint32_t size)
+{
+ /* Recommended sequence for cache operations is:
+ * 1) Disable all interrupts
+ * 2) Perform the cache block operation
+ * 3) Wait until the cache operation is done either by polling
+ * the corresponding WC register or using _mfence ()
+ * instruction.
+ * 4) Enable interrupts back.
+ */
+ /* Disable all interrupts */
+ Osal_biosInterruptCsEnter ();
+
+ /* Invalidate L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled
+ */
+ CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
+
+ /* Invalidate L2 cache. This should invalidate L1D as well.
+ * Wait until operation is complete.
+ */
+ /* CACHE_invL2 (ptr, size, CACHE_FENCE_WAIT); */
+
+ /* Invalidate the prefetch buffer also. */
+ CSL_XMC_invalidatePrefetchBuffer();
+
+ /* Enable back interrupts */
+ Osal_biosInterruptCsExit ();
+
+ return;
+}
+
+/* ============================================================================
+ * @n@b Osal_qmssEndMemAccess
+ *
+ * @b brief
+ * @n The function is used to indicate that the block of memory has
+ * finished being accessed. If the memory block is cached then the
+ * application would need to ensure that the contents of the cache
+ * are updated immediately to the actual memory..
+ *
+ * @param[in] ptr
+ * Address of memory block
+ *
+ * @param[in] size
+ * Size of memory block
+
+ * @retval
+ * Not Applicable
+ * =============================================================================
+ */
+void Osal_qmssEndMemAccess (void *ptr, uint32_t size)
+{
+ /* Recommended sequence for cache operations is:
+ * 1) Disable all interrupts
+ * 2) Perform the cache block operation
+ * 3) Wait until the cache operation is done either by polling
+ * the corresponding WC register or using _mfence ()
+ * instruction.
+ * 4) Enable interrupts back.
+ */
+ /* Disable all interrupts */
+ Osal_biosInterruptCsEnter ();
+
+ /* Writeback L1D cache and wait until operation is complete.
+ * Use this approach if L2 cache is not enabled
+ */
+ CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+
+ /* Writeback L2 cache. This should Writeback L1D as well.
+ * Wait until operation is complete.
+ */
+ /* CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT); */
+
+ /* Enable back interrupts */
+ Osal_biosInterruptCsExit ();
+
+ return;
+}
diff --git a/test/src/test_main.c b/test/src/test_main.c
index a3c7e3eee8d1ae6edf6716dac6d3e48b57a5cc12..0b10688ad8c57cb86b2cbd5e4fa8f1a69483f6aa 100755 (executable)
--- a/test/src/test_main.c
+++ b/test/src/test_main.c
\r
/* Initialize FFTC driver for instance number specified. */\r
fftcInstNum = CSL_FFTC_0; \r
- fftcDevCfg.cpdmaNum = Cppi_CpDma_FFTC_A_CPDMA;\r
+ fftcDevCfg.cpdmaNum = Cppi_CpDma_FFTC_0_CPDMA;\r
fftcDevCfg.baseQueueNum = QMSS_FFTC_A_QUEUE_BASE; \r
fftcDevCfg.cfgRegs = (Void *) (CSL_FFTC_0_CFG_REGS);\r
retVal = Fftc_init (fftcInstNum, &fftcGlobalCfg, &fftcDevCfg);\r
\r
/* Initialize FFTC driver for instance number specified. */\r
fftcInstNum = CSL_FFTC_1;\r
- fftcDevCfg.cpdmaNum = Cppi_CpDma_FFTC_B_CPDMA;\r
+ fftcDevCfg.cpdmaNum = Cppi_CpDma_FFTC_1_CPDMA;\r
fftcDevCfg.baseQueueNum = QMSS_FFTC_B_QUEUE_BASE; \r
fftcDevCfg.cfgRegs = (Void *) (CSL_FFTC_1_CFG_REGS);\r
retVal = Fftc_init (fftcInstNum, &fftcGlobalCfg, &fftcDevCfg);\r