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raw | patch | inline | side by side (parent: 2b60bd9)
raw | patch | inline | side by side (parent: 2b60bd9)
| author | Hao Zhang <hzhang@ti.com> | |
| Thu, 19 Sep 2019 15:00:40 +0000 (11:00 -0400) | ||
| committer | Hao Zhang <hzhang@ti.com> | |
| Thu, 19 Sep 2019 15:00:40 +0000 (11:00 -0400) |
Signed-off-by: Hao Zhang <hzhang@ti.com>
| GPIO.h | patch | blob | history | |
| soc/GPIO_soc.h | patch | blob | history | |
| soc/j721e/GPIO_soc.c | patch | blob | history | |
| src/v0/GPIO_v0.c | patch | blob | history | |
| src/v0/GPIO_v0.h | patch | blob | history |
index a32a8dcce45522329cfcb92d077e5f211463540c..e41177d1c125f5879b2422d06efe5344c8097a76 100644 (file)
--- a/GPIO.h
+++ b/GPIO.h
/*!
* @brief Reads the value of a GPIO pin
*/
-typedef uint32_t (*GPIO_ReadFxn) (uint32_t index);
+typedef uint32_t (*GPIO_ReadFxn) (uint32_t idx);
/*!
* @brief Writes the value to a GPIO pin
*/
-typedef void (*GPIO_WriteFxn) (uint32_t index,
+typedef void (*GPIO_WriteFxn) (uint32_t idx,
uint32_t value);
/*!
* @brief Clear a GPIO pin interrupt flag
*/
-typedef void (*GPIO_clearIntFxn) (uint32_t index);
+typedef void (*GPIO_clearIntFxn) (uint32_t idx);
/*!
* @brief Disable a GPIO pin interrupt
*/
-typedef void (*GPIO_disableIntFxn) (uint32_t index);
+typedef void (*GPIO_disableIntFxn) (uint32_t idx);
/*!
* @brief Enable a GPIO pin interrupt
*/
-typedef void (*GPIO_enableIntFxn) (uint32_t index);
+typedef void (*GPIO_enableIntFxn) (uint32_t idx);
/*!
* @brief Bind a callback function to a GPIO pin interrupt
*/
-typedef void (*GPIO_setCallbackFxn) (uint32_t index,
+typedef void (*GPIO_setCallbackFxn) (uint32_t idx,
GPIO_CallbackFxn callback);
/*!
* @brief Configure the gpio pin
*/
-typedef void (*GPIO_setConfigFxn) (uint32_t index,
+typedef void (*GPIO_setConfigFxn) (uint32_t idx,
GPIO_PinConfig pinConfig);
/*!
* @brief Toggles the current state of a GPIO
*
- * @param index GPIO index
+ * @param idx GPIO index
*/
-typedef void (*GPIO_toggleFxn) (uint32_t index);
+typedef void (*GPIO_toggleFxn) (uint32_t idx);
/*!
* @brief The definition of a GPIO function table that contains the
* Note: It is not necessary to call this API within a
* callback assigned to a pin.
*
- * @param index GPIO index
+ * @param idx GPIO index
*/
-extern void GPIO_clearInt(uint32_t index);
+extern void GPIO_clearInt(uint32_t idx);
/*!
* @brief Disable a GPIO pin interrupt
*
* Disables interrupts for the specified GPIO index.
*
- * @param index GPIO index
+ * @param idx GPIO index
*/
-extern void GPIO_disableInt(uint32_t index);
+extern void GPIO_disableInt(uint32_t idx);
/*!
* @brief Enable a GPIO pin interrupt
* Alternatively, the callback function can be statically
* configured in the GPIO_CallbackFxn array provided.
*
- * @param index GPIO index
+ * @param idx GPIO index
*/
-extern void GPIO_enableInt(uint32_t index);
+extern void GPIO_enableInt(uint32_t idx);
/*!
* @brief Initializes the GPIO module
* The value returned will either be zero or one depending on the
* state of the pin.
*
- * @param index GPIO index
+ * @param idx GPIO index
*
* @return 0 or 1, depending on the state of the pin.
*/
-extern uint32_t GPIO_read(uint32_t index);
+extern uint32_t GPIO_read(uint32_t idx);
/*!
* @brief Bind a callback function to a GPIO pin interrupt
* Note: it is not necessary to call GPIO_clearInt() within a callback.
* That operation is performed internally before the callback is invoked.
*
- * @param index GPIO index
+ * @param idx GPIO index
* @param callback address of the callback function
*/
-extern void GPIO_setCallback(uint32_t index, GPIO_CallbackFxn callback);
+extern void GPIO_setCallback(uint32_t idx, GPIO_CallbackFxn callback);
/*!
* @brief Configure the gpio pin
* For input pins with interrupt configurations, a corresponding interrupt
* object will be created as needed.
*
- * @param index GPIO index
+ * @param idx GPIO index
* @param pinConfig device specific pin configuration settings
*/
-extern void GPIO_setConfig(uint32_t index, GPIO_PinConfig pinConfig);
+extern void GPIO_setConfig(uint32_t idx, GPIO_PinConfig pinConfig);
/*!
* @brief Toggles the current state of a GPIO
*
- * @param index GPIO index
+ * @param idx GPIO index
*/
-extern void GPIO_toggle(uint32_t index);
+extern void GPIO_toggle(uint32_t idx);
/*!
* @brief Writes the value to a GPIO pin
*
- * @param index GPIO index
+ * @param idx GPIO index
* @param value must be either 0 or 1
*/
-extern void GPIO_write(uint32_t index, uint32_t value);
+extern void GPIO_write(uint32_t idx, uint32_t value);
#ifdef __cplusplus
}
diff --git a/soc/GPIO_soc.h b/soc/GPIO_soc.h
index bc388c481556511920fe0fd1c821125c2c0a80f4..5c7d679f35bf4ce70152ba182f4b30b49ae48b2c 100644 (file)
--- a/soc/GPIO_soc.h
+++ b/soc/GPIO_soc.h
/* GPIO SoC level API */
#if defined(SOC_K2H) || defined(SOC_K2K) || defined(SOC_K2L) || defined(SOC_K2E) || defined(SOC_K2G) || defined(SOC_C6678) || defined(SOC_C6657) || defined(SOC_OMAPL137) || defined(SOC_OMAPL138) || defined(SOC_AM65XX) || defined(SOC_J721E)
-extern int32_t GPIO_socGetInitCfg(uint32_t index, GPIO_v0_HwAttrs *cfg);
-extern int32_t GPIO_socSetInitCfg(uint32_t index, const GPIO_v0_HwAttrs *cfg);
+extern int32_t GPIO_socGetInitCfg(uint32_t idx, GPIO_v0_HwAttrs *cfg);
+extern int32_t GPIO_socSetInitCfg(uint32_t idx, const GPIO_v0_HwAttrs *cfg);
extern void GPIO_socGetNumPinsPorts(uint32_t *numPins, uint32_t *numPorts);
#endif
diff --git a/soc/j721e/GPIO_soc.c b/soc/j721e/GPIO_soc.c
index 3a71c5197dc702ec41da6b0fb638db6a89ae86ed..76abd10ceb979357c9d27f82df6da30b8978d6cf 100755 (executable)
--- a/soc/j721e/GPIO_soc.c
+++ b/soc/j721e/GPIO_soc.c
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main int router output interrupt number */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
{
#if defined (BUILD_MPU)
/* main domain */
- CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
0, /* GPIO pin interrupt event */
#endif
#if defined (BUILD_MCU)
GPIO_v0_hwAttrsList GPIO_v0_hwAttrs =
{
{
- CSL_GPIO0_BASE,
+ (uint32_t)CSL_GPIO0_BASE,
&GPIO_intCfgs[0][0],
&GPIO_socConfigIntrPath,
},
-
{
- CSL_GPIO1_BASE,
+ (uint32_t)CSL_GPIO1_BASE,
&GPIO_intCfgs[1][0],
&GPIO_socConfigIntrPath,
+ },
+ {
+ (uint32_t)CSL_GPIO2_BASE,
+ &GPIO_intCfgs[2][0],
+ &GPIO_socConfigIntrPath,
+ },
+ {
+ (uint32_t)CSL_GPIO3_BASE,
+ &GPIO_intCfgs[3][0],
+ &GPIO_socConfigIntrPath,
+ },
+ {
+ (uint32_t)CSL_GPIO4_BASE,
+ &GPIO_intCfgs[4][0],
+ &GPIO_socConfigIntrPath,
+ },
+ {
+ (uint32_t)CSL_GPIO5_BASE,
+ &GPIO_intCfgs[5][0],
+ &GPIO_socConfigIntrPath,
+ },
+ {
+ (uint32_t)CSL_GPIO6_BASE,
+ &GPIO_intCfgs[6][0],
+ &GPIO_socConfigIntrPath,
+ },
+ {
+ (uint32_t)CSL_GPIO7_BASE,
+ &GPIO_intCfgs[7][0],
+ &GPIO_socConfigIntrPath,
}
};
/**
* \brief This API gets the SoC level of GPIO intial configuration
*
- * \param index GPIO instance index.
+ * \param idx GPIO instance index.
* \param cfg Pointer to GPIO SOC initial config.
*
* \return 0 success: -1: error
*
*/
-int32_t GPIO_socGetInitCfg(uint32_t index, GPIO_v0_HwAttrs *cfg)
+int32_t GPIO_socGetInitCfg(uint32_t idx, GPIO_v0_HwAttrs *cfg)
{
int32_t ret = 0;
- if (index < GPIO_NUM_PORTS)
+ if (idx < GPIO_NUM_PORTS)
{
- *cfg = GPIO_v0_hwAttrs[index];
+ *cfg = GPIO_v0_hwAttrs[idx];
}
else
{
/**
* \brief This API sets the SoC level of GPIO intial configuration
*
- * \param index GPIO instance index.
+ * \param idx GPIO instance index.
* \param cfg Pointer to GPIO SOC initial config.
*
* \return 0 success: -1: error
*
*/
-int32_t GPIO_socSetInitCfg(uint32_t index, const GPIO_v0_HwAttrs *cfg)
+int32_t GPIO_socSetInitCfg(uint32_t idx, const GPIO_v0_HwAttrs *cfg)
{
int32_t ret = 0;
- if (index < GPIO_NUM_PORTS)
+ if (idx < GPIO_NUM_PORTS)
{
- GPIO_v0_hwAttrs[index] = *cfg;
+ GPIO_v0_hwAttrs[idx] = *cfg;
}
else
{
void MuxIntcP_clearInEvent(int32_t muxNum, int32_t muxInEvent)
{
+ (void)muxNum;
+ (void)muxInEvent;
+
return;
}
MuxIntcP_Status MuxIntcP_create(MuxIntcP_inParams *inParams, MuxIntcP_outParams *outParams)
{
+ inParams = inParams;
+ outParams = outParams;
+
return (MuxIntcP_OK);
}
/* A count kept for each bank usage/ 16 pins share a bank */
-#define GPIO_NUM_BANKS ((GPIO_NUM_PINS_PER_PORT+15)/16)
-int32_t GPIO_PinBankUsageCount[GPIO_NUM_PORTS][GPIO_NUM_BANKS] ={0};
+#define GPIO_NUM_BANKS ((GPIO_NUM_PINS_PER_PORT + 15U) / 16U)
+uint32_t GPIO_PinBankUsageCount[GPIO_NUM_PORTS][GPIO_NUM_BANKS] = {0U, };
/**
* \brief This function sets/clears the soc interrupt path including the interrupt routers (GPIO_RTR,MAIN2MCU_RTR) etc
@@ -637,76 +672,90 @@ int32_t GPIO_socConfigIntrPath(uint32_t portNum, uint32_t pinNum,void *hwAttrs,b
uint16_t src_id,src_index,dst_id,dst_host_irq;
intCfg = cfg->intCfg;
- cfg->baseAddr = CSL_WKUP_GPIO0_BASE; /* For AM65x GP EVM */
+ cfg->baseAddr = (uint32_t)CSL_WKUP_GPIO0_BASE; /* For AM65x GP EVM */
#if defined(BUILD_MCU1_0) || defined(BUILD_MCU1_1) || defined(BUILD_MCU2_0) || defined(BUILD_MCU2_1) || defined(BUILD_MCU3_0) || defined(BUILD_MCU3_1)
CSL_armR5GetCpuID(&r5CpuInfo);
#endif
/* Input parameter validation */
- bankNum = pinNum/16; /* Each GPIO bank has 16 pins */
+ bankNum = pinNum/16U; /* Each GPIO bank has 16 pins */
/* We route bank interrupts to the cpu interrupts */
- if(cfg->baseAddr == CSL_WKUP_GPIO0_BASE) {
- src_id = TISCI_DEV_WKUP_GPIO0;
- src_index = bankNum; /* This is the bus_gpio_bank (0-5) mentioned in DMSC firmware guide for J721E_DEV_WKUP_GPIO0 */
- } else if(cfg->baseAddr == CSL_WKUP_GPIO1_BASE) {
- src_id = TISCI_DEV_GPIO1;
- src_index = bankNum; /* This is the bus_gpio_bank (0-5) mentioned in DMSC firmware guide for J721E_DEV_WKUP_GPIO1 */
- } else if(cfg->baseAddr == CSL_GPIO0_BASE) {
- src_id = TISCI_DEV_GPIO0;
- src_index = bankNum; /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide for J721E_DEV_GPIO0 */
- } else if(cfg->baseAddr == CSL_GPIO2_BASE) {
- src_id = TISCI_DEV_GPIO2;
- src_index = bankNum; /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide for J721E_DEV_GPIO2 */
- } else if(cfg->baseAddr == CSL_GPIO4_BASE) {
- src_id = TISCI_DEV_GPIO4;
- src_index = bankNum; /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide for J721E_DEV_GPIO4 */
- } else if(cfg->baseAddr == CSL_GPIO6_BASE) {
- src_id = TISCI_DEV_GPIO6;
- src_index = bankNum; /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide for J721E_DEV_GPIO6 */
- } else if(cfg->baseAddr == CSL_GPIO1_BASE) {
- src_id = TISCI_DEV_GPIO1;
- src_index = bankNum; /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide for J721E_DEV_GPIO1 */
- } else if(cfg->baseAddr == CSL_GPIO3_BASE) {
- src_id = TISCI_DEV_GPIO3;
- src_index = bankNum; /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide for J721E_DEV_GPIO3 */
- } else if(cfg->baseAddr == CSL_GPIO5_BASE) {
- src_id = TISCI_DEV_GPIO5;
- src_index = bankNum; /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide for J721E_DEV_GPIO5 */
- } else if(cfg->baseAddr == CSL_GPIO7_BASE) {
- src_id = TISCI_DEV_GPIO7;
- src_index = bankNum; /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide for J721E_DEV_GPIO7 */
- }
+ switch (cfg->baseAddr)
+ {
+ case (uint32_t)CSL_WKUP_GPIO0_BASE:
+ src_id = TISCI_DEV_WKUP_GPIO0;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-5) mentioned in DMSC firmware guide for J721E_DEV_WKUP_GPIO0 */
+ break;
+ case (uint32_t)CSL_WKUP_GPIO1_BASE:
+ src_id = TISCI_DEV_WKUP_GPIO1;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-5) mentioned in DMSC firmware guide for J721E_DEV_WKUP_GPIO1 */
+ break;
+ case (uint32_t)CSL_GPIO0_BASE:
+ src_id = TISCI_DEV_GPIO0;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide for J721E_DEV_GPIO0 */
+ break;
+ case (uint32_t)CSL_GPIO2_BASE:
+ src_id = TISCI_DEV_GPIO2;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide for J721E_DEV_GPIO2 */
+ break;
+ case (uint32_t)CSL_GPIO4_BASE:
+ src_id = TISCI_DEV_GPIO4;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide for J721E_DEV_GPIO4 */
+ break;
+ case (uint32_t)CSL_GPIO6_BASE:
+ src_id = TISCI_DEV_GPIO6;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide for J721E_DEV_GPIO6 */
+ break;
+ case (uint32_t)CSL_GPIO1_BASE:
+ src_id = TISCI_DEV_GPIO1;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide for J721E_DEV_GPIO1 */
+ break;
+ case (uint32_t)CSL_GPIO3_BASE:
+ src_id = TISCI_DEV_GPIO3;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide for J721E_DEV_GPIO3 */
+ break;
+ case (uint32_t)CSL_GPIO5_BASE:
+ src_id = TISCI_DEV_GPIO5;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide for J721E_DEV_GPIO5 */
+ break;
+ case (uint32_t)CSL_GPIO7_BASE:
+ src_id = TISCI_DEV_GPIO7;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide for J721E_DEV_GPIO7 */
+ break;
+ default:
+ break;
+ }
/* GPIO uses bank interrupts. So choose the bank interrupts from bus_gpio_bank with valid values from
* the DMSC firmware user guide */
#if defined(BUILD_MCU1_0) || defined(BUILD_MCU1_1)
- if(r5CpuInfo.cpuID == 0) {
+ if(r5CpuInfo.cpuID == 0U) {
dst_id = TISCI_DEV_MCU_R5FSS0_CORE0;
- dst_host_irq = intCfg[pinNum].intNum;
+ dst_host_irq = (uint16_t)intCfg[pinNum].intNum;
} else {
dst_id = TISCI_DEV_MCU_R5FSS0_CORE1;
- dst_host_irq = intCfg[pinNum].intNum;
+ dst_host_irq = (uint16_t)intCfg[pinNum].intNum;
}
#elif defined(BUILD_MCU2_0) || defined(BUILD_MCU2_1)
- if(r5CpuInfo.cpuID == 0) {
+ if(r5CpuInfo.cpuID == 0U) {
dst_id = TISCI_DEV_R5FSS0_CORE0;
- dst_host_irq = intCfg[pinNum].intNum;
+ dst_host_irq = (uint16_t)intCfg[pinNum].intNum;
} else {
dst_id = TISCI_DEV_R5FSS0_CORE1;
- dst_host_irq = intCfg[pinNum].intNum;
+ dst_host_irq = (uint16_t)intCfg[pinNum].intNum;
}
#elif defined(BUILD_MCU3_0) || defined(BUILD_MCU3_1)
- if(r5CpuInfo.cpuID == 0) {
+ if(r5CpuInfo.cpuID == 0U) {
dst_id = TISCI_DEV_R5FSS1_CORE0;
- dst_host_irq = intCfg[pinNum].intNum;
+ dst_host_irq = (uint16_t)intCfg[pinNum].intNum;
} else {
dst_id = TISCI_DEV_R5FSS1_CORE1;
- dst_host_irq = intCfg[pinNum].intNum;
+ dst_host_irq = (uint16_t)intCfg[pinNum].intNum;
}
#elif defined(BUILD_MPU1_0) || defined(BUILD_MPU1_1)
dst_id = TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS;
- dst_host_irq = intCfg[pinNum].intNum;
+ dst_host_irq = (uint16_t)intCfg[pinNum].intNum;
#elif defined(BUILD_DSP_1) || defined(BUILD_DSP_2)
if (CSL_chipReadDNUM() == 0U)
{
@@ -718,14 +767,14 @@ int32_t GPIO_socConfigIntrPath(uint32_t portNum, uint32_t pinNum,void *hwAttrs,b
/* Set the destination for core1 */
dst_id = TISCI_DEV_C66SS1_CORE0;
}
- dst_host_irq = intCfg[pinNum].eventId;
+ dst_host_irq = (uint16_t)intCfg[pinNum].eventId;
#elif defined(BUILD_C7X_1)
dst_id = TISCI_DEV_COMPUTE_CLUSTER0_CLEC;
- dst_host_irq = CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_WKUP_GPIOMUX_INTRTR0_OUTP_16 + bankNum;
+ dst_host_irq = (uint16_t)(CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_WKUP_GPIOMUX_INTRTR0_OUTP_16 + bankNum);
#endif
if(setIntrPath) {
- memset (&rmIrqReq,0,sizeof(rmIrqReq));
+ (void)memset (&rmIrqReq,0,sizeof(rmIrqReq));
rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
rmIrqReq.src_id = src_id;
@@ -740,7 +789,7 @@ int32_t GPIO_socConfigIntrPath(uint32_t portNum, uint32_t pinNum,void *hwAttrs,b
rmIrqReq.dst_id = dst_id;
rmIrqReq.dst_host_irq = dst_host_irq;
} else {
- memset (&rmIrqRelease,0,sizeof(rmIrqRelease));
+ (void)memset (&rmIrqRelease,0,sizeof(rmIrqRelease));
rmIrqRelease.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
rmIrqRelease.src_id = src_id;
@@ -757,7 +806,7 @@ int32_t GPIO_socConfigIntrPath(uint32_t portNum, uint32_t pinNum,void *hwAttrs,b
/* Config event */
if(setIntrPath) {
- if(GPIO_PinBankUsageCount[portNum][bankNum]==0) {
+ if(GPIO_PinBankUsageCount[portNum][bankNum] == 0U) {
retVal = Sciclient_rmIrqSet(
(const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
&rmIrqResp,
diff --git a/src/v0/GPIO_v0.c b/src/v0/GPIO_v0.c
index 7ec275750500a191c688d457396d5a536d3ff383..163ee3e17efd207714b7fcac12b72e9c3c462ce8 100644 (file)
--- a/src/v0/GPIO_v0.c
+++ b/src/v0/GPIO_v0.c
static uint32_t portHwiCreatedBitMask = 0;
/* Boolean to confirm that GPIO_init() has been called */
-static volatile bool initCalled = false;
+static volatile bool initCalled = (bool)false;
/* GPIO driver config data structure */
extern GPIO_v0_Config GPIO_v0_config;
*/
static inline uint32_t getPinNumber(uint32_t x) {
uint32_t idx = 0;
+ uint32_t v = x;
- while((x & 0x1U) == 0U)
+ while((v & 0x1U) == 0U)
{
idx++;
- x = x>>1;
+ v = v >> 1U;
}
return idx;
uint32_t portNum;
/* Input parameter validation */
- GPIO_osalAssert(!((true == initCalled) &&
- (index < GPIO_v0_config.numberOfPinConfigs)));
-
- pinConfig = GPIO_v0_config.pinConfigs[index];
- portNum = GPIO_GET_PORT_NUM(pinConfig);
- pinNum = GPIO_GET_PIN_NUM(pinConfig);
- if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
- (pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
+ if (((bool)true == initCalled) &&
+ (index < GPIO_v0_config.numberOfPinConfigs))
{
- GPIOIntrClear_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum);
+ pinConfig = GPIO_v0_config.pinConfigs[index];
+ portNum = GPIO_GET_PORT_NUM(pinConfig);
+ pinNum = GPIO_GET_PIN_NUM(pinConfig);
+ if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
+ (pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
+ {
+ GPIOIntrClear_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum);
+ }
}
}
static void GPIO_disableInt_v0(uint32_t index); /*for misra warnings*/
static void GPIO_disableInt_v0(uint32_t index)
{
- uint32_t key;
- uint32_t pinConfig;
- uint32_t pinNum;
- uint32_t portNum;
+ uintptr_t key;
+ uint32_t pinConfig;
+ uint32_t pinNum;
+ uint32_t portNum;
/* Input parameter validation */
- GPIO_osalAssert(!((true == initCalled) &&
- (index < GPIO_v0_config.numberOfPinConfigs)));
-
- pinConfig = GPIO_v0_config.pinConfigs[index];
- portNum = GPIO_GET_PORT_NUM(pinConfig);
- pinNum = GPIO_GET_PIN_NUM(pinConfig);
- if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
- (pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
+ if (((bool)true == initCalled) &&
+ (index < GPIO_v0_config.numberOfPinConfigs))
{
- /* Make atomic update */
- key = GPIO_osalHardwareIntDisable();
+ pinConfig = GPIO_v0_config.pinConfigs[index];
+ portNum = GPIO_GET_PORT_NUM(pinConfig);
+ pinNum = GPIO_GET_PIN_NUM(pinConfig);
+ if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
+ (pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
+ {
+ /* Make atomic update */
+ key = GPIO_osalHardwareIntDisable();
- GPIOIntrDisable_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum);
+ GPIOIntrDisable_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum);
- GPIO_osalHardwareIntRestore(key);
+ GPIO_osalHardwareIntRestore(key);
+ }
}
}
static void GPIO_enableInt_v0(uint32_t index); /*for misra warnings*/
static void GPIO_enableInt_v0(uint32_t index)
{
- uint32_t key;
- uint32_t pinConfig;
- uint32_t pinNum;
- uint32_t portNum;
- uint32_t intrEvtType;
-
- GPIO_osalAssert(!((true == initCalled) &&
- (index < GPIO_v0_config.numberOfPinConfigs)));
-
- pinConfig = GPIO_v0_config.pinConfigs[index];
- portNum = GPIO_GET_PORT_NUM(pinConfig);
- pinNum = GPIO_GET_PIN_NUM(pinConfig);
- if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
- (pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
+ uintptr_t key;
+ uint32_t pinConfig;
+ uint32_t pinNum;
+ uint32_t portNum;
+ uint32_t intrEvtType;
+
+ if (((bool)true == initCalled) &&
+ (index < GPIO_v0_config.numberOfPinConfigs))
{
- /* Make atomic update */
- key = GPIO_osalHardwareIntDisable();
+ pinConfig = GPIO_v0_config.pinConfigs[index];
+ portNum = GPIO_GET_PORT_NUM(pinConfig);
+ pinNum = GPIO_GET_PIN_NUM(pinConfig);
+ if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
+ (pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
+ {
+ /* Make atomic update */
+ key = GPIO_osalHardwareIntDisable();
- intrEvtType = GPIO_getIntEvtType(pinConfig);
- GPIOIntrEnable_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum, intrEvtType);
+ intrEvtType = GPIO_getIntEvtType(pinConfig);
+ GPIOIntrEnable_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum, intrEvtType);
- GPIO_osalHardwareIntRestore(key);
+ GPIO_osalHardwareIntRestore(key);
+ }
}
}
GPIOIntrClearMask_v0(gpioBase, bankIdx, gpioIntStatus);
/* Match each set bit to its corresponding callback function */
- while (gpioIntStatus)
+ while (gpioIntStatus != 0U)
{
/* Gets the lowest order set bit number */
pinNum = getPinNumber(gpioIntStatus) + (bankIdx * GPIO_NUM_PINS_PER_BANK);
intCfg = hwAttrs->intCfg + pinNum;
if (intCfg->intcMuxNum != INVALID_INTC_MUX_NUM)
{
- GPIO_osalHardwareIntrClear(intCfg->intcMuxInEvent,intCfg->intNum);
+ GPIO_osalHardwareIntrClear((int32_t)intCfg->intcMuxInEvent, (int32_t)intCfg->intNum);
GPIO_osalMuxIntcClearSysInt(intCfg->intcMuxNum, intCfg->intcMuxInEvent);
}
}
uint32_t pinNum;
/* Input parameter validation */
- GPIO_osalAssert(!((true == initCalled) &&
- (index < GPIO_v0_config.numberOfPinConfigs)));
-
- pinConfig = GPIO_v0_config.pinConfigs[index];
- portNum = GPIO_GET_PORT_NUM(pinConfig);
- pinNum = GPIO_GET_PIN_NUM(pinConfig);
- if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
- (pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
+ if (((bool)true == initCalled) &&
+ (index < GPIO_v0_config.numberOfPinConfigs))
{
- value = GPIOPinRead_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum);
+ pinConfig = GPIO_v0_config.pinConfigs[index];
+ portNum = GPIO_GET_PORT_NUM(pinConfig);
+ pinNum = GPIO_GET_PIN_NUM(pinConfig);
+ if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
+ (pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
+ {
+ value = GPIOPinRead_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum);
+ }
}
return value;
static void GPIO_setCallback_v0(uint32_t index, GPIO_CallbackFxn callback); /*for misra warnings*/
static void GPIO_setCallback_v0(uint32_t index, GPIO_CallbackFxn callback)
{
- uint32_t key;
- uint32_t pinConfig;
- uint32_t pinNum;
- uint32_t portNum;
-
- GPIO_osalAssert(index >= GPIO_v0_config.numberOfCallbacks);
+ uintptr_t key;
+ uint32_t pinConfig;
+ uint32_t pinNum;
+ uint32_t portNum;
- pinConfig = GPIO_v0_config.pinConfigs[index];
- portNum = GPIO_GET_PORT_NUM(pinConfig);
- pinNum = GPIO_GET_PIN_NUM(pinConfig);
- if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
- (pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
+ if (index < GPIO_v0_config.numberOfCallbacks)
{
- /* Make atomic update */
- key = GPIO_osalHardwareIntDisable();
-
- /* Store index into corresponding port's callbackInfo pinIndex entry */
- gpioCallbackInfo[portNum].pinIndex[pinNum] =
- (callback) ? index : CALLBACK_INDEX_NOT_CONFIGURED;
-
- /*
- * Only update callBackFunctions entry if different. This allows the
- * callBackFunctions array to be in flash for static systems.
- */
- if (GPIO_v0_config.callbacks[index] != callback) {
- GPIO_v0_config.callbacks[index] = callback;
- }
+ pinConfig = GPIO_v0_config.pinConfigs[index];
+ portNum = GPIO_GET_PORT_NUM(pinConfig);
+ pinNum = GPIO_GET_PIN_NUM(pinConfig);
+ if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
+ (pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
+ {
+ /* Make atomic update */
+ key = GPIO_osalHardwareIntDisable();
+
+ /* Store index into corresponding port's callbackInfo pinIndex entry */
+ gpioCallbackInfo[portNum].pinIndex[pinNum] =
+ (callback) ? (uint8_t)index : (uint8_t)CALLBACK_INDEX_NOT_CONFIGURED;
- GPIO_osalHardwareIntRestore(key);
+ /*
+ * Only update callBackFunctions entry if different. This allows the
+ * callBackFunctions array to be in flash for static systems.
+ */
+ if (GPIO_v0_config.callbacks[index] != callback) {
+ GPIO_v0_config.callbacks[index] = callback;
+ }
+
+ GPIO_osalHardwareIntRestore(key);
+ }
}
}
*/
static void GPIO_setConfig_v0(uint32_t index, GPIO_PinConfig pinConfig)
{
- uint32_t key;
+ uintptr_t key;
void * hwiHandle = NULL;
uint32_t gpioBase;
uint32_t intrEvtType;
int32_t ret_socIntrPath=CSL_PASS;
uint8_t ret_flag = 0U;
- GPIO_osalAssert(!(index < GPIO_v0_config.numberOfPinConfigs));
-
- portNum = GPIO_GET_PORT_NUM(pinConfig);
- pinNum = GPIO_GET_PIN_NUM(pinConfig);
- if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
+ if (index < GPIO_v0_config.numberOfPinConfigs)
+ {
+ portNum = GPIO_GET_PORT_NUM(pinConfig);
+ pinNum = GPIO_GET_PIN_NUM(pinConfig);
+ }
+ else
+ {
+ ret_flag = 1U;
+ }
+ if ((ret_flag == 0U) &&
+ (portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
(pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
{
pinConfigVal = GPIO_v0_config.pinConfigs[index];
/* Get GPIO configuration settings */
/* Determine settings for GPIO as input or output */
- if (pinConfig & GPIO_CFG_INPUT) {
+ if ((pinConfig & GPIO_CFG_INPUT) != 0U)
+ {
gpio_Direction = GPIO_DIRECTION_INPUT;
}
- else {
+ else
+ {
gpio_Direction = GPIO_DIRECTION_OUTPUT;
}
/* Set output value */
if (gpio_Direction == GPIO_DIRECTION_OUTPUT) {
GPIOPinWrite_v0(gpioBase, pinNum,
- ((pinConfig & GPIO_CFG_OUT_HIGH) ? 1 : 0));
+ (((pinConfig & GPIO_CFG_OUT_HIGH) != 0U) ? 1U : 0U));
}
/* Configure the GPIO pin */
}
/* Set type of interrupt and then clear it */
- if (pinConfig & GPIO_CFG_INT_MASK) {
+ if ((pinConfig & GPIO_CFG_INT_MASK) != 0U)
+ {
/* Initialize with defaults */
Osal_RegisterInterrupt_initParams(&interruptRegParams);
muxInParams.muxInEvent = intCfg->intcMuxInEvent;
muxInParams.muxOutEvent = intCfg->intcMuxOutEvent;
muxInParams.muxIntcFxn = (MuxIntcFxn)(&GPIO_v0_hwiFxn);
- GPIO_osalMuxIntcSetup(&muxInParams, &muxOutParams);
+ (void)GPIO_osalMuxIntcSetup(&muxInParams, &muxOutParams);
interruptRegParams.corepacConfig.isrRoutine = muxOutParams.muxIntcFxn;
interruptRegParams.corepacConfig.arg = muxOutParams.arg;
/* Populate the interrupt parameters */
interruptRegParams.corepacConfig.priority = GPIO_v0_config.intPriority;
interruptRegParams.corepacConfig.name=NULL;
- interruptRegParams.corepacConfig.corepacEventNum=intCfg->eventId; /* Event going in to CPU */
- interruptRegParams.corepacConfig.intVecNum=intCfg->intNum; /* Host Interrupt vector */
+ interruptRegParams.corepacConfig.corepacEventNum = (int32_t)intCfg->eventId; /* Event going in to CPU */
+ interruptRegParams.corepacConfig.intVecNum = (int32_t)intCfg->intNum; /* Host Interrupt vector */
#if defined (__aarch64__)
- interruptRegParams.corepacConfig.triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_EDGE; /* interrupt edge triggered */
+ interruptRegParams.corepacConfig.triggerSensitivity = (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_EDGE; /* interrupt edge triggered */
#endif
#if defined (__TI_ARM_V7R4__)
- interruptRegParams.corepacConfig.triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_EDGE;
+ interruptRegParams.corepacConfig.triggerSensitivity = (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_EDGE;
#endif
- /* Configure SOC interrupt path if any */
- if(hwAttrs->socConfigIntrPath!=NULL) {
- ret_socIntrPath = (*hwAttrs->socConfigIntrPath)(portNum,pinNum,hwAttrs,TRUE);
- }
+ /* Configure SOC interrupt path if any */
+ if(hwAttrs->socConfigIntrPath!=NULL) {
+ ret_socIntrPath = (*hwAttrs->socConfigIntrPath)(portNum,pinNum,hwAttrs,TRUE);
+ }
if(ret_socIntrPath==CSL_PASS) {
- /* Register interrupts */
- GPIO_osalRegisterInterrupt(&interruptRegParams,&(hwiHandle));
+ /* Register interrupts */
+ (void)GPIO_osalRegisterInterrupt(&interruptRegParams,&(hwiHandle));
}
if (hwiHandle == NULL) {
static void GPIO_toggle_v0(uint32_t index); /*for misra warnings*/
static void GPIO_toggle_v0(uint32_t index)
{
- uint32_t key;
- uint32_t value;
- uint32_t pinConfig;
- uint32_t pinNum;
- uint32_t portNum;
+ uintptr_t key;
+ uint32_t value;
+ uint32_t pinConfig;
+ uint32_t pinNum;
+ uint32_t portNum;
/* Input parameter validation */
- GPIO_osalAssert(!((true == initCalled) &&
- (index < GPIO_v0_config.numberOfPinConfigs)));
-
- pinConfig = GPIO_v0_config.pinConfigs[index];
- portNum = GPIO_GET_PORT_NUM(pinConfig);
- pinNum = GPIO_GET_PIN_NUM(pinConfig);
- if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
- (pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
+ if (((bool)true == initCalled) &&
+ (index < GPIO_v0_config.numberOfPinConfigs))
{
- /* Make atomic update */
- key = GPIO_osalHardwareIntDisable();
+ pinConfig = GPIO_v0_config.pinConfigs[index];
+ portNum = GPIO_GET_PORT_NUM(pinConfig);
+ pinNum = GPIO_GET_PIN_NUM(pinConfig);
+ if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
+ (pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
+ {
+ /* Make atomic update */
+ key = GPIO_osalHardwareIntDisable();
- value = GPIOPinOutValueRead_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum);
- value = (value == 0U) ? 1U : 0U;
- GPIOPinWrite_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum, value);
+ value = GPIOPinOutValueRead_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum);
+ value = (value == 0U) ? 1U : 0U;
+ GPIOPinWrite_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum, value);
- /* Update pinConfig with new output value */
- GPIO_v0_config.pinConfigs[index] ^= GPIO_CFG_OUT_HIGH;
+ /* Update pinConfig with new output value */
+ GPIO_v0_config.pinConfigs[index] ^= GPIO_CFG_OUT_HIGH;
- GPIO_osalHardwareIntRestore(key);
+ GPIO_osalHardwareIntRestore(key);
+ }
}
}
static void GPIO_write_v0(uint32_t index, uint32_t value); /*for misra warnings*/
static void GPIO_write_v0(uint32_t index, uint32_t value)
{
- uint32_t key;
- uint32_t pinConfig;
- uint32_t pinNum;
- uint32_t portNum;
+ uintptr_t key;
+ uint32_t pinConfig;
+ uint32_t pinNum;
+ uint32_t portNum;
/* Input parameter validation */
- GPIO_osalAssert(!((true == initCalled) &&
- (index < GPIO_v0_config.numberOfPinConfigs)));
-
- pinConfig = GPIO_v0_config.pinConfigs[index];
- portNum = GPIO_GET_PORT_NUM(pinConfig);
- pinNum = GPIO_GET_PIN_NUM(pinConfig);
- if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
- (pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
+ if (((bool)true == initCalled) &&
+ (index < GPIO_v0_config.numberOfPinConfigs))
{
- key = GPIO_osalHardwareIntDisable();
+ pinConfig = GPIO_v0_config.pinConfigs[index];
+ portNum = GPIO_GET_PORT_NUM(pinConfig);
+ pinNum = GPIO_GET_PIN_NUM(pinConfig);
+ if ((portNum < GPIO_MAX_HWATTRS_V0_CNT) &&
+ (pinNum < GPIO_MAX_NUM_PINS_PER_PORT))
+ {
+ key = GPIO_osalHardwareIntDisable();
- /* Clear output from pinConfig */
- GPIO_v0_config.pinConfigs[index] &= ~GPIO_CFG_OUT_HIGH;
+ /* Clear output from pinConfig */
+ GPIO_v0_config.pinConfigs[index] &= ~GPIO_CFG_OUT_HIGH;
- if (value) {
- /* Set the pinConfig output bit to high */
- GPIO_v0_config.pinConfigs[index] |= GPIO_CFG_OUT_HIGH;
- }
+ if (value != 0U)
+ {
+ /* Set the pinConfig output bit to high */
+ GPIO_v0_config.pinConfigs[index] |= GPIO_CFG_OUT_HIGH;
+ }
- GPIOPinWrite_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum, value);
+ GPIOPinWrite_v0(GPIO_v0_hwAttrs[portNum].baseAddr, pinNum, value);
- GPIO_osalHardwareIntRestore(key);
+ GPIO_osalHardwareIntRestore(key);
+ }
}
}
diff --git a/src/v0/GPIO_v0.h b/src/v0/GPIO_v0.h
index 4523f83b9e83472ae71a7df15efb398cf663809a..e0d547f6a14f14472c6ac40a4acb6c396fa840f2 100644 (file)
--- a/src/v0/GPIO_v0.h
+++ b/src/v0/GPIO_v0.h
/* Avoid Misra warning "MISRA.DECL.ARRAY_SIZE" by pairing config array type
* with its array size to avoid externs with [] (no size) */
-#define GPIO_MAX_HWATTRS_V0_CNT (2U)
+#define GPIO_MAX_HWATTRS_V0_CNT (8U)
typedef GPIO_v0_HwAttrs GPIO_v0_hwAttrsList[GPIO_MAX_HWATTRS_V0_CNT];
/*!
* configuration table. These macros should be OR'd in with the respective pin
* configuration settings.
*/
-#define GPIO_v0_EMPTY_PIN 0x0000
+#define GPIO_v0_EMPTY_PIN (0x0000U)
/* Invalid Intc Mux number, intc Mux not used if assigned INVALID_INTC_MUX_NUM */
-#define INVALID_INTC_MUX_NUM 0xffff
+#define INVALID_INTC_MUX_NUM ((int32_t)0xffff)
/* Invalid CorePac primary event ID */
-#define INVALID_INTC_EVENT_ID 0xffff
+#define INVALID_INTC_EVENT_ID ((int32_t)0xffff)
extern void GPIO_socGetNumPinsPorts(uint32_t *numPins, uint32_t *numPorts);
extern int32_t GPIO_socConfigIntrPath(uint32_t portNum, uint32_t pinNum,void *hwAttrs,bool setIntrPath);