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raw | patch | inline | side by side (parent: 9ad6aa0)
raw | patch | inline | side by side (parent: 9ad6aa0)
author | Suraj Das <s-das@ti.com> | |
Mon, 7 Mar 2016 20:03:14 +0000 (15:03 -0500) | ||
committer | Suraj Das <s-das@ti.com> | |
Mon, 7 Mar 2016 20:03:14 +0000 (15:03 -0500) |
14 files changed:
index 502824a0e120c4ffdaf26be79fba34a21a6e1983..be8dfd536961f3e390144d43037fe866491ff3b2 100644 (file)
\r
/* Flag variable to check transfer completion on channel 1 */\r
volatile short irqRaised1 = 0;\r
-/* Flag variable to check transfer completion on channel 2 */\r
-volatile short irqRaised2 = 0;\r
\r
/* Callback functions are used to handle interrupts. This is currently not enabled in this exmaple code.\r
* To see how the callback function is used, refer to the EDMA LLD example project.\r
}\r
\r
\r
-/* Callback function 2 */\r
-void callback2 (unsigned int tcc, EDMA3_RM_TccStatus status,\r
- void *appData)\r
- {\r
- (void)tcc;\r
- (void)appData;\r
-\r
- switch (status)\r
- {\r
- case EDMA3_RM_XFER_COMPLETE:\r
- /* Transfer completed successfully */\r
- irqRaised2 = 1;\r
- break;\r
- case EDMA3_RM_E_CC_DMA_EVT_MISS:\r
- /* Transfer resulted in DMA event miss error. */\r
- irqRaised2 = -1;\r
- break;\r
- case EDMA3_RM_E_CC_QDMA_EVT_MISS:\r
- /* Transfer resulted in QDMA event miss error. */\r
- irqRaised2 = -2;\r
- break;\r
- default:\r
- break;\r
- }\r
- }\r
-\r
-\r
\r
index f75f77fd09c74d7fd32b712dd8949638b989fd2f..623a84f235a1a8b49e196443665bcd10d25e5006 100644 (file)
extern void callback1 (unsigned int tcc, EDMA3_RM_TccStatus status,\r
void *appData);\r
\r
-extern void callback2 (unsigned int tcc, EDMA3_RM_TccStatus status,\r
- void *appData);\r
-\r
signed char* getGlobalAddr(signed char* addr);\r
/* Flag variable to check transfer completion on channel 1 */\r
extern volatile short irqRaised1;\r
-/* Flag variable to check transfer completion on channel 2 */\r
-extern volatile short irqRaised2;\r
-\r
\r
/*\r
* Note that not all of EDMAs are implemented. These\r
unsigned long* totalTime);\r
\r
\r
-\r
-/**\r
- * \brief EDMA3 mem-to-mem data copy test case, using two DMA\r
- * channels, linked to each other.\r
- *\r
- * \param hEdma [IN] EDMA handle\r
- * \param acnt [IN] Number of bytes in an array\r
- * \param bcnt [IN] Number of arrays in a frame\r
- * \param ccnt [IN] Number of frames in a block\r
- * \param syncType [IN] Synchronization type (A/AB Sync)\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- */\r
-EDMA3_DRV_Result edma3_test_with_link(\r
- EDMA3_DRV_Handle hEdma,\r
- unsigned int acnt,\r
- unsigned int bcnt,\r
- unsigned int ccnt,\r
- EDMA3_DRV_SyncType syncType);\r
-\r
-\r
-\r
-/**\r
- * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel.\r
- *\r
- * \param hEdma [IN] EDMA handle\r
- * \param srcBuff [IN] Source buffer address\r
- * \param dstBuff [IN] Destination buffer address\r
- * \param acnt [IN] Number of bytes in an array\r
- * \param bcnt [IN] Number of arrays in a frame\r
- * \param ccnt [IN] Number of frames in a block\r
- * \param syncType [IN] Synchronization type (A/AB Sync)\r
- * \param totalTime [out] Total time it takes to transfer data\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- */\r
-EDMA3_DRV_Result qdma_test(\r
- EDMA3_DRV_Handle hEdma,\r
- unsigned int* srcBuff,\r
- unsigned int* dstBuff,\r
- unsigned int acnt,\r
- unsigned int bcnt,\r
- unsigned int ccnt,\r
- EDMA3_DRV_SyncType syncType,\r
- unsigned long * totalTime);\r
-\r
-\r
-\r
-/**\r
- * \brief EDMA3 misc test cases.\r
- * This test case will read/write to some CC registers.\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- */\r
-EDMA3_DRV_Result edma3_misc_test(EDMA3_DRV_Handle hEdma);\r
-\r
-\r
-/**\r
- * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel,\r
- * linked to another LINK channel.\r
- *\r
- * \param acnt [IN] Number of bytes in an array\r
- * \param bcnt [IN] Number of arrays in a frame\r
- * \param ccnt [IN] Number of frames in a block\r
- * \param syncType [IN] Synchronization type (A/AB Sync)\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- */\r
-EDMA3_DRV_Result qdma_test_with_link(\r
- EDMA3_DRV_Handle hEdma,\r
- unsigned int acnt,\r
- unsigned int bcnt,\r
- unsigned int ccnt,\r
- EDMA3_DRV_SyncType syncType);\r
-\r
-\r
-/**\r
- * \brief EDMA3 mem-to-mem data copy test case, using two DMA channels,\r
- * chained to each other.\r
- *\r
- * \param acnt [IN] Number of bytes in an array\r
- * \param bcnt [IN] Number of arrays in a frame\r
- * \param ccnt [IN] Number of frames in a block\r
- * \param syncType [IN] Synchronization type (A/AB Sync)\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- */\r
-EDMA3_DRV_Result edma3_test_with_chaining(\r
- EDMA3_DRV_Handle hEdma,\r
- unsigned int acnt,\r
- unsigned int bcnt,\r
- unsigned int ccnt,\r
- EDMA3_DRV_SyncType syncType);\r
-\r
-\r
-/**\r
- * \brief EDMA3 mem-to-mem data copy test case, using a DMA channel.\r
- * This test case doesnot rely on the callback mechanism.\r
- * Instead, it Polls the IPR register to check the transfer\r
- * completion status.\r
- *\r
- * \param acnt [IN] Number of bytes in an array\r
- * \param bcnt [IN] Number of arrays in a frame\r
- * \param ccnt [IN] Number of frames in a block\r
- * \param syncType [IN] Synchronization type (A/AB Sync)\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- */\r
-EDMA3_DRV_Result edma3_test_poll_mode(\r
- EDMA3_DRV_Handle hEdma,\r
- unsigned int acnt,\r
- unsigned int bcnt,\r
- unsigned int ccnt,\r
- EDMA3_DRV_SyncType syncType);\r
-\r
-\r
-/**\r
- * \brief EDMA3 ping-pong based data copy test case, using a DMA and\r
- * a link channel.\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- */\r
-EDMA3_DRV_Result edma3_test_ping_pong_mode(EDMA3_DRV_Handle hEdma);\r
-\r
-\r
#endif /* HYPLNKEDMA_H_ */\r
index 7bf28e57874b18f2a378b66e31c21c070f28f7e8..1fa5a895372d1f76254f1a5a594dfae348641284 100644 (file)
\r
int EDMA_debug = 0;\r
#ifdef DEBUG_MODE\r
-int EDMA_debug = 1;\r
+ EDMA_debug = 1;\r
#endif\r
\r
-/**\r
- * DSP instance number on which the executable is running. Its value is\r
- * determined by reading the processor specific register DNUM.\r
- */\r
-unsigned int dsp_num_tmp;\r
-/* To find out the DSP# */\r
-extern unsigned short determineProcId();\r
-extern EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[][EDMA3_MAX_REGIONS];\r
-extern EDMA3_RM_InstanceInitConfig defInstInitConfig[][EDMA3_MAX_REGIONS];\r
/* External Global Configuration Structure */\r
extern EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[];\r
\r
EDMA3_DRV_SyncType syncType,\r
unsigned long* totalTime);\r
\r
-/**\r
- * \brief This function determines if testing on a EDMA3 instance will be bypassed.\r
- * When there are no EDMA channels allocated for the core from the given EDMA3\r
- * instance, testing shall be bypassed.\r
- *\r
- * \return TRUE if bypass; FALSE if testing will done.\r
- */\r
-unsigned int bypassCore(unsigned int edmaInstNum) {\r
- unsigned int i, bypassFlag = 1;\r
-\r
-#ifndef EDMA3_DRV_USE_DEF_RM_CFG\r
- EDMA3_DRV_InstanceInitConfig *instanceConfig = NULL;\r
-#else\r
- EDMA3_RM_InstanceInitConfig *rmInstInitCfg = NULL;\r
-#endif\r
-\r
- /* DSP instance number */\r
- dsp_num_tmp = determineProcId();\r
-\r
-#ifndef EDMA3_DRV_USE_DEF_RM_CFG\r
- /* configuration structure for the Driver */\r
- instanceConfig = &sampleInstInitConfig[edmaInstNum][dsp_num_tmp];\r
- for (i = 0; i < EDMA3_MAX_DMA_CHAN_DWRDS; i++) {\r
- if (instanceConfig->ownDmaChannels[i])\r
- bypassFlag = 0;\r
- }\r
-#else\r
- /* configuration structure for the Driver */\r
- rmInstInitCfg = &defInstInitConfig[edmaInstNum][dsp_num_tmp];\r
- for (i = 0; i < EDMA3_MAX_DMA_CHAN_DWRDS; i++)\r
- {\r
- if(rmInstInitCfg->ownDmaChannels[i])\r
- bypassFlag = 0;\r
- }\r
-#endif\r
-\r
- return (bypassFlag);\r
-}\r
\r
EDMA3_DRV_Handle edmaInit(EDMA3_DRV_Handle hEdma) {\r
EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK;\r
}\r
break;\r
\r
- case (QDMA):\r
- // Qdma test, async, incr mode\r
- if (result == EDMA3_DRV_SOK) {\r
- result = qdma_test(hEdma, src, dst, acnt, bcnt, ccnt, syncType,totalTime);\r
-\r
- if (result == EDMA3_DRV_SOK) {\r
- if(EDMA_debug)printf("qdma_test Passed\r\n");\r
- } else {\r
- printf("qdma_test Failed\r\n");\r
- }\r
- }\r
- break;\r
-\r
-/*\r
- * The following is setup code for the other types of EDMA transfer\r
- * In order for them to work, the code from the EDMA examples must be transfered to\r
- * this project directory and adjusted similarly to the way "dma_test.c" and "qmda_test.c"\r
- * were adjusted.\r
- */\r
-\r
- case (EDMA3_WITH_LINK):\r
- printf("edma3_test_with_link not implemented\r\n");\r
- break;\r
-\r
- case (QDMA_WITH_LINK):\r
- printf("qdma_test_with_link not implemented\r\n");\r
- break;\r
-\r
- case (EDMA3_WITH_CHAIN):\r
- printf("edma3_test_with_chaining not implemented\r\n");\r
- break;\r
-\r
- case (EDMA3_POLL_MODE):\r
- printf("edma3_test_poll_mode not implemented\r\n");\r
- break;\r
-\r
- case (EDMA3_PING_PONG):\r
- printf("edma3_test_ping_pong_mode not implemented\r\n");\r
- break;\r
-\r
- case (EDMA3_MISC):\r
- printf("edma3_misc_test not implemented\r\n");\r
- break;\r
-\r
default:\r
printf("EDMA type unknown.");\r
break;\r
diff --git a/example/EDMA/hyplnkQDMA.c b/example/EDMA/hyplnkQDMA.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*\r
- * qdma_test.c\r
- *\r
- * EDMA3 mem-to-mem data copy test case, using a QDMA channel.\r
- *\r
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/\r
- *\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- *\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- *\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the\r
- * distribution.\r
- *\r
- * Neither the name of Texas Instruments Incorporated nor the names of\r
- * its contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- */\r
-\r
-#include "hyplnkEDMA.h"\r
-\r
-/**\r
- * \brief EDMA3 mem-to-mem data copy test case, using a QDMA channel.\r
- *\r
- * \param hEdma [IN] EDMA handle\r
- * \param srcBuff [IN] Source buffer address\r
- * \param dstBuff [IN] Destination buffer address\r
- * \param acnt [IN] Number of bytes in an array\r
- * \param bcnt [IN] Number of arrays in a frame\r
- * \param ccnt [IN] Number of frames in a block\r
- * \param syncType [IN] Synchronization type (A/AB Sync)\r
- *\r
- * \return EDMA3_DRV_SOK or EDMA3_DRV Error Code\r
- */\r
-EDMA3_DRV_Result qdma_test(EDMA3_DRV_Handle hEdma, unsigned int* srcBuff,\r
- unsigned int* dstBuff, unsigned int acnt, unsigned int bcnt,\r
- unsigned int ccnt, EDMA3_DRV_SyncType syncType,unsigned long * totalTime) {\r
- EDMA3_DRV_Result result = EDMA3_DRV_SOK;\r
- unsigned int i;\r
- unsigned int numenabled = 0;\r
- unsigned int qCh1Id = 0;\r
- unsigned int qTcc1 = 0;\r
- unsigned int BRCnt = 0;\r
- int srcbidx = 0, desbidx = 0;\r
- int srccidx = 0, descidx = 0;\r
- unsigned int* srcBuff1;\r
- unsigned int* dstBuff1;\r
- unsigned int dataSize;\r
- unsigned long startTime=0;\r
-\r
-\r
- srcBuff1 = (unsigned int*) GLOBAL_ADDR((signed char*)srcBuff);\r
- dstBuff1 = (unsigned int*) GLOBAL_ADDR((signed char*)dstBuff);\r
-\r
-#ifdef EDMA3_ENABLE_DCACHE\r
- /*\r
- * Note: These functions are required if the buffer is in DDR.\r
- * For other cases, where buffer is NOT in DDR, user\r
- * may or may not require the below functions.\r
- */\r
- /* Flush the Source Buffer */\r
- if (result == EDMA3_DRV_SOK) {\r
- result = Edma3_CacheFlush((unsigned int) srcBuff1,\r
- (acnt * bcnt * ccnt));\r
- }\r
-\r
- /* Invalidate the Destination Buffer */\r
- if (result == EDMA3_DRV_SOK) {\r
- result = Edma3_CacheInvalidate((unsigned int) dstBuff1,\r
- (acnt * bcnt * ccnt));\r
- }\r
-#endif /* EDMA3_ENABLE_DCACHE */\r
-\r
- irqRaised1 = 0;\r
-\r
- /* Set B count reload as B count. */\r
- BRCnt = bcnt;\r
-\r
- /* set the SRC/DES Indexes\r
- *\r
- * Divide by the number of bytes in source type (int=4, long=8)\r
- */\r
- dataSize = sizeof(srcBuff1[0]);\r
-\r
- srcbidx = (int)acnt/dataSize;\r
- desbidx = (int)acnt/dataSize;\r
- if (syncType == EDMA3_DRV_SYNC_A)\r
- {\r
- /* A Sync Transfer Mode */\r
- srccidx = (int)acnt/dataSize;\r
- descidx = (int)acnt/dataSize;\r
- }\r
- else\r
- {\r
- /* AB Sync Transfer Mode */\r
- srccidx = ((int)acnt * (int)bcnt)/dataSize;\r
- descidx = ((int)acnt * (int)bcnt)/dataSize;\r
- }\r
-\r
-\r
- /* Setup for any QDMA Channel */\r
- qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;\r
- qTcc1 = EDMA3_DRV_TCC_ANY;\r
-\r
- if (result == EDMA3_DRV_SOK) {\r
- result = EDMA3_DRV_requestChannel(hEdma, &qCh1Id, &qTcc1,\r
- (EDMA3_RM_EventQueue) 0, &callback1, NULL);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK) {\r
- /* Set QDMA Trigger Word as Destination Address */\r
- result = EDMA3_DRV_setQdmaTrigWord(hEdma, qCh1Id,\r
- EDMA3_RM_QDMA_TRIG_DST);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK) {\r
- result = EDMA3_DRV_setSrcIndex(hEdma, qCh1Id, srcbidx, srccidx);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK) {\r
- result = EDMA3_DRV_setDestIndex(hEdma, qCh1Id, desbidx, descidx);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK) {\r
- if (syncType == EDMA3_DRV_SYNC_A) {\r
- result = EDMA3_DRV_setTransferParams(hEdma, qCh1Id, acnt, bcnt,\r
- ccnt, BRCnt, EDMA3_DRV_SYNC_A);\r
- } else {\r
- /* AB Sync Transfer Mode */\r
- result = EDMA3_DRV_setTransferParams(hEdma, qCh1Id, acnt, bcnt,\r
- ccnt, BRCnt, EDMA3_DRV_SYNC_AB);\r
- }\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK) {\r
- /* Enable Transfer Completion Interrupt */\r
- result = EDMA3_DRV_setOptField(hEdma, qCh1Id,\r
- EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK) {\r
- /* Enable Intermediate Transfer Completion Interrupt */\r
- result = EDMA3_DRV_setOptField(hEdma, qCh1Id,\r
- EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK) {\r
- /* Set Source Transfer Mode as Increment Mode. */\r
- result = EDMA3_DRV_setOptField(hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_SAM,\r
- EDMA3_DRV_ADDR_MODE_INCR);\r
- }\r
-\r
- if (result == EDMA3_DRV_SOK) {\r
- /* Set Destination Transfer Mode as Increment Mode. */\r
- result = EDMA3_DRV_setOptField(hEdma, qCh1Id, EDMA3_DRV_OPT_FIELD_DAM,\r
- EDMA3_DRV_ADDR_MODE_INCR);\r
- }\r
-\r
- /*\r
- * Since the transfer is going to happen in QDMA mode of EDMA3\r
- * operation, we have to "Trigger" the transfer multiple times.\r
- * Number of times depends upon the Mode (A/AB Sync)\r
- * and the different counts.\r
- */\r
- if (result == EDMA3_DRV_SOK) {\r
- /*Need to activate next param*/\r
- if (syncType == EDMA3_DRV_SYNC_A) {\r
- numenabled = bcnt * ccnt;\r
- } else {\r
- /* AB Sync Transfer Mode */\r
- numenabled = ccnt;\r
- }\r
-\r
- *totalTime = 0;\r
-\r
- for (i = 0u; i < numenabled; i++) {\r
- irqRaised1 = 0u;\r
-\r
- if (i == (numenabled - 1u)) {\r
- /**\r
- * Since OPT.STATIC field should be SET for isolated QDMA\r
- * transfers or for the final transfer in a linked list of QDMA\r
- * transfers, do the needful for the last request.\r
- */\r
- result = EDMA3_DRV_setOptField(hEdma, qCh1Id,\r
- EDMA3_DRV_OPT_FIELD_STATIC, 1u);\r
- }\r
-\r
- /* Write to the Source Address */\r
- result = EDMA3_DRV_setSrcParams(hEdma, qCh1Id,\r
- (unsigned int) (srcBuff1), EDMA3_DRV_ADDR_MODE_INCR,\r
- EDMA3_DRV_W8BIT);\r
- /*\r
- * Now trigger the QDMA channel by writing to the Trigger\r
- * Word which is set as Destination Address.\r
- */\r
- startTime = hyplnkExampleReadTime(); //Start time as soon as transfer is enabled\r
-\r
- if (result == EDMA3_DRV_SOK) {\r
- result = EDMA3_DRV_setPaRAMEntry(hEdma, qCh1Id,\r
- EDMA3_DRV_PARAM_ENTRY_DST, (unsigned int) (dstBuff1));\r
- if (result != EDMA3_DRV_SOK) {\r
- printf("error from qdma_test\n\r\n");\r
- break;\r
- }\r
- }\r
-\r
- /**Wait for a transfer completion interrupt to occur and clear it**/\r
- result = EDMA3_DRV_waitAndClearTcc(hEdma, (uint32_t) qTcc1);\r
-\r
- *totalTime += (hyplnkExampleReadTime() - startTime); //End time after transfer completion\r
-\r
- if (result != EDMA3_DRV_SOK) {\r
- printf("edma3_test: EDMA3_DRV_waitAndClearTcc "\r
- "Failed, error code: %d\r\n", result);\r
- break;\r
- }\r
-\r
- /* Check the status of the completed transfer */\r
- if (irqRaised1 < 0) {\r
- /* Some error occured, break from the FOR loop. */\r
- printf("\r\nqdma_test: Event Miss Occured!!!\r\n");\r
-\r
- /* Clear the error bits first */\r
- result = EDMA3_DRV_clearErrorBits(hEdma, qCh1Id);\r
-\r
- break;\r
- }\r
-\r
- /**\r
- * Now, update the source and destination addresses for next\r
- * "Trigger".\r
- */\r
-\r
- srcBuff1 += srccidx;\r
- dstBuff1 += descidx;\r
- }\r
- }\r
-\r
- /* Free the previously allocated channel. */\r
- result = EDMA3_DRV_freeChannel(hEdma, qCh1Id);\r
- if (result != EDMA3_DRV_SOK) {\r
- printf("qdma_test: EDMA3_DRV_freeChannel() FAILED, error code: %d\r\n",\r
- result);\r
- }\r
-\r
- return result;\r
-}\r
-\r
diff --git a/example/memoryMappedExample/c6657/c66/bios/hyplnk_evmc6657_C66BiosExampleProject.txt b/example/memoryMappedExample/c6657/c66/bios/hyplnk_evmc6657_C66BiosExampleProject.txt
index 12854e544f0e4ad6021305ecfc87c10925132e8b..e09ad69f1c1600acea034fd78de931cbe64778a6 100644 (file)
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/commonEDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkEDMAselector.c"
--ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkQDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.h"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/device/c6657/src/hyplnk_device.c"
diff --git a/example/memoryMappedExample/c6657/c66/bios/hyplnk_evmc6657_C66DevLibBiosExampleProject.txt b/example/memoryMappedExample/c6657/c66/bios/hyplnk_evmc6657_C66DevLibBiosExampleProject.txt
index 4195d8d2da2c2142b7148520d69cee3fbcd9da4d..6cb8c3ccd98eb1681afce2b1ae1c4871734464cf 100644 (file)
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/commonEDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkEDMAselector.c"
--ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkQDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.h"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/device/c6657/src/hyplnk_device.c"
diff --git a/example/memoryMappedExample/c6678/c66/bios/hyplnk_evmc6678_C66BiosExampleProject.txt b/example/memoryMappedExample/c6678/c66/bios/hyplnk_evmc6678_C66BiosExampleProject.txt
index 1a91b1190c9d840d98932f0fe4e192f08397a8a3..4834499239b09e1d320caa1f93e9621a298c139a 100644 (file)
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/commonEDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkEDMAselector.c"
--ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkQDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.h"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/device/c6678/src/hyplnk_device.c"
diff --git a/example/memoryMappedExample/c6678/c66/bios/hyplnk_evmc6678_C66DevLibBiosExampleProject.txt b/example/memoryMappedExample/c6678/c66/bios/hyplnk_evmc6678_C66DevLibBiosExampleProject.txt
index bb54c3febdca7ccad544f56fd85c38442d9e6777..b0ce9df4a69c89158f2ef14adf4265089f2ca28f 100644 (file)
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/commonEDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkEDMAselector.c"
--ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkQDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.h"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/device/c6678/src/hyplnk_device.c"
diff --git a/example/memoryMappedExample/k2e/c66/bios/hyplnk_K2EC66BiosExampleProject.txt b/example/memoryMappedExample/k2e/c66/bios/hyplnk_K2EC66BiosExampleProject.txt
index e02c7c31b4252312f6429e35255e613ce1293a69..4f72517a95ca8b2c8b4cf55e05e2474a6b8d8d30 100644 (file)
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/commonEDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkEDMAselector.c"
--ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkQDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.h"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/device/k2e/src/hyplnk_device.c"
diff --git a/example/memoryMappedExample/k2e/c66/bios/hyplnk_K2EC66DevLibBiosExampleProject.txt b/example/memoryMappedExample/k2e/c66/bios/hyplnk_K2EC66DevLibBiosExampleProject.txt
index b5df5c8b60a81a47734ea151aba0871d1f5f05da..40f0e27e372514cf0dcb6abdd0438200d7bc7121 100644 (file)
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/commonEDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkEDMAselector.c"
--ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkQDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.h"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/device/k2e/src/hyplnk_device.c"
diff --git a/example/memoryMappedExample/k2h/c66/bios/hyplnk_K2HC66BiosExampleProject.txt b/example/memoryMappedExample/k2h/c66/bios/hyplnk_K2HC66BiosExampleProject.txt
index af0bed1047b6381748356189072bf399fb10c7de..5e3b96d4bf4cef0fd5b5c5fc18c72f4de0624027 100644 (file)
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/commonEDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkEDMAselector.c"
--ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkQDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.h"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/device/k2h/src/hyplnk_device.c"
diff --git a/example/memoryMappedExample/k2h/c66/bios/hyplnk_K2HC66DevLibBiosExampleProject.txt b/example/memoryMappedExample/k2h/c66/bios/hyplnk_K2HC66DevLibBiosExampleProject.txt
index a641737806af8f3527224ad3ddeb1b1594413722..d9fbfc26aa4061a951915213d6fcb73ba3706a70 100644 (file)
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/commonEDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkEDMAselector.c"
--ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkQDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.h"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/device/k2h/src/hyplnk_device.c"
diff --git a/example/memoryMappedExample/k2k/c66/bios/hyplnk_K2KC66BiosExampleProject.txt b/example/memoryMappedExample/k2k/c66/bios/hyplnk_K2KC66BiosExampleProject.txt
index 8690bc2858f5517e2a0750da83b6b6b7331540c9..2ec386c6bd5436fab32372d2da3f75df43ef0348 100644 (file)
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/commonEDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkEDMAselector.c"
--ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkQDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.h"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/device/k2k/src/hyplnk_device.c"
diff --git a/example/memoryMappedExample/k2k/c66/bios/hyplnk_K2KC66DevLibBiosExampleProject.txt b/example/memoryMappedExample/k2k/c66/bios/hyplnk_K2KC66DevLibBiosExampleProject.txt
index 6fbda433d52e71b2f546885a83d50793c2883e12..5c5222c1c7b7a1c51952e02b588ea71afb0ad93e 100644 (file)
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/commonEDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkEDMAselector.c"
--ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/EDMA/hyplnkQDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.c"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/example/InfraDMA/hyplnkInfraDMA.h"
-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/hyplnk/device/k2k/src/hyplnk_device.c"