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59 <div class="title">ibl.h</div> </div>
60 </div>
61 <div class="contents">
62 <div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">/*</span>
63 <a name="l00002"></a>00002 <span class="comment"> *</span>
64 <a name="l00003"></a>00003 <span class="comment"> * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/</span>
65 <a name="l00004"></a>00004 <span class="comment"> *</span>
66 <a name="l00005"></a>00005 <span class="comment"> *</span>
67 <a name="l00006"></a>00006 <span class="comment"> * Redistribution and use in source and binary forms, with or without</span>
68 <a name="l00007"></a>00007 <span class="comment"> * modification, are permitted provided that the following conditions</span>
69 <a name="l00008"></a>00008 <span class="comment"> * are met:</span>
70 <a name="l00009"></a>00009 <span class="comment"> *</span>
71 <a name="l00010"></a>00010 <span class="comment"> * Redistributions of source code must retain the above copyright</span>
72 <a name="l00011"></a>00011 <span class="comment"> * notice, this list of conditions and the following disclaimer.</span>
73 <a name="l00012"></a>00012 <span class="comment"> *</span>
74 <a name="l00013"></a>00013 <span class="comment"> * Redistributions in binary form must reproduce the above copyright</span>
75 <a name="l00014"></a>00014 <span class="comment"> * notice, this list of conditions and the following disclaimer in the</span>
76 <a name="l00015"></a>00015 <span class="comment"> * documentation and/or other materials provided with the</span>
77 <a name="l00016"></a>00016 <span class="comment"> * distribution.</span>
78 <a name="l00017"></a>00017 <span class="comment"> *</span>
79 <a name="l00018"></a>00018 <span class="comment"> * Neither the name of Texas Instruments Incorporated nor the names of</span>
80 <a name="l00019"></a>00019 <span class="comment"> * its contributors may be used to endorse or promote products derived</span>
81 <a name="l00020"></a>00020 <span class="comment"> * from this software without specific prior written permission.</span>
82 <a name="l00021"></a>00021 <span class="comment"> *</span>
83 <a name="l00022"></a>00022 <span class="comment"> * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS</span>
84 <a name="l00023"></a>00023 <span class="comment"> * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT</span>
85 <a name="l00024"></a>00024 <span class="comment"> * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR</span>
86 <a name="l00025"></a>00025 <span class="comment"> * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT</span>
87 <a name="l00026"></a>00026 <span class="comment"> * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,</span>
88 <a name="l00027"></a>00027 <span class="comment"> * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT</span>
89 <a name="l00028"></a>00028 <span class="comment"> * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,</span>
90 <a name="l00029"></a>00029 <span class="comment"> * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY</span>
91 <a name="l00030"></a>00030 <span class="comment"> * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT</span>
92 <a name="l00031"></a>00031 <span class="comment"> * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE</span>
93 <a name="l00032"></a>00032 <span class="comment"> * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span>
94 <a name="l00033"></a>00033 <span class="comment"> *</span>
95 <a name="l00034"></a>00034 <span class="comment">*/</span>
96 <a name="l00035"></a>00035
97 <a name="l00036"></a>00036
98 <a name="l00037"></a>00037
99 <a name="l00038"></a>00038 <span class="comment">/********************************************************************************************************</span>
100 <a name="l00039"></a>00039 <span class="comment"> * FILE PURPOSE: IBL configuration and control definitions</span>
101 <a name="l00040"></a>00040 <span class="comment"> ********************************************************************************************************</span>
102 <a name="l00041"></a>00041 <span class="comment"> * FILE NAME: ibl.h</span>
103 <a name="l00042"></a>00042 <span class="comment"> *</span>
104 <a name="l00043"></a>00043 <span class="comment"> * DESCRIPTION: Defines the data structure used to handle initial configuration and control</span>
105 <a name="l00044"></a>00044 <span class="comment"> * of the ibl. This data structure resides at a fixed location in the device memory</span>
106 <a name="l00045"></a>00045 <span class="comment"> * map. It is initially populated either during the rom boot. The table can be</span>
107 <a name="l00046"></a>00046 <span class="comment"> * over-written during the ibl process to redirect the boot. For example the ibl</span>
108 <a name="l00047"></a>00047 <span class="comment"> * can initially load from an i2c which repopulates this table with parameters</span>
109 <a name="l00048"></a>00048 <span class="comment"> * for an ethernet boot.</span>
110 <a name="l00049"></a>00049 <span class="comment"> *</span>
111 <a name="l00050"></a>00050 <span class="comment"> * @file ibl.h</span>
112 <a name="l00051"></a>00051 <span class="comment"> *</span>
113 <a name="l00052"></a>00052 <span class="comment"> * @brief</span>
114 <a name="l00053"></a>00053 <span class="comment"> * This file defines the configuration and control of the IBL</span>
115 <a name="l00054"></a>00054 <span class="comment"> *</span>
116 <a name="l00055"></a>00055 <span class="comment"> *</span>
117 <a name="l00056"></a>00056 <span class="comment"> ********************************************************************************************************/</span>
118 <a name="l00057"></a>00057 <span class="preprocessor">#ifndef IBL_H</span>
119 <a name="l00058"></a>00058 <span class="preprocessor"></span><span class="preprocessor">#define IBL_H</span>
120 <a name="l00059"></a>00059 <span class="preprocessor"></span>
121 <a name="l00060"></a>00060 <span class="preprocessor">#include "types.h"</span>
122 <a name="l00061"></a>00061
123 <a name="l00062"></a>00062
124 <a name="l00063"></a>00063 <span class="preprocessor">#define ibl_MAKE_VERSION(a,b,c,d) ((a << 24) | (b << 16) | (c << 8) | (d << 0))</span>
125 <a name="l00064"></a>00064 <span class="preprocessor"></span>
126 <a name="l00065"></a>00065
127 <a name="l00070"></a>00070 <span class="preprocessor">#define ibl_VERSION ibl_MAKE_VERSION(1,0,0,4)</span>
128 <a name="l00071"></a>00071 <span class="preprocessor"></span>
129 <a name="l00072"></a>00072
130 <a name="l00080"></a>00080 <span class="preprocessor"> #define ibl_BOOT_MODE_TFTP 10 </span><span class="comment">/* Boot through a tftp interface */</span>
131 <a name="l00081"></a>00081
132 <a name="l00082"></a>00082 <span class="comment">/* @def ibl_BOOT_MODE_NAND */</span>
133 <a name="l00083"></a>00083 <span class="preprocessor">#define ibl_BOOT_MODE_NAND 11 </span><span class="comment">/* Boot through a nand interface */</span>
134 <a name="l00084"></a>00084
135 <a name="l00085"></a>00085 <span class="comment">/* @def ibl_BOOT_MODE_NOR */</span>
136 <a name="l00086"></a>00086 <span class="preprocessor">#define ibl_BOOT_MODE_NOR 12 </span><span class="comment">/* Boot through a nor (or flash) interface */</span>
137 <a name="l00087"></a>00087
138 <a name="l00088"></a>00088 <span class="comment">/* @def ibl_BOOT_MODE_NONE */</span>
139 <a name="l00089"></a>00089 <span class="preprocessor">#define ibl_BOOT_MODE_NONE 13 </span><span class="comment">/* Boot mode selection is inactive */</span>
140 <a name="l00090"></a>00090
141 <a name="l00091"></a>00091 <span class="comment">/* @} */</span>
142 <a name="l00092"></a>00092
143 <a name="l00098"></a>00098 <span class="preprocessor">#define ibl_N_BOOT_MODES 3</span>
144 <a name="l00099"></a>00099 <span class="preprocessor"></span>
145 <a name="l00100"></a>00100 <span class="comment">/* Information used to make generate a bootp request */</span>
146 <a name="l00108"></a><a class="code" href="structibl_bootp__s.html">00108</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structibl_bootp__s.html" title="Defines parameters used for making a bootp request.">iblBootp_s</a>
147 <a name="l00109"></a>00109 {
148 <a name="l00110"></a><a class="code" href="structibl_bootp__s.html#a902455b75b0f4a69b58ea73990ae8246">00110</a> uint8 <a class="code" href="structibl_bootp__s.html#a902455b75b0f4a69b58ea73990ae8246">hwAddress</a>[6];
149 <a name="l00113"></a><a class="code" href="structibl_bootp__s.html#aaf59fc9e70a72cca95bc675b486fbf31">00113</a> uint8 <a class="code" href="structibl_bootp__s.html#aaf59fc9e70a72cca95bc675b486fbf31">ipDest</a>[4];
150 <a name="l00116"></a>00116 } <a class="code" href="structibl_bootp__s.html" title="Defines parameters used for making a bootp request.">iblBootp_t</a>;
151 <a name="l00117"></a>00117
152 <a name="l00118"></a>00118
153 <a name="l00126"></a><a class="code" href="structibl_eth_boot_info__s.html">00126</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structibl_eth_boot_info__s.html" title="This structure contains information used for tftp boot.">iblEthBootInfo_s</a>
154 <a name="l00127"></a>00127 {
155 <a name="l00128"></a><a class="code" href="structibl_eth_boot_info__s.html#aa5a4a8a407789bb2b9250adadc89662b">00128</a> uint8 <a class="code" href="structibl_eth_boot_info__s.html#aa5a4a8a407789bb2b9250adadc89662b">ipAddr</a>[4];
156 <a name="l00129"></a><a class="code" href="structibl_eth_boot_info__s.html#ac134470babb5e0ff1ef0f85d703c5cb1">00129</a> uint8 <a class="code" href="structibl_eth_boot_info__s.html#ac134470babb5e0ff1ef0f85d703c5cb1">serverIp</a>[4];
157 <a name="l00130"></a><a class="code" href="structibl_eth_boot_info__s.html#ae539a45ecce271d4edbd276b7ca2410e">00130</a> uint8 <a class="code" href="structibl_eth_boot_info__s.html#ae539a45ecce271d4edbd276b7ca2410e">gatewayIp</a>[4];
158 <a name="l00131"></a><a class="code" href="structibl_eth_boot_info__s.html#aa862217d7c7395cd662afa01504e34d0">00131</a> uint8 <a class="code" href="structibl_eth_boot_info__s.html#aa862217d7c7395cd662afa01504e34d0">netmask</a>[4];
159 <a name="l00132"></a><a class="code" href="structibl_eth_boot_info__s.html#a902455b75b0f4a69b58ea73990ae8246">00132</a> uint8 <a class="code" href="structibl_eth_boot_info__s.html#a902455b75b0f4a69b58ea73990ae8246">hwAddress</a>[6];
160 <a name="l00133"></a><a class="code" href="structibl_eth_boot_info__s.html#a1b37dd214d8c3d01ce90d23172842ce8">00133</a> char8 <a class="code" href="structibl_eth_boot_info__s.html#a1b37dd214d8c3d01ce90d23172842ce8">fileName</a>[64];
161 <a name="l00135"></a>00135 } <a class="code" href="structibl_eth_boot_info__s.html" title="This structure contains information used for tftp boot.">iblEthBootInfo_t</a>;
162 <a name="l00136"></a>00136
163 <a name="l00137"></a>00137
164 <a name="l00141"></a>00141 <span class="preprocessor">#define ibl_ETH_PORT_FROM_RBL -1 </span>
165 <a name="l00147"></a>00147 <span class="preprocessor">#define ibl_PORT_SWITCH_ALL -2 </span>
166 <a name="l00157"></a><a class="code" href="group__ibl_boot_formats.html#gae87b1d18a95fb3ffa8c62cf264e887b6">00157</a> <span class="preprocessor">#define ibl_BOOT_FORMAT_AUTO 0 </span>
167 <a name="l00158"></a><a class="code" href="group__ibl_boot_formats.html#ga04d44f44a43ce3d2a702dd979ca586b1">00158</a> <span class="preprocessor">#define ibl_BOOT_FORMAT_NAME 1 </span>
168 <a name="l00159"></a><a class="code" href="group__ibl_boot_formats.html#ga6d1e1c839dcf9e5679bec11a19be6334">00159</a> <span class="preprocessor">#define ibl_BOOT_FORMAT_BIS 2 </span>
169 <a name="l00160"></a><a class="code" href="group__ibl_boot_formats.html#ga2c3991bcb8cdbee651474385c114e469">00160</a> <span class="preprocessor">#define ibl_BOOT_FORMAT_COFF 3 </span>
170 <a name="l00161"></a><a class="code" href="group__ibl_boot_formats.html#ga9ed42438a6b1b15d1ef44f7d60200158">00161</a> <span class="preprocessor">#define ibl_BOOT_FORMAT_ELF 4 </span>
171 <a name="l00162"></a><a class="code" href="group__ibl_boot_formats.html#ga3d08523e93ee79b0231db3a2f158b226">00162</a> <span class="preprocessor">#define ibl_BOOT_FORMAT_BBLOB 5 </span>
172 <a name="l00163"></a><a class="code" href="group__ibl_boot_formats.html#gae48383e75105239fb298bd17f341adeb">00163</a> <span class="preprocessor">#define ibl_BOOT_FORMAT_BTBL 6 </span>
173 <a name="l00165"></a>00165 <span class="preprocessor"></span><span class="comment">/* @} */</span>
174 <a name="l00166"></a>00166
175 <a name="l00174"></a><a class="code" href="group__ibl_periph_priority.html#gae3e1dec0815792b59f2261782a2daae8">00174</a> <span class="preprocessor">#define ibl_LOWEST_PRIORITY 10 </span>
176 <a name="l00179"></a><a class="code" href="group__ibl_periph_priority.html#gaf17b6d0def34df5d975a77c901a7902c">00179</a> <span class="preprocessor">#define ibl_HIGHEST_PRIORITY 1 </span>
177 <a name="l00184"></a><a class="code" href="group__ibl_periph_priority.html#gaac14f77a1608296e5a405784933802db">00184</a> <span class="preprocessor">#define ibl_DEVICE_NOBOOT 20 </span>
178 <a name="l00186"></a>00186 <span class="preprocessor"></span><span class="comment">/* @} */</span>
179 <a name="l00187"></a>00187
180 <a name="l00188"></a>00188
181 <a name="l00196"></a><a class="code" href="structibl_emif3p1__s.html">00196</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structibl_emif3p1__s.html" title="Emif controller 3.1 configuration.">iblEmif3p1_s</a>
182 <a name="l00197"></a>00197 {
183 <a name="l00198"></a><a class="code" href="structibl_emif3p1__s.html#a0edc321b9a93e8810479fc2fa71f7320">00198</a> uint32 <a class="code" href="structibl_emif3p1__s.html#a0edc321b9a93e8810479fc2fa71f7320">sdcfg</a>;
184 <a name="l00199"></a><a class="code" href="structibl_emif3p1__s.html#a7018e3809d54d65af13bc41ca711b37f">00199</a> uint32 <a class="code" href="structibl_emif3p1__s.html#a7018e3809d54d65af13bc41ca711b37f">sdrfc</a>;
185 <a name="l00200"></a><a class="code" href="structibl_emif3p1__s.html#a030cc038632d28702f80f02405a9d49c">00200</a> uint32 <a class="code" href="structibl_emif3p1__s.html#a030cc038632d28702f80f02405a9d49c">sdtim1</a>;
186 <a name="l00201"></a><a class="code" href="structibl_emif3p1__s.html#a41dd0a970568b4cf0c30e4d4d9d75524">00201</a> uint32 <a class="code" href="structibl_emif3p1__s.html#a41dd0a970568b4cf0c30e4d4d9d75524">sdtim2</a>;
187 <a name="l00202"></a><a class="code" href="structibl_emif3p1__s.html#a315383eb3d274fa724fe4246e4ae76ef">00202</a> uint32 <a class="code" href="structibl_emif3p1__s.html#a315383eb3d274fa724fe4246e4ae76ef">dmcctl</a>;
188 <a name="l00204"></a>00204 } <a class="code" href="structibl_emif3p1__s.html" title="Emif controller 3.1 configuration.">iblEmif3p1_t</a>;
189 <a name="l00205"></a>00205
190 <a name="l00206"></a>00206
191 <a name="l00214"></a><a class="code" href="structibl_emif4p0__s.html">00214</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structibl_emif4p0__s.html" title="Emif controller 4.0 configuration.">iblEmif4p0_s</a>
192 <a name="l00215"></a>00215 {
193 <a name="l00216"></a><a class="code" href="structibl_emif4p0__s.html#afc32bc65ce2cf71dd3c6e30a239af47e">00216</a> uint32 <a class="code" href="structibl_emif4p0__s.html#afc32bc65ce2cf71dd3c6e30a239af47e">registerMask</a>;
194 <a name="l00217"></a><a class="code" href="structibl_emif4p0__s.html#a5faf82fad83d39e53de237a13d512220">00217</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a5faf82fad83d39e53de237a13d512220">sdRamConfig</a>;
195 <a name="l00218"></a><a class="code" href="structibl_emif4p0__s.html#a8a03c562a21ec31b59c17c72bcddb4ec">00218</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a8a03c562a21ec31b59c17c72bcddb4ec">sdRamConfig2</a>;
196 <a name="l00219"></a><a class="code" href="structibl_emif4p0__s.html#afc1d0b4e38a8ce09b240abb20bc60116">00219</a> uint32 <a class="code" href="structibl_emif4p0__s.html#afc1d0b4e38a8ce09b240abb20bc60116">sdRamRefreshCtl</a>;
197 <a name="l00220"></a><a class="code" href="structibl_emif4p0__s.html#ae330e2ac1c489536400107dabe14229a">00220</a> uint32 <a class="code" href="structibl_emif4p0__s.html#ae330e2ac1c489536400107dabe14229a">sdRamTiming1</a>;
198 <a name="l00221"></a><a class="code" href="structibl_emif4p0__s.html#ad34082e05339f2632e978dc42389a9e7">00221</a> uint32 <a class="code" href="structibl_emif4p0__s.html#ad34082e05339f2632e978dc42389a9e7">sdRamTiming2</a>;
199 <a name="l00222"></a><a class="code" href="structibl_emif4p0__s.html#a9bdbcede174de1bd60c4a2d06549d672">00222</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a9bdbcede174de1bd60c4a2d06549d672">sdRamTiming3</a>;
200 <a name="l00223"></a><a class="code" href="structibl_emif4p0__s.html#a9f0ea9fb2dde68278b226cf61db7d724">00223</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a9f0ea9fb2dde68278b226cf61db7d724">lpDdrNvmTiming</a>;
201 <a name="l00224"></a><a class="code" href="structibl_emif4p0__s.html#a8faa1c2c250fd8d50a1821f9f9a4c15f">00224</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a8faa1c2c250fd8d50a1821f9f9a4c15f">powerManageCtl</a>;
202 <a name="l00225"></a><a class="code" href="structibl_emif4p0__s.html#a6d5eb1a616936e57873af2a648819d2f">00225</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a6d5eb1a616936e57873af2a648819d2f">iODFTTestLogic</a>;
203 <a name="l00226"></a><a class="code" href="structibl_emif4p0__s.html#a779f0a58c5d1cc0e492f24b3f842ddd0">00226</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a779f0a58c5d1cc0e492f24b3f842ddd0">performCountCfg</a>;
204 <a name="l00227"></a><a class="code" href="structibl_emif4p0__s.html#af5754e8493066e1b66dea97161916a14">00227</a> uint32 <a class="code" href="structibl_emif4p0__s.html#af5754e8493066e1b66dea97161916a14">performCountMstRegSel</a>;
205 <a name="l00228"></a><a class="code" href="structibl_emif4p0__s.html#ae792d7050596145b63d50117d6220de3">00228</a> uint32 <a class="code" href="structibl_emif4p0__s.html#ae792d7050596145b63d50117d6220de3">readIdleCtl</a>;
206 <a name="l00229"></a><a class="code" href="structibl_emif4p0__s.html#aa6f4e601d939f54af799f78571f24cbc">00229</a> uint32 <a class="code" href="structibl_emif4p0__s.html#aa6f4e601d939f54af799f78571f24cbc">sysVbusmIntEnSet</a>;
207 <a name="l00230"></a><a class="code" href="structibl_emif4p0__s.html#a24b8b8f644cab72d004375d7ef597322">00230</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a24b8b8f644cab72d004375d7ef597322">sdRamOutImpdedCalCfg</a>;
208 <a name="l00231"></a><a class="code" href="structibl_emif4p0__s.html#ac27fa6e3bf375487950e5a3b4a429ba7">00231</a> uint32 <a class="code" href="structibl_emif4p0__s.html#ac27fa6e3bf375487950e5a3b4a429ba7">tempAlterCfg</a>;
209 <a name="l00232"></a><a class="code" href="structibl_emif4p0__s.html#a959f7a69fe3191f79cb200263067d3e9">00232</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a959f7a69fe3191f79cb200263067d3e9">ddrPhyCtl1</a>;
210 <a name="l00233"></a><a class="code" href="structibl_emif4p0__s.html#abc295d552a398f31e636f2dbb9ce180c">00233</a> uint32 <a class="code" href="structibl_emif4p0__s.html#abc295d552a398f31e636f2dbb9ce180c">ddrPhyCtl2</a>;
211 <a name="l00234"></a><a class="code" href="structibl_emif4p0__s.html#aeee9d593ff0901ec99ca9e7ebb3fa2f6">00234</a> uint32 <a class="code" href="structibl_emif4p0__s.html#aeee9d593ff0901ec99ca9e7ebb3fa2f6">priClassSvceMap</a>;
212 <a name="l00235"></a><a class="code" href="structibl_emif4p0__s.html#a8ed6f7abab17ae59bf2a1cf5169fb3e8">00235</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a8ed6f7abab17ae59bf2a1cf5169fb3e8">mstId2ClsSvce1Map</a>;
213 <a name="l00236"></a><a class="code" href="structibl_emif4p0__s.html#a19116d15b3c25e891b85134f5298af17">00236</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a19116d15b3c25e891b85134f5298af17">mstId2ClsSvce2Map</a>;
214 <a name="l00237"></a><a class="code" href="structibl_emif4p0__s.html#a4cc76fb6a01e74434bad174b82485489">00237</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a4cc76fb6a01e74434bad174b82485489">eccCtl</a>;
215 <a name="l00238"></a><a class="code" href="structibl_emif4p0__s.html#a3416b063ce5e86cf0b99752baed7e978">00238</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a3416b063ce5e86cf0b99752baed7e978">eccRange1</a>;
216 <a name="l00239"></a><a class="code" href="structibl_emif4p0__s.html#a8c9d5f1c8ebd1e746a05915b80e8a0c2">00239</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a8c9d5f1c8ebd1e746a05915b80e8a0c2">eccRange2</a>;
217 <a name="l00240"></a><a class="code" href="structibl_emif4p0__s.html#a512ad045f76a8a93b5bdad6a80cd2454">00240</a> uint32 <a class="code" href="structibl_emif4p0__s.html#a512ad045f76a8a93b5bdad6a80cd2454">rdWrtExcThresh</a>;
218 <a name="l00242"></a>00242 } <a class="code" href="structibl_emif4p0__s.html" title="Emif controller 4.0 configuration.">iblEmif4p0_t</a>;
219 <a name="l00243"></a>00243
220 <a name="l00244"></a>00244
221 <a name="l00252"></a>00252 <span class="preprocessor">#define ibl_EMIF4_ENABLE_sdRamConfig (1 << 0)</span>
222 <a name="l00253"></a>00253 <span class="preprocessor"></span>
223 <a name="l00255"></a>00255 <span class="preprocessor">#define ibl_EMIF4_ENABLE_sdRamConfig2 (1 << 1)</span>
224 <a name="l00256"></a>00256 <span class="preprocessor"></span>
225 <a name="l00258"></a>00258 <span class="preprocessor">#define ibl_EMIF4_ENABLE_sdRamRefreshCtl (1 << 2)</span>
226 <a name="l00259"></a>00259 <span class="preprocessor"></span>
227 <a name="l00261"></a>00261 <span class="preprocessor">#define ibl_EMIF4_ENABLE_sdRamTiming1 (1 << 3)</span>
228 <a name="l00262"></a>00262 <span class="preprocessor"></span>
229 <a name="l00264"></a>00264 <span class="preprocessor">#define ibl_EMIF4_ENABLE_sdRamTiming2 (1 << 4)</span>
230 <a name="l00265"></a>00265 <span class="preprocessor"></span>
231 <a name="l00267"></a>00267 <span class="preprocessor">#define ibl_EMIF4_ENABLE_sdRamTiming3 (1 << 5)</span>
232 <a name="l00268"></a>00268 <span class="preprocessor"></span>
233 <a name="l00270"></a>00270 <span class="preprocessor">#define ibl_EMIF4_ENABLE_lpDdrNvmTiming (1 << 6)</span>
234 <a name="l00271"></a>00271 <span class="preprocessor"></span>
235 <a name="l00273"></a>00273 <span class="preprocessor">#define ibl_EMIF4_ENABLE_powerManageCtl (1 << 7)</span>
236 <a name="l00274"></a>00274 <span class="preprocessor"></span>
237 <a name="l00276"></a>00276 <span class="preprocessor">#define ibl_EMIF4_ENABLE_iODFTTestLogic (1 << 8)</span>
238 <a name="l00277"></a>00277 <span class="preprocessor"></span>
239 <a name="l00279"></a>00279 <span class="preprocessor">#define ibl_EMIF4_ENABLE_performCountCfg (1 << 9)</span>
240 <a name="l00280"></a>00280 <span class="preprocessor"></span>
241 <a name="l00282"></a>00282 <span class="preprocessor">#define ibl_EMIF4_ENABLE_performCountMstRegSel (1 << 10)</span>
242 <a name="l00283"></a>00283 <span class="preprocessor"></span>
243 <a name="l00285"></a>00285 <span class="preprocessor">#define ibl_EMIF4_ENABLE_readIdleCtl (1 << 11)</span>
244 <a name="l00286"></a>00286 <span class="preprocessor"></span>
245 <a name="l00288"></a>00288 <span class="preprocessor">#define ibl_EMIF4_ENABLE_sysVbusmIntEnSet (1 << 12)</span>
246 <a name="l00289"></a>00289 <span class="preprocessor"></span>
247 <a name="l00291"></a>00291 <span class="preprocessor">#define ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg (1 << 13)</span>
248 <a name="l00292"></a>00292 <span class="preprocessor"></span>
249 <a name="l00294"></a>00294 <span class="preprocessor">#define ibl_EMIF4_ENABLE_tempAlterCfg (1 << 14)</span>
250 <a name="l00295"></a>00295 <span class="preprocessor"></span>
251 <a name="l00297"></a>00297 <span class="preprocessor">#define ibl_EMIF4_ENABLE_ddrPhyCtl1 (1 << 15)</span>
252 <a name="l00298"></a>00298 <span class="preprocessor"></span>
253 <a name="l00300"></a>00300 <span class="preprocessor">#define ibl_EMIF4_ENABLE_ddrPhyCtl2 (1 << 16)</span>
254 <a name="l00301"></a>00301 <span class="preprocessor"></span>
255 <a name="l00303"></a>00303 <span class="preprocessor">#define ibl_EMIF4_ENABLE_priClassSvceMap (1 << 17)</span>
256 <a name="l00304"></a>00304 <span class="preprocessor"></span>
257 <a name="l00306"></a>00306 <span class="preprocessor">#define ibl_EMIF4_ENABLE_mstId2ClsSvce1Map (1 << 18)</span>
258 <a name="l00307"></a>00307 <span class="preprocessor"></span>
259 <a name="l00309"></a>00309 <span class="preprocessor">#define ibl_EMIF4_ENABLE_mstId2ClsSvce2Map (1 << 11)</span>
260 <a name="l00310"></a>00310 <span class="preprocessor"></span>
261 <a name="l00312"></a>00312 <span class="preprocessor">#define ibl_EMIF4_ENABLE_eccCtl (1 << 19)</span>
262 <a name="l00313"></a>00313 <span class="preprocessor"></span>
263 <a name="l00315"></a>00315 <span class="preprocessor">#define ibl_EMIF4_ENABLE_eccRange1 (1 << 20)</span>
264 <a name="l00316"></a>00316 <span class="preprocessor"></span>
265 <a name="l00318"></a>00318 <span class="preprocessor">#define ibl_EMIF4_ENABLE_eccRange2 (1 << 21)</span>
266 <a name="l00319"></a>00319 <span class="preprocessor"></span>
267 <a name="l00321"></a>00321 <span class="preprocessor">#define ibl_EMIF4_ENABLE_rdWrtExcThresh (1 << 22)</span>
268 <a name="l00322"></a>00322 <span class="preprocessor"></span>
269 <a name="l00324"></a>00324 <span class="preprocessor">#define ibl_BOOT_EMIF4_ENABLE_ALL 0x007fffff</span>
270 <a name="l00325"></a>00325 <span class="preprocessor"></span>
271 <a name="l00326"></a>00326 <span class="comment">/* @} */</span>
272 <a name="l00327"></a>00327
273 <a name="l00328"></a>00328
274 <a name="l00336"></a>00336 <span class="preprocessor">#define ibl_EMIF_TYPE_31 31</span>
275 <a name="l00337"></a>00337 <span class="preprocessor"></span>
276 <a name="l00339"></a>00339 <span class="preprocessor">#define ibl_EMIF_TYPE_40 40</span>
277 <a name="l00340"></a>00340 <span class="preprocessor"></span>
278 <a name="l00341"></a>00341 <span class="comment">/* @} */</span>
279 <a name="l00342"></a>00342
280 <a name="l00351"></a><a class="code" href="structidbl_ddr__s.html">00351</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structidbl_ddr__s.html" title="This structure is used to configure the DDR interface.">idblDdr_s</a>
281 <a name="l00352"></a>00352 {
282 <a name="l00353"></a><a class="code" href="structidbl_ddr__s.html#a07d4d9201bef8829681434aadf30acd1">00353</a> <span class="keywordtype">bool</span> <a class="code" href="structidbl_ddr__s.html#a07d4d9201bef8829681434aadf30acd1">configDdr</a>;
283 <a name="l00355"></a>00355 <span class="keyword">union </span>{
284 <a name="l00356"></a>00356
285 <a name="l00357"></a><a class="code" href="structidbl_ddr__s.html#afe71b284da89213e10c5ca8951a11ad9">00357</a> <a class="code" href="structibl_emif3p1__s.html" title="Emif controller 3.1 configuration.">iblEmif3p1_t</a> <a class="code" href="structidbl_ddr__s.html#afe71b284da89213e10c5ca8951a11ad9">emif3p1</a>;
286 <a name="l00358"></a><a class="code" href="structidbl_ddr__s.html#a61d9e41068292179f92195b4d21b6f4b">00358</a> <a class="code" href="structibl_emif4p0__s.html" title="Emif controller 4.0 configuration.">iblEmif4p0_t</a> <a class="code" href="structidbl_ddr__s.html#a61d9e41068292179f92195b4d21b6f4b">emif4p0</a>;
287 <a name="l00359"></a>00359 } uEmif;
288 <a name="l00360"></a>00360
289 <a name="l00361"></a>00361 } <a class="code" href="structidbl_ddr__s.html" title="This structure is used to configure the DDR interface.">iblDdr_t</a>;
290 <a name="l00362"></a>00362
291 <a name="l00372"></a><a class="code" href="structibl_bin_blob__s.html">00372</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structibl_bin_blob__s.html" title="This structure is used to identify binary blob load parameters.">iblBinBlob_s</a>
292 <a name="l00373"></a>00373 {
293 <a name="l00374"></a><a class="code" href="structibl_bin_blob__s.html#a462abcbede1446b392febe5309351135">00374</a> uint32 <a class="code" href="structibl_bin_blob__s.html#a462abcbede1446b392febe5309351135">startAddress</a>;
294 <a name="l00375"></a><a class="code" href="structibl_bin_blob__s.html#ac30b853b6e92862495fa25a9740b9d54">00375</a> uint32 <a class="code" href="structibl_bin_blob__s.html#ac30b853b6e92862495fa25a9740b9d54">sizeBytes</a>;
295 <a name="l00376"></a><a class="code" href="structibl_bin_blob__s.html#acfaa6331e5c9c22012ec5babaa284c27">00376</a> uint32 <a class="code" href="structibl_bin_blob__s.html#acfaa6331e5c9c22012ec5babaa284c27">branchAddress</a>;
296 <a name="l00378"></a>00378 } <a class="code" href="structibl_bin_blob__s.html" title="This structure is used to identify binary blob load parameters.">iblBinBlob_t</a>;
297 <a name="l00379"></a>00379
298 <a name="l00387"></a><a class="code" href="structibl_eth__s.html">00387</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structibl_eth__s.html" title="This structure is used to control the operation of the ibl ethernet boot.">iblEth_s</a>
299 <a name="l00388"></a>00388 {
300 <a name="l00389"></a><a class="code" href="structibl_eth__s.html#a80d22490b07330930d3e740d2f1533d4">00389</a> <span class="keywordtype">bool</span> <a class="code" href="structibl_eth__s.html#a80d22490b07330930d3e740d2f1533d4">doBootp</a>;
301 <a name="l00391"></a><a class="code" href="structibl_eth__s.html#a1786512099a59e491b4c6b7c87836dba">00391</a> <span class="keywordtype">bool</span> <a class="code" href="structibl_eth__s.html#a1786512099a59e491b4c6b7c87836dba">useBootpServerIp</a>;
302 <a name="l00393"></a><a class="code" href="structibl_eth__s.html#af90bc642d0a3482e357e398ec521056a">00393</a> <span class="keywordtype">bool</span> <a class="code" href="structibl_eth__s.html#af90bc642d0a3482e357e398ec521056a">useBootpFileName</a>;
303 <a name="l00395"></a><a class="code" href="structibl_eth__s.html#acf88dc7da49ef21e125e0e4a2dec29f6">00395</a> int32 <a class="code" href="structibl_eth__s.html#acf88dc7da49ef21e125e0e4a2dec29f6">bootFormat</a>;
304 <a name="l00397"></a><a class="code" href="structibl_eth__s.html#ab0d6d7dd82f370c9ef51aec658fa3eb2">00397</a> <a class="code" href="structibl_bin_blob__s.html" title="This structure is used to identify binary blob load parameters.">iblBinBlob_t</a> <a class="code" href="structibl_eth__s.html#ab0d6d7dd82f370c9ef51aec658fa3eb2">blob</a>;
305 <a name="l00399"></a><a class="code" href="structibl_eth__s.html#abbde53672bb8b243bc52fb4b82780a35">00399</a> <a class="code" href="structibl_eth_boot_info__s.html" title="This structure contains information used for tftp boot.">iblEthBootInfo_t</a> <a class="code" href="structibl_eth__s.html#abbde53672bb8b243bc52fb4b82780a35">ethInfo</a>;
306 <a name="l00401"></a>00401 } <a class="code" href="structibl_eth__s.html" title="This structure is used to control the operation of the ibl ethernet boot.">iblEth_t</a>;
307 <a name="l00402"></a>00402
308 <a name="l00403"></a>00403
309 <a name="l00411"></a><a class="code" href="structibl_sgmii__s.html">00411</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structibl_sgmii__s.html" title="This structure is used to control the operation of the ibl sgmii ports.">iblSgmii_s</a>
310 <a name="l00412"></a>00412 {
311 <a name="l00413"></a><a class="code" href="structibl_sgmii__s.html#a1d98807b7d49a87fb03747ffc839bb14">00413</a> <span class="keywordtype">bool</span> <a class="code" href="structibl_sgmii__s.html#a1d98807b7d49a87fb03747ffc839bb14">configure</a>;
312 <a name="l00414"></a><a class="code" href="structibl_sgmii__s.html#a67f49382af670b3270cef473252145df">00414</a> uint32 <a class="code" href="structibl_sgmii__s.html#a67f49382af670b3270cef473252145df">adviseAbility</a>;
313 <a name="l00415"></a><a class="code" href="structibl_sgmii__s.html#a60792957cac883fb031fa40acf6953a9">00415</a> uint32 <a class="code" href="structibl_sgmii__s.html#a60792957cac883fb031fa40acf6953a9">control</a>;
314 <a name="l00416"></a><a class="code" href="structibl_sgmii__s.html#a70944556b492281822c0a56e46bd1fac">00416</a> uint32 <a class="code" href="structibl_sgmii__s.html#a70944556b492281822c0a56e46bd1fac">txConfig</a>;
315 <a name="l00417"></a><a class="code" href="structibl_sgmii__s.html#ae0c294b13d5df2b000dc947ef511b0cc">00417</a> uint32 <a class="code" href="structibl_sgmii__s.html#ae0c294b13d5df2b000dc947ef511b0cc">rxConfig</a>;
316 <a name="l00418"></a><a class="code" href="structibl_sgmii__s.html#ad7f8697ce9b43ff42f3b435e29ec3c83">00418</a> uint32 <a class="code" href="structibl_sgmii__s.html#ad7f8697ce9b43ff42f3b435e29ec3c83">auxConfig</a>;
317 <a name="l00420"></a>00420 } <a class="code" href="structibl_sgmii__s.html" title="This structure is used to control the operation of the ibl sgmii ports.">iblSgmii_t</a>;
318 <a name="l00421"></a>00421
319 <a name="l00422"></a>00422
320 <a name="l00426"></a>00426 <span class="preprocessor">#define ibl_N_ETH_PORTS 2 </span>
321 <a name="l00431"></a>00431 <span class="preprocessor">#define ibl_N_MDIO_CFGS 16 </span>
322 <a name="l00448"></a><a class="code" href="structibl_mdio__s.html">00448</a> <span class="preprocessor">typedef struct iblMdio_s</span>
323 <a name="l00449"></a>00449 <span class="preprocessor"></span>{
324 <a name="l00450"></a><a class="code" href="structibl_mdio__s.html#ad76919c048aaa10bae0a1696f38ed090">00450</a> int16 <a class="code" href="structibl_mdio__s.html#ad76919c048aaa10bae0a1696f38ed090">nMdioOps</a>;
325 <a name="l00451"></a><a class="code" href="structibl_mdio__s.html#afbf1e6a9ca8f512e5cdc69cd5f9d553c">00451</a> uint16 <a class="code" href="structibl_mdio__s.html#afbf1e6a9ca8f512e5cdc69cd5f9d553c">mdioClkDiv</a>;
326 <a name="l00453"></a><a class="code" href="structibl_mdio__s.html#ad237aec703f1f7c798e50332bf816abd">00453</a> uint32 <a class="code" href="structibl_mdio__s.html#ad237aec703f1f7c798e50332bf816abd">interDelay</a>;
327 <a name="l00455"></a>00455 uint32 mdio[ibl_N_MDIO_CFGS]; <span class="comment">/* The MDIO transactions */</span>
328 <a name="l00456"></a>00456
329 <a name="l00457"></a>00457 } <a class="code" href="structibl_mdio__s.html" title="This structure is used to configure phys through the mdio interface.">iblMdio_t</a>;
330 <a name="l00458"></a>00458
331 <a name="l00462"></a>00462 <span class="preprocessor">#define ibl_N_ECC_BYTES 10 </span>
332 <a name="l00467"></a>00467 <span class="preprocessor">#define ibl_N_BAD_BLOCK_PAGE 2 </span>
333 <a name="l00473"></a><a class="code" href="structnand_dev_info__s.html">00473</a> <span class="preprocessor">typedef struct nandDevInfo_s</span>
334 <a name="l00474"></a>00474 <span class="preprocessor"></span>{
335 <a name="l00475"></a><a class="code" href="structnand_dev_info__s.html#a449de62be58d2d13dd866436ec8edf18">00475</a> uint32 <a class="code" href="structnand_dev_info__s.html#a449de62be58d2d13dd866436ec8edf18">busWidthBits</a>;
336 <a name="l00476"></a><a class="code" href="structnand_dev_info__s.html#a81e7a7bcce5dff5392f7e2a61e771abd">00476</a> uint32 <a class="code" href="structnand_dev_info__s.html#a81e7a7bcce5dff5392f7e2a61e771abd">pageSizeBytes</a>;
337 <a name="l00477"></a><a class="code" href="structnand_dev_info__s.html#a81e743309414ef617d4b27a6537142f3">00477</a> uint32 <a class="code" href="structnand_dev_info__s.html#a81e743309414ef617d4b27a6537142f3">pageEccBytes</a>;
338 <a name="l00478"></a><a class="code" href="structnand_dev_info__s.html#a234b9fa6c1b59ea71dcde18e2d3fec47">00478</a> uint32 <a class="code" href="structnand_dev_info__s.html#a234b9fa6c1b59ea71dcde18e2d3fec47">pagesPerBlock</a>;
339 <a name="l00479"></a><a class="code" href="structnand_dev_info__s.html#ad1facaca2843ea22c27df03462d1eb08">00479</a> uint32 <a class="code" href="structnand_dev_info__s.html#ad1facaca2843ea22c27df03462d1eb08">totalBlocks</a>;
340 <a name="l00481"></a><a class="code" href="structnand_dev_info__s.html#ae8b1cc85105db42c80d796c45b236766">00481</a> uint32 <a class="code" href="structnand_dev_info__s.html#ae8b1cc85105db42c80d796c45b236766">addressBytes</a>;
341 <a name="l00482"></a><a class="code" href="structnand_dev_info__s.html#af684ebd7127978006da4f66fd4b1bf9a">00482</a> <span class="keywordtype">bool</span> <a class="code" href="structnand_dev_info__s.html#af684ebd7127978006da4f66fd4b1bf9a">lsbFirst</a>;
342 <a name="l00483"></a><a class="code" href="structnand_dev_info__s.html#aab09413a8b0f8ffc3418e7207d27719f">00483</a> uint32 <a class="code" href="structnand_dev_info__s.html#aab09413a8b0f8ffc3418e7207d27719f">blockOffset</a>;
343 <a name="l00484"></a><a class="code" href="structnand_dev_info__s.html#aacadecb0707f793ef4c50f3f6e932616">00484</a> uint32 <a class="code" href="structnand_dev_info__s.html#aacadecb0707f793ef4c50f3f6e932616">pageOffset</a>;
344 <a name="l00485"></a><a class="code" href="structnand_dev_info__s.html#a6a3d800d293228b57d6661d60705a5d3">00485</a> uint32 <a class="code" href="structnand_dev_info__s.html#a6a3d800d293228b57d6661d60705a5d3">columnOffset</a>;
345 <a name="l00487"></a>00487 uint8 eccBytesIdx[ibl_N_ECC_BYTES];
346 <a name="l00489"></a>00489 uint8 badBlkMarkIdx[ibl_N_BAD_BLOCK_PAGE];
347 <a name="l00492"></a><a class="code" href="structnand_dev_info__s.html#a9377cc69e9f0396c71e39d26cd63d56f">00492</a> uint8 <a class="code" href="structnand_dev_info__s.html#a9377cc69e9f0396c71e39d26cd63d56f">resetCommand</a>;
348 <a name="l00493"></a><a class="code" href="structnand_dev_info__s.html#a2f8b62682044471f3c4613d0f9c43627">00493</a> uint8 <a class="code" href="structnand_dev_info__s.html#a2f8b62682044471f3c4613d0f9c43627">readCommandPre</a>;
349 <a name="l00494"></a><a class="code" href="structnand_dev_info__s.html#a0923ed4675a46cf4e5a8f78c10a324d7">00494</a> uint8 <a class="code" href="structnand_dev_info__s.html#a0923ed4675a46cf4e5a8f78c10a324d7">readCommandPost</a>;
350 <a name="l00495"></a><a class="code" href="structnand_dev_info__s.html#a321b34578736ddb47fbb48c655a4df27">00495</a> <span class="keywordtype">bool</span> <a class="code" href="structnand_dev_info__s.html#a321b34578736ddb47fbb48c655a4df27">postCommand</a>;
351 <a name="l00497"></a>00497 } <a class="code" href="structnand_dev_info__s.html" title="This structure defines the physical parameters of the NAND device.">nandDevInfo_t</a>;
352 <a name="l00498"></a>00498
353 <a name="l00499"></a>00499
354 <a name="l00503"></a>00503 <span class="preprocessor">#define ibl_N_ENDIANS 2 </span>
355 <a name="l00505"></a>00505 <span class="preprocessor">#define ibl_ENDIAN_BIG 0 </span>
356 <a name="l00506"></a>00506 <span class="preprocessor">#define ibl_ENDIAN_LITTLE 1 </span>
357 <a name="l00511"></a>00511 <span class="preprocessor">#define ibl_N_IMAGES 2 </span>
358 <a name="l00518"></a><a class="code" href="structibl_nand__s.html">00518</a> <span class="preprocessor">typedef struct iblNand_s</span>
359 <a name="l00519"></a>00519 <span class="preprocessor"></span>{
360 <a name="l00520"></a>00520
361 <a name="l00521"></a><a class="code" href="structibl_nand__s.html#acf88dc7da49ef21e125e0e4a2dec29f6">00521</a> int32 <a class="code" href="structibl_nand__s.html#acf88dc7da49ef21e125e0e4a2dec29f6">bootFormat</a>;
362 <a name="l00522"></a><a class="code" href="structibl_nand__s.html#a800723f95dd58a57773e3b2f8ef79537">00522</a> uint32 bootAddress[ibl_N_ENDIANS][ibl_N_IMAGES];
363 <a name="l00523"></a><a class="code" href="structibl_nand__s.html#a390a11baf791b8f363d7b950730d2a08">00523</a> int32 <a class="code" href="structibl_nand__s.html#a390a11baf791b8f363d7b950730d2a08">interface</a>;
364 <a name="l00524"></a><a class="code" href="structibl_nand__s.html#a78d321ead780bdcb9fd3173b134318f2">00524</a> <a class="code" href="structibl_bin_blob__s.html" title="This structure is used to identify binary blob load parameters.">iblBinBlob_t</a> blob[ibl_N_ENDIANS][ibl_N_IMAGES];
365 <a name="l00527"></a>00527 <a class="code" href="structnand_dev_info__s.html" title="This structure defines the physical parameters of the NAND device.">nandDevInfo_t</a> nandInfo;
366 <a name="l00529"></a>00529 } <a class="code" href="structibl_nand__s.html" title="This structure is used to control the operation of the NAND boot.">iblNand_t</a>;
367 <a name="l00530"></a>00530
368 <a name="l00535"></a><a class="code" href="structibl_nor__s.html">00535</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structibl_nor__s.html" title="Nor boot configuration.">iblNor_s</a>
369 <a name="l00536"></a>00536 {
370 <a name="l00537"></a><a class="code" href="structibl_nor__s.html#acf88dc7da49ef21e125e0e4a2dec29f6">00537</a> int32 <a class="code" href="structibl_nor__s.html#acf88dc7da49ef21e125e0e4a2dec29f6">bootFormat</a>;
371 <a name="l00538"></a><a class="code" href="structibl_nor__s.html#a800723f95dd58a57773e3b2f8ef79537">00538</a> uint32 <a class="code" href="structibl_nor__s.html#a800723f95dd58a57773e3b2f8ef79537">bootAddress</a>[ibl_N_ENDIANS][ibl_N_IMAGES];
372 <a name="l00539"></a><a class="code" href="structibl_nor__s.html#a390a11baf791b8f363d7b950730d2a08">00539</a> int32 <a class="code" href="structibl_nor__s.html#a390a11baf791b8f363d7b950730d2a08">interface</a>;
373 <a name="l00540"></a><a class="code" href="structibl_nor__s.html#a78d321ead780bdcb9fd3173b134318f2">00540</a> <a class="code" href="structibl_bin_blob__s.html" title="This structure is used to identify binary blob load parameters.">iblBinBlob_t</a> <a class="code" href="structibl_nor__s.html#a78d321ead780bdcb9fd3173b134318f2">blob</a>[ibl_N_ENDIANS][ibl_N_IMAGES];
374 <a name="l00542"></a>00542 } <a class="code" href="structibl_nor__s.html" title="Nor boot configuration.">iblNor_t</a>;
375 <a name="l00543"></a>00543
376 <a name="l00544"></a>00544 <span class="keyword">extern</span> uint32 iblEndianIdx;
377 <a name="l00545"></a>00545 <span class="keyword">extern</span> uint32 iblImageIdx;
378 <a name="l00546"></a>00546
379 <a name="l00556"></a>00556 <span class="preprocessor">#define ibl_PMEM_IF_GPIO 0</span>
380 <a name="l00557"></a>00557 <span class="preprocessor"></span>
381 <a name="l00559"></a>00559 <span class="preprocessor">#define ibl_PMEM_IF_CHIPSEL_2 2 </span><span class="comment">/* EMIF interface using chip select 2, no wait enabled */</span>
382 <a name="l00560"></a>00560
383 <a name="l00562"></a>00562 <span class="preprocessor">#define ibl_PMEM_IF_CHIPSEL_3 3 </span><span class="comment">/* EMIF interface using chip select 3, no wait enabled */</span>
384 <a name="l00563"></a>00563
385 <a name="l00565"></a>00565 <span class="preprocessor">#define ibl_PMEM_IF_CHIPSEL_4 4 </span><span class="comment">/* EMIF interface using chip select 4 */</span>
386 <a name="l00566"></a>00566
387 <a name="l00568"></a>00568 <span class="preprocessor">#define ibl_PMEM_IF_CHIPSEL_5 5 </span><span class="comment">/* EMIF interface using chip select 5 */</span>
388 <a name="l00569"></a>00569
389 <a name="l00571"></a>00571 <span class="preprocessor">#define ibl_PMEM_IF_SPI 100 </span><span class="comment">/* Interface through SPI */</span>
390 <a name="l00572"></a>00572
391 <a name="l00573"></a>00573 <span class="comment">/* @} */</span>
392 <a name="l00574"></a>00574
393 <a name="l00575"></a>00575
394 <a name="l00580"></a><a class="code" href="structibl_emif__s.html">00580</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structibl_emif__s.html" title="EMIF (nand/nor) configuration.">iblEmif_s</a> {
395 <a name="l00581"></a>00581
396 <a name="l00582"></a><a class="code" href="structibl_emif__s.html#af2a0b74cd977467c405abc3fd5d428bd">00582</a> int16 <a class="code" href="structibl_emif__s.html#af2a0b74cd977467c405abc3fd5d428bd">csSpace</a>;
397 <a name="l00583"></a><a class="code" href="structibl_emif__s.html#a71676eed3a073ea5e5322b07cab37df5">00583</a> int16 <a class="code" href="structibl_emif__s.html#a71676eed3a073ea5e5322b07cab37df5">busWidth</a>;
398 <a name="l00584"></a><a class="code" href="structibl_emif__s.html#a89bdf287845679059d2c37aa142cb049">00584</a> <span class="keywordtype">bool</span> <a class="code" href="structibl_emif__s.html#a89bdf287845679059d2c37aa142cb049">waitEnable</a>;
399 <a name="l00586"></a>00586 } <a class="code" href="structibl_emif__s.html" title="EMIF (nand/nor) configuration.">iblEmif_t</a>;
400 <a name="l00587"></a>00587
401 <a name="l00592"></a>00592 <span class="preprocessor">#define ibl_MAX_EMIF_PMEM 2</span>
402 <a name="l00593"></a>00593 <span class="preprocessor"></span>
403 <a name="l00594"></a>00594
404 <a name="l00599"></a><a class="code" href="structibl_spi__s.html">00599</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structibl_spi__s.html" title="SPI configuration used for either NOR or NAND.">iblSpi_s</a>
405 <a name="l00600"></a>00600 {
406 <a name="l00601"></a><a class="code" href="structibl_spi__s.html#a80f96c7a513095dbffe1f940da88004e">00601</a> int16 <a class="code" href="structibl_spi__s.html#a80f96c7a513095dbffe1f940da88004e">addrWidth</a>;
407 <a name="l00602"></a><a class="code" href="structibl_spi__s.html#a65024cf03e1cc8767a84765c66bcb3ee">00602</a> int16 <a class="code" href="structibl_spi__s.html#a65024cf03e1cc8767a84765c66bcb3ee">nPins</a>;
408 <a name="l00603"></a><a class="code" href="structibl_spi__s.html#a7b9d350f528bcd26b176c6b06cf76d54">00603</a> int16 <a class="code" href="structibl_spi__s.html#a7b9d350f528bcd26b176c6b06cf76d54">mode</a>;
409 <a name="l00604"></a><a class="code" href="structibl_spi__s.html#a1ade01ece3395902af4b6e3aa83cb0eb">00604</a> int16 <a class="code" href="structibl_spi__s.html#a1ade01ece3395902af4b6e3aa83cb0eb">csel</a>;
410 <a name="l00605"></a><a class="code" href="structibl_spi__s.html#a3f73343d4a1839e207bc7e04539619e3">00605</a> uint16 <a class="code" href="structibl_spi__s.html#a3f73343d4a1839e207bc7e04539619e3">c2tdelay</a>;
411 <a name="l00606"></a><a class="code" href="structibl_spi__s.html#ae1562cf105fc689a17119c45f550694a">00606</a> uint16 <a class="code" href="structibl_spi__s.html#ae1562cf105fc689a17119c45f550694a">busFreqMHz</a>;
412 <a name="l00608"></a>00608 } <a class="code" href="structibl_spi__s.html" title="SPI configuration used for either NOR or NAND.">iblSpi_t</a>;
413 <a name="l00609"></a>00609
414 <a name="l00610"></a>00610
415 <a name="l00611"></a>00611
416 <a name="l00619"></a><a class="code" href="structibl_pll__s.html">00619</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structibl_pll__s.html" title="This structure is used to control the programming of the device PLL.">iblPll_s</a> {
417 <a name="l00620"></a>00620
418 <a name="l00621"></a><a class="code" href="structibl_pll__s.html#a7446d80d89daa09456ca7685b1b104e6">00621</a> <span class="keywordtype">bool</span> <a class="code" href="structibl_pll__s.html#a7446d80d89daa09456ca7685b1b104e6">doEnable</a>;
419 <a name="l00623"></a><a class="code" href="structibl_pll__s.html#adf4ca3e1cd8b286dad9a88c76e5dc4da">00623</a> Uint32 <a class="code" href="structibl_pll__s.html#adf4ca3e1cd8b286dad9a88c76e5dc4da">prediv</a>;
420 <a name="l00624"></a><a class="code" href="structibl_pll__s.html#a9a7e8ab6815604c829742a7f6e53d31d">00624</a> Uint32 <a class="code" href="structibl_pll__s.html#a9a7e8ab6815604c829742a7f6e53d31d">mult</a>;
421 <a name="l00625"></a><a class="code" href="structibl_pll__s.html#acf2781399cb2688871060589af85d10b">00625</a> Uint32 <a class="code" href="structibl_pll__s.html#acf2781399cb2688871060589af85d10b">postdiv</a>;
422 <a name="l00627"></a><a class="code" href="structibl_pll__s.html#a9e734abe3074f9c749556458ff3ef7bc">00627</a> Uint32 <a class="code" href="structibl_pll__s.html#a9e734abe3074f9c749556458ff3ef7bc">pllOutFreqMhz</a>;
423 <a name="l00629"></a>00629 } <a class="code" href="structibl_pll__s.html" title="This structure is used to control the programming of the device PLL.">iblPll_t</a>;
424 <a name="l00630"></a>00630
425 <a name="l00631"></a>00631
426 <a name="l00640"></a><a class="code" href="group__ibl_pll_num.html#gad8f099a1896943d3b201b2d01d7786e0">00640</a> <span class="preprocessor">#define ibl_MAIN_PLL 0 </span>
427 <a name="l00645"></a><a class="code" href="group__ibl_pll_num.html#gaab8d598386c9a86afea9b21cdc48f716">00645</a> <span class="preprocessor">#define ibl_DDR_PLL 1 </span>
428 <a name="l00650"></a><a class="code" href="group__ibl_pll_num.html#ga393560f66801d799608908911bf45db3">00650</a> <span class="preprocessor">#define ibl_NET_PLL 2 </span>
429 <a name="l00658"></a><a class="code" href="group__ibl_pll_num.html#ga64571eeaa73441952ab8403655bea805">00658</a> <span class="preprocessor">#define ibl_N_PLL_CFGS (ibl_NET_PLL + 1)</span>
430 <a name="l00659"></a>00659 <span class="preprocessor"></span>
431 <a name="l00660"></a>00660 <span class="comment">/* @} */</span>
432 <a name="l00661"></a>00661
433 <a name="l00662"></a>00662
434 <a name="l00671"></a><a class="code" href="structibl_boot__s.html">00671</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structibl_boot__s.html">iblBoot_s</a>
435 <a name="l00672"></a>00672 {
436 <a name="l00673"></a>00673
437 <a name="l00674"></a><a class="code" href="structibl_boot__s.html#a11810afa5a6d9f6a66152894b84cd962">00674</a> int32 <a class="code" href="structibl_boot__s.html#a11810afa5a6d9f6a66152894b84cd962">bootMode</a>;
438 <a name="l00676"></a><a class="code" href="structibl_boot__s.html#a457469539f7f23121fea412f04fb7cde">00676</a> uint32 <a class="code" href="structibl_boot__s.html#a457469539f7f23121fea412f04fb7cde">priority</a>;
439 <a name="l00677"></a><a class="code" href="structibl_boot__s.html#af6e792832790b5cb68de5b0989b601b7">00677</a> int32 <a class="code" href="structibl_boot__s.html#af6e792832790b5cb68de5b0989b601b7">port</a>;
440 <a name="l00679"></a>00679 <span class="keyword">union </span>{
441 <a name="l00680"></a>00680
442 <a name="l00681"></a><a class="code" href="structibl_boot__s.html#ad0c03b1a20175ad624ed6820ba522455">00681</a> <a class="code" href="structibl_eth__s.html" title="This structure is used to control the operation of the ibl ethernet boot.">iblEth_t</a> <a class="code" href="structibl_boot__s.html#ad0c03b1a20175ad624ed6820ba522455">ethBoot</a>;
443 <a name="l00683"></a><a class="code" href="structibl_boot__s.html#aa809f0704e74d9c8d9bf63688b4034c5">00683</a> <a class="code" href="structibl_nand__s.html" title="This structure is used to control the operation of the NAND boot.">iblNand_t</a> <a class="code" href="structibl_boot__s.html#aa809f0704e74d9c8d9bf63688b4034c5">nandBoot</a>;
444 <a name="l00685"></a><a class="code" href="structibl_boot__s.html#a4846f976983a7aa9c4de12f041dcd0da">00685</a> <a class="code" href="structibl_nor__s.html" title="Nor boot configuration.">iblNor_t</a> <a class="code" href="structibl_boot__s.html#a4846f976983a7aa9c4de12f041dcd0da">norBoot</a>;
445 <a name="l00687"></a>00687 } u;
446 <a name="l00688"></a>00688
447 <a name="l00689"></a>00689 } <a class="code" href="structibl_boot__s.html">iblBoot_t</a>;
448 <a name="l00690"></a>00690
449 <a name="l00691"></a>00691
450 <a name="l00695"></a>00695 <span class="preprocessor">#define ibl_MAGIC_VALUE 0xCEC11EBC </span>
451 <a name="l00700"></a>00700 <span class="preprocessor">#define ibl_EVM_C6455L 0x10 </span>
452 <a name="l00701"></a>00701 <span class="preprocessor">#define ibl_EVM_C6457L 0x20 </span>
453 <a name="l00702"></a>00702 <span class="preprocessor">#define ibl_EVM_C6472L 0x30 </span>
454 <a name="l00703"></a>00703 <span class="preprocessor">#define ibl_EVM_C6474L 0x40 </span>
455 <a name="l00704"></a>00704 <span class="preprocessor">#define ibl_EVM_C6474M 0x41 </span>
456 <a name="l00705"></a>00705 <span class="preprocessor">#define ibl_EVM_C6670L 0x50 </span>
457 <a name="l00706"></a>00706 <span class="preprocessor">#define ibl_EVM_C6678L 0x60 </span>
458 <a name="l00724"></a><a class="code" href="structibl__s.html">00724</a> <span class="preprocessor">typedef struct ibl_s</span>
459 <a name="l00725"></a>00725 <span class="preprocessor"></span>{
460 <a name="l00726"></a><a class="code" href="structibl__s.html#add5ec733f479909722380a6880995673">00726</a> uint32 <a class="code" href="structibl__s.html#add5ec733f479909722380a6880995673">iblMagic</a>;
461 <a name="l00728"></a><a class="code" href="structibl__s.html#af1e477e09d15a32e9a2ed6d89ee3d667">00728</a> <a class="code" href="structibl_pll__s.html" title="This structure is used to control the programming of the device PLL.">iblPll_t</a> pllConfig[<a class="code" href="group__ibl_pll_num.html#ga64571eeaa73441952ab8403655bea805">ibl_N_PLL_CFGS</a>];
462 <a name="l00730"></a><a class="code" href="structibl__s.html#a95a45446987cf69490d9004cdbe24b7d">00730</a> <a class="code" href="structidbl_ddr__s.html" title="This structure is used to configure the DDR interface.">iblDdr_t</a> <a class="code" href="structibl__s.html#a95a45446987cf69490d9004cdbe24b7d">ddrConfig</a>;
463 <a name="l00732"></a><a class="code" href="structibl__s.html#a752dc89274849576c56d626d4d7b5372">00732</a> <a class="code" href="structibl_sgmii__s.html" title="This structure is used to control the operation of the ibl sgmii ports.">iblSgmii_t</a> sgmiiConfig[ibl_N_ETH_PORTS];
464 <a name="l00734"></a><a class="code" href="structibl__s.html#a9225480ccb811b152809aa2a02462ca3">00734</a> <a class="code" href="structibl_mdio__s.html" title="This structure is used to configure phys through the mdio interface.">iblMdio_t</a> <a class="code" href="structibl__s.html#a9225480ccb811b152809aa2a02462ca3">mdioConfig</a>;
465 <a name="l00736"></a><a class="code" href="structibl__s.html#abf522eceb1d7804d9458e2b6617f85e7">00736</a> <a class="code" href="structibl_spi__s.html" title="SPI configuration used for either NOR or NAND.">iblSpi_t</a> <a class="code" href="structibl__s.html#abf522eceb1d7804d9458e2b6617f85e7">spiConfig</a>;
466 <a name="l00738"></a><a class="code" href="structibl__s.html#a1cc366bcd579365e8e736837b6b1f020">00738</a> <a class="code" href="structibl_emif__s.html" title="EMIF (nand/nor) configuration.">iblEmif_t</a> emifConfig[ibl_MAX_EMIF_PMEM];
467 <a name="l00740"></a><a class="code" href="structibl__s.html#a2edf5193321c7e1552ecd5604b4d5022">00740</a> <a class="code" href="structibl_boot__s.html">iblBoot_t</a> bootModes[ibl_N_BOOT_MODES];
468 <a name="l00742"></a><a class="code" href="structibl__s.html#a878fdb14f1ce7d58037db61a18831c77">00742</a> uint16 <a class="code" href="structibl__s.html#a878fdb14f1ce7d58037db61a18831c77">iblEvmType</a>;
469 <a name="l00744"></a><a class="code" href="structibl__s.html#ab937f6e330ae8a715bad68b6dc7b4322">00744</a> uint16 <a class="code" href="structibl__s.html#ab937f6e330ae8a715bad68b6dc7b4322">chkSum</a>;
470 <a name="l00746"></a>00746 } <a class="code" href="structibl__s.html" title="The main configuration/control structure for the ibl.">ibl_t</a>;
471 <a name="l00747"></a>00747
472 <a name="l00748"></a>00748
473 <a name="l00749"></a>00749 <span class="keyword">extern</span> <a class="code" href="structibl__s.html" title="The main configuration/control structure for the ibl.">ibl_t</a> ibl;
474 <a name="l00750"></a>00750
475 <a name="l00751"></a>00751
476 <a name="l00759"></a><a class="code" href="group__ibl_active_device.html#ga7b60ae08a7bc16d445b5c53ef920e4fe">00759</a> <span class="preprocessor">#define ibl_ACTIVE_DEVICE_ETH 100 </span>
477 <a name="l00764"></a><a class="code" href="group__ibl_active_device.html#gaf223b45eb86346d21b5ea47bcdd1ac95">00764</a> <span class="preprocessor">#define ibl_ACTIVE_DEVICE_EMIF 101 </span>
478 <a name="l00769"></a><a class="code" href="group__ibl_active_device.html#ga64ec9c63351daabf9473b94e7711174b">00769</a> <span class="preprocessor">#define ibl_ACTIVE_DEVICE_I2C 102 </span>
479 <a name="l00774"></a><a class="code" href="group__ibl_active_device.html#ga21924ee1617da4ea3c741445d7d035e6">00774</a> <span class="preprocessor">#define ibl_ACTIVE_DEVICE_SPI 103 </span>
480 <a name="l00776"></a>00776 <span class="preprocessor"></span><span class="comment">/* @} */</span>
481 <a name="l00777"></a>00777
482 <a name="l00778"></a>00778
483 <a name="l00786"></a><a class="code" href="group__ibl_fail_code.html#gace1789e7e50c850f153492f9827a3726">00786</a> <span class="preprocessor">#define ibl_FAIL_CODE_INVALID_I2C_ADDRESS 700 </span>
484 <a name="l00791"></a><a class="code" href="group__ibl_fail_code.html#gaf27ec9cdb149f8eb5c4c28c41bc97f59">00791</a> <span class="preprocessor">#define ibl_FAIL_CODE_BTBL_FAIL 701 </span>
485 <a name="l00796"></a><a class="code" href="group__ibl_fail_code.html#gacc39b134da7c8b5ac088042662193ca9">00796</a> <span class="preprocessor">#define ibl_FAIL_CODE_PA 702 </span>
486 <a name="l00802"></a><a class="code" href="group__ibl_fail_code.html#ga25a91e4268e8cc6c61eaf3fab3e43a7d">00802</a> <span class="preprocessor">#define ibl_FAIL_CODE_SPI_PARAMS 703 </span>
487 <a name="l00807"></a><a class="code" href="group__ibl_fail_code.html#ga2a52c8d9d930629d21694f8547f02edd">00807</a> <span class="preprocessor">#define ibl_FAIL_CODE_INVALID_INIT_DEVICE 704 </span>
488 <a name="l00812"></a><a class="code" href="group__ibl_fail_code.html#gafa86a8ee3cfa9480f187407cd8385c24">00812</a> <span class="preprocessor">#define ibl_FAIL_CODE_INVALID_SPI_ADDRESS 705 </span>
489 <a name="l00817"></a><a class="code" href="group__ibl_fail_code.html#gaee16c1d6e3dbeebeeef462a538bf98ed">00817</a> <span class="preprocessor">#define ibl_FAIL_CODE_PERIPH_POWER_UP 706 </span>
490 <a name="l00822"></a><a class="code" href="group__ibl_fail_code.html#gac6221874caedd0915c007b42c7eb0d32">00822</a> <span class="preprocessor">#define ibl_FAIL_CODE_INVALID_NAND_PERIPH 707 </span>
491 <a name="l00827"></a><a class="code" href="group__ibl_fail_code.html#ga66775ad56564f969f0dd03b19f0d7f8f">00827</a> <span class="preprocessor">#define ibl_FAIL_CODE_NO_EMIF_CFG 708 </span>
492 <a name="l00832"></a><a class="code" href="group__ibl_fail_code.html#gabaf518404427120c69387646c62a85cc">00832</a> <span class="preprocessor">#define ibl_FAIL_CODE_EMIF_CFG_FAIL 709 </span>
493 <a name="l00834"></a>00834 <span class="preprocessor"> </span><span class="comment">/* @} */</span>
494 <a name="l00835"></a>00835
495 <a name="l00836"></a>00836
496 <a name="l00845"></a><a class="code" href="structibl_status__s.html">00845</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structibl_status__s.html" title="Provide status on the boot operation.">iblStatus_s</a>
497 <a name="l00846"></a>00846 {
498 <a name="l00847"></a><a class="code" href="structibl_status__s.html#add5ec733f479909722380a6880995673">00847</a> uint32 <a class="code" href="structibl_status__s.html#add5ec733f479909722380a6880995673">iblMagic</a>;
499 <a name="l00849"></a><a class="code" href="structibl_status__s.html#ace272327d1658941b98b1e03cee3a402">00849</a> uint32 <a class="code" href="structibl_status__s.html#ace272327d1658941b98b1e03cee3a402">iblVersion</a>;
500 <a name="l00851"></a><a class="code" href="structibl_status__s.html#ac2eda90f13cdbbacb74024fa6f29ab2e">00851</a> uint32 <a class="code" href="structibl_status__s.html#ac2eda90f13cdbbacb74024fa6f29ab2e">iblFail</a>;
501 <a name="l00853"></a><a class="code" href="structibl_status__s.html#aea7e16d9a657dd69c5495664095ed6e4">00853</a> uint32 <a class="code" href="structibl_status__s.html#aea7e16d9a657dd69c5495664095ed6e4">i2cRetries</a>;
502 <a name="l00854"></a><a class="code" href="structibl_status__s.html#a440b1f0e50348ab334e7ddcaca43b4ef">00854</a> uint32 <a class="code" href="structibl_status__s.html#a440b1f0e50348ab334e7ddcaca43b4ef">i2cDataRetries</a>;
503 <a name="l00856"></a><a class="code" href="structibl_status__s.html#a6434dbc4e7687cea99f0fa2363476549">00856</a> uint32 <a class="code" href="structibl_status__s.html#a6434dbc4e7687cea99f0fa2363476549">spiRetries</a>;
504 <a name="l00857"></a><a class="code" href="structibl_status__s.html#af51b00e64de6af48d0b164718dc99593">00857</a> uint32 <a class="code" href="structibl_status__s.html#af51b00e64de6af48d0b164718dc99593">spiDataRetries</a>;
505 <a name="l00859"></a><a class="code" href="structibl_status__s.html#a8c93c8e4bc60be25d55b8e43a5aed2b3">00859</a> uint32 <a class="code" href="structibl_status__s.html#a8c93c8e4bc60be25d55b8e43a5aed2b3">magicRetries</a>;
506 <a name="l00860"></a><a class="code" href="structibl_status__s.html#a6aa1204e7bad49390ea53f9673fd6b2b">00860</a> uint32 <a class="code" href="structibl_status__s.html#a6aa1204e7bad49390ea53f9673fd6b2b">mapSizeFail</a>;
507 <a name="l00861"></a><a class="code" href="structibl_status__s.html#a3c52ce2b066817b2450fac026e1f3d3e">00861</a> uint32 <a class="code" href="structibl_status__s.html#a3c52ce2b066817b2450fac026e1f3d3e">mapRetries</a>;
508 <a name="l00863"></a><a class="code" href="structibl_status__s.html#a3be37918da6b342c4bca4441b5f7074b">00863</a> int32 <a class="code" href="structibl_status__s.html#a3be37918da6b342c4bca4441b5f7074b">heartBeat</a>;
509 <a name="l00865"></a><a class="code" href="structibl_status__s.html#af9404b81ae2879cf8119744172a80ae9">00865</a> int32 <a class="code" href="structibl_status__s.html#af9404b81ae2879cf8119744172a80ae9">activeBoot</a>;
510 <a name="l00866"></a><a class="code" href="structibl_status__s.html#ab97cd270113d9c27f1673e0961ed9f9b">00866</a> int32 <a class="code" href="structibl_status__s.html#ab97cd270113d9c27f1673e0961ed9f9b">activeDevice</a>;
511 <a name="l00867"></a><a class="code" href="structibl_status__s.html#aeadf4893c19422032edaaf3829c3fe6c">00867</a> int32 <a class="code" href="structibl_status__s.html#aeadf4893c19422032edaaf3829c3fe6c">activeFileFormat</a>;
512 <a name="l00869"></a><a class="code" href="structibl_status__s.html#aa25657c0354d19c7c6d692582de5c417">00869</a> uint32 <a class="code" href="structibl_status__s.html#aa25657c0354d19c7c6d692582de5c417">autoDetectFailCnt</a>;
513 <a name="l00870"></a><a class="code" href="structibl_status__s.html#a48ab769750f4203a3f42e615ce6fffb1">00870</a> uint32 <a class="code" href="structibl_status__s.html#a48ab769750f4203a3f42e615ce6fffb1">nameDetectFailCnt</a>;
514 <a name="l00872"></a><a class="code" href="structibl_status__s.html#a385624b1b6a8e1f0bb307c43ed65e467">00872</a> uint32 <a class="code" href="structibl_status__s.html#a385624b1b6a8e1f0bb307c43ed65e467">invalidDataFormatSpec</a>;
515 <a name="l00874"></a><a class="code" href="structibl_status__s.html#afb126a061728cd7cebaf57f59723365e">00874</a> uint32 <a class="code" href="structibl_status__s.html#afb126a061728cd7cebaf57f59723365e">exitAddress</a>;
516 <a name="l00876"></a><a class="code" href="structibl_status__s.html#ac94d4b125bbda1d2d70403b7efdbe4a0">00876</a> <a class="code" href="structibl_eth_boot_info__s.html" title="This structure contains information used for tftp boot.">iblEthBootInfo_t</a> <a class="code" href="structibl_status__s.html#ac94d4b125bbda1d2d70403b7efdbe4a0">ethParams</a>;
517 <a name="l00878"></a>00878 } <a class="code" href="structibl_status__s.html" title="Provide status on the boot operation.">iblStatus_t</a>;
518 <a name="l00879"></a>00879
519 <a name="l00880"></a>00880 <span class="keyword">extern</span> <a class="code" href="structibl_status__s.html" title="Provide status on the boot operation.">iblStatus_t</a> iblStatus;
520 <a name="l00881"></a>00881
521 <a name="l00882"></a>00882
522 <a name="l00891"></a><a class="code" href="structibl_boot_map__s.html">00891</a> <span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code" href="structibl_boot_map__s.html" title="The ibl boot map structure.">iblBootMap_s</a>
523 <a name="l00892"></a>00892 {
524 <a name="l00893"></a><a class="code" href="structibl_boot_map__s.html#ac980581eac611ff72becec6a8782bcef">00893</a> uint16 <a class="code" href="structibl_boot_map__s.html#ac980581eac611ff72becec6a8782bcef">length</a>;
525 <a name="l00894"></a><a class="code" href="structibl_boot_map__s.html#ab937f6e330ae8a715bad68b6dc7b4322">00894</a> uint16 <a class="code" href="structibl_boot_map__s.html#ab937f6e330ae8a715bad68b6dc7b4322">chkSum</a>;
526 <a name="l00896"></a><a class="code" href="structibl_boot_map__s.html#adc6de6281b0aff2e7fba0909fa550a82">00896</a> uint32 <a class="code" href="structibl_boot_map__s.html#adc6de6281b0aff2e7fba0909fa550a82">addrLe</a>;
527 <a name="l00897"></a><a class="code" href="structibl_boot_map__s.html#afec4599864d7b359ddfd6b6888fe0909">00897</a> uint32 <a class="code" href="structibl_boot_map__s.html#afec4599864d7b359ddfd6b6888fe0909">configLe</a>;
528 <a name="l00899"></a><a class="code" href="structibl_boot_map__s.html#a26da46fbca5a801dc3a7eb2e1fda1557">00899</a> uint32 <a class="code" href="structibl_boot_map__s.html#a26da46fbca5a801dc3a7eb2e1fda1557">addrBe</a>;
529 <a name="l00900"></a><a class="code" href="structibl_boot_map__s.html#ab03cf2a9aa8c794d998af53d8e396f2a">00900</a> uint32 <a class="code" href="structibl_boot_map__s.html#ab03cf2a9aa8c794d998af53d8e396f2a">configBe</a>;
530 <a name="l00902"></a>00902 } <a class="code" href="structibl_boot_map__s.html" title="The ibl boot map structure.">iblBootMap_t</a>;
531 <a name="l00903"></a>00903
532 <a name="l00904"></a>00904
533 <a name="l00905"></a>00905
534 <a name="l00906"></a>00906
535 <a name="l00907"></a>00907
536 <a name="l00908"></a>00908
537 <a name="l00909"></a>00909
538 <a name="l00910"></a>00910 <span class="preprocessor">#endif </span><span class="comment">/* IBL_H */</span>
539 </pre></div></div>
540 </div>
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555 <hr class="footer"/><address class="footer"><small>Generated on Mon May 2 2011 12:50:33 for IBL Configuration by 
556 <a href="http://www.doxygen.org/index.html">
557 <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.4 </small></address>
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