doc/IBL-Configuration/structibl_emif4p0__s.html

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   5 <title>IBL Configuration: iblEmif4p0_s Struct Reference</title>
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  22    <div id="projectname">IBL Configuration</div>
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  60 <div class="header">
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  62 <a href="#pub-attribs">Data Fields</a>  </div>
  63   <div class="headertitle">
  64 <div class="title">iblEmif4p0_s Struct Reference</div>  </div>
  65 </div>
  66 <div class="contents">
  67 <!-- doxytag: class="iblEmif4p0_s" -->
  68 <p>Emif controller 4.0 configuration.
  69  <a href="structibl_emif4p0__s.html#details">More...</a></p>
  70
  71 <p><code>#include &lt;<a class="el" href="ibl_8h_source.html">ibl.h</a>&gt;</code></p>
  72 <table class="memberdecls">
  73 <tr><td colspan="2"><h2><a name="pub-attribs"></a>
  74 Data Fields</h2></td></tr>
  75 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#afc32bc65ce2cf71dd3c6e30a239af47e">registerMask</a></td></tr>
  76 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a5faf82fad83d39e53de237a13d512220">sdRamConfig</a></td></tr>
  77 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a8a03c562a21ec31b59c17c72bcddb4ec">sdRamConfig2</a></td></tr>
  78 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#afc1d0b4e38a8ce09b240abb20bc60116">sdRamRefreshCtl</a></td></tr>
  79 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#ae330e2ac1c489536400107dabe14229a">sdRamTiming1</a></td></tr>
  80 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#ad34082e05339f2632e978dc42389a9e7">sdRamTiming2</a></td></tr>
  81 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a9bdbcede174de1bd60c4a2d06549d672">sdRamTiming3</a></td></tr>
  82 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a9f0ea9fb2dde68278b226cf61db7d724">lpDdrNvmTiming</a></td></tr>
  83 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a8faa1c2c250fd8d50a1821f9f9a4c15f">powerManageCtl</a></td></tr>
  84 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a6d5eb1a616936e57873af2a648819d2f">iODFTTestLogic</a></td></tr>
  85 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a779f0a58c5d1cc0e492f24b3f842ddd0">performCountCfg</a></td></tr>
  86 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#af5754e8493066e1b66dea97161916a14">performCountMstRegSel</a></td></tr>
  87 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#ae792d7050596145b63d50117d6220de3">readIdleCtl</a></td></tr>
  88 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#aa6f4e601d939f54af799f78571f24cbc">sysVbusmIntEnSet</a></td></tr>
  89 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a24b8b8f644cab72d004375d7ef597322">sdRamOutImpdedCalCfg</a></td></tr>
  90 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#ac27fa6e3bf375487950e5a3b4a429ba7">tempAlterCfg</a></td></tr>
  91 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a959f7a69fe3191f79cb200263067d3e9">ddrPhyCtl1</a></td></tr>
  92 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#abc295d552a398f31e636f2dbb9ce180c">ddrPhyCtl2</a></td></tr>
  93 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#aeee9d593ff0901ec99ca9e7ebb3fa2f6">priClassSvceMap</a></td></tr>
  94 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a8ed6f7abab17ae59bf2a1cf5169fb3e8">mstId2ClsSvce1Map</a></td></tr>
  95 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a19116d15b3c25e891b85134f5298af17">mstId2ClsSvce2Map</a></td></tr>
  96 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a4cc76fb6a01e74434bad174b82485489">eccCtl</a></td></tr>
  97 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a3416b063ce5e86cf0b99752baed7e978">eccRange1</a></td></tr>
  98 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a8c9d5f1c8ebd1e746a05915b80e8a0c2">eccRange2</a></td></tr>
  99 <tr><td class="memItemLeft" align="right" valign="top">uint32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a512ad045f76a8a93b5bdad6a80cd2454">rdWrtExcThresh</a></td></tr>
 100 </table>
 101 <hr/><a name="details" id="details"></a><h2>Detailed Description</h2>
 102 <div class="textblock"><p>Emif controller 4.0 configuration. </p>
 103 <p>The parameters are placed directly into the emif controller </p>
 104 </div><hr/><h2>Field Documentation</h2>
 105 <a class="anchor" id="a959f7a69fe3191f79cb200263067d3e9"></a><!-- doxytag: member="iblEmif4p0_s::ddrPhyCtl1" ref="a959f7a69fe3191f79cb200263067d3e9" args="" -->
 106 <div class="memitem">
 107 <div class="memproto">
 108       <table class="memname">
 109         <tr>
 110           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a959f7a69fe3191f79cb200263067d3e9">ddrPhyCtl1</a></td>
 111         </tr>
 112       </table>
 113 </div>
 114 <div class="memdoc">
 115 <p>DDR PHY Control 1 Register </p>
 116
 117 </div>
 118 </div>
 119 <a class="anchor" id="abc295d552a398f31e636f2dbb9ce180c"></a><!-- doxytag: member="iblEmif4p0_s::ddrPhyCtl2" ref="abc295d552a398f31e636f2dbb9ce180c" args="" -->
 120 <div class="memitem">
 121 <div class="memproto">
 122       <table class="memname">
 123         <tr>
 124           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#abc295d552a398f31e636f2dbb9ce180c">ddrPhyCtl2</a></td>
 125         </tr>
 126       </table>
 127 </div>
 128 <div class="memdoc">
 129 <p>DDR PHY Control 2 Register </p>
 130
 131 </div>
 132 </div>
 133 <a class="anchor" id="a4cc76fb6a01e74434bad174b82485489"></a><!-- doxytag: member="iblEmif4p0_s::eccCtl" ref="a4cc76fb6a01e74434bad174b82485489" args="" -->
 134 <div class="memitem">
 135 <div class="memproto">
 136       <table class="memname">
 137         <tr>
 138           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a4cc76fb6a01e74434bad174b82485489">eccCtl</a></td>
 139         </tr>
 140       </table>
 141 </div>
 142 <div class="memdoc">
 143 <p>ECC Control Register </p>
 144
 145 </div>
 146 </div>
 147 <a class="anchor" id="a3416b063ce5e86cf0b99752baed7e978"></a><!-- doxytag: member="iblEmif4p0_s::eccRange1" ref="a3416b063ce5e86cf0b99752baed7e978" args="" -->
 148 <div class="memitem">
 149 <div class="memproto">
 150       <table class="memname">
 151         <tr>
 152           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a3416b063ce5e86cf0b99752baed7e978">eccRange1</a></td>
 153         </tr>
 154       </table>
 155 </div>
 156 <div class="memdoc">
 157 <p>ECC Address Range 1 Register </p>
 158
 159 </div>
 160 </div>
 161 <a class="anchor" id="a8c9d5f1c8ebd1e746a05915b80e8a0c2"></a><!-- doxytag: member="iblEmif4p0_s::eccRange2" ref="a8c9d5f1c8ebd1e746a05915b80e8a0c2" args="" -->
 162 <div class="memitem">
 163 <div class="memproto">
 164       <table class="memname">
 165         <tr>
 166           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a8c9d5f1c8ebd1e746a05915b80e8a0c2">eccRange2</a></td>
 167         </tr>
 168       </table>
 169 </div>
 170 <div class="memdoc">
 171 <p>ECC Address Range 2 Register </p>
 172
 173 </div>
 174 </div>
 175 <a class="anchor" id="a6d5eb1a616936e57873af2a648819d2f"></a><!-- doxytag: member="iblEmif4p0_s::iODFTTestLogic" ref="a6d5eb1a616936e57873af2a648819d2f" args="" -->
 176 <div class="memitem">
 177 <div class="memproto">
 178       <table class="memname">
 179         <tr>
 180           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a6d5eb1a616936e57873af2a648819d2f">iODFTTestLogic</a></td>
 181         </tr>
 182       </table>
 183 </div>
 184 <div class="memdoc">
 185 <p>IODFT Test Logic Global Control Register </p>
 186
 187 </div>
 188 </div>
 189 <a class="anchor" id="a9f0ea9fb2dde68278b226cf61db7d724"></a><!-- doxytag: member="iblEmif4p0_s::lpDdrNvmTiming" ref="a9f0ea9fb2dde68278b226cf61db7d724" args="" -->
 190 <div class="memitem">
 191 <div class="memproto">
 192       <table class="memname">
 193         <tr>
 194           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a9f0ea9fb2dde68278b226cf61db7d724">lpDdrNvmTiming</a></td>
 195         </tr>
 196       </table>
 197 </div>
 198 <div class="memdoc">
 199 <p>LPDDR2-NVM Timing Register </p>
 200
 201 </div>
 202 </div>
 203 <a class="anchor" id="a8ed6f7abab17ae59bf2a1cf5169fb3e8"></a><!-- doxytag: member="iblEmif4p0_s::mstId2ClsSvce1Map" ref="a8ed6f7abab17ae59bf2a1cf5169fb3e8" args="" -->
 204 <div class="memitem">
 205 <div class="memproto">
 206       <table class="memname">
 207         <tr>
 208           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a8ed6f7abab17ae59bf2a1cf5169fb3e8">mstId2ClsSvce1Map</a></td>
 209         </tr>
 210       </table>
 211 </div>
 212 <div class="memdoc">
 213 <p>Master ID to Class of Service 1 Mapping Register </p>
 214
 215 </div>
 216 </div>
 217 <a class="anchor" id="a19116d15b3c25e891b85134f5298af17"></a><!-- doxytag: member="iblEmif4p0_s::mstId2ClsSvce2Map" ref="a19116d15b3c25e891b85134f5298af17" args="" -->
 218 <div class="memitem">
 219 <div class="memproto">
 220       <table class="memname">
 221         <tr>
 222           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a19116d15b3c25e891b85134f5298af17">mstId2ClsSvce2Map</a></td>
 223         </tr>
 224       </table>
 225 </div>
 226 <div class="memdoc">
 227 <p>Master ID to Class of Service 2 Mapping Register </p>
 228
 229 </div>
 230 </div>
 231 <a class="anchor" id="a779f0a58c5d1cc0e492f24b3f842ddd0"></a><!-- doxytag: member="iblEmif4p0_s::performCountCfg" ref="a779f0a58c5d1cc0e492f24b3f842ddd0" args="" -->
 232 <div class="memitem">
 233 <div class="memproto">
 234       <table class="memname">
 235         <tr>
 236           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a779f0a58c5d1cc0e492f24b3f842ddd0">performCountCfg</a></td>
 237         </tr>
 238       </table>
 239 </div>
 240 <div class="memdoc">
 241 <p>Performance Counter Config Register </p>
 242
 243 </div>
 244 </div>
 245 <a class="anchor" id="af5754e8493066e1b66dea97161916a14"></a><!-- doxytag: member="iblEmif4p0_s::performCountMstRegSel" ref="af5754e8493066e1b66dea97161916a14" args="" -->
 246 <div class="memitem">
 247 <div class="memproto">
 248       <table class="memname">
 249         <tr>
 250           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#af5754e8493066e1b66dea97161916a14">performCountMstRegSel</a></td>
 251         </tr>
 252       </table>
 253 </div>
 254 <div class="memdoc">
 255 <p>Performance Counter Master Region Select Register </p>
 256
 257 </div>
 258 </div>
 259 <a class="anchor" id="a8faa1c2c250fd8d50a1821f9f9a4c15f"></a><!-- doxytag: member="iblEmif4p0_s::powerManageCtl" ref="a8faa1c2c250fd8d50a1821f9f9a4c15f" args="" -->
 260 <div class="memitem">
 261 <div class="memproto">
 262       <table class="memname">
 263         <tr>
 264           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a8faa1c2c250fd8d50a1821f9f9a4c15f">powerManageCtl</a></td>
 265         </tr>
 266       </table>
 267 </div>
 268 <div class="memdoc">
 269 <p>Power Management Control Register </p>
 270
 271 </div>
 272 </div>
 273 <a class="anchor" id="aeee9d593ff0901ec99ca9e7ebb3fa2f6"></a><!-- doxytag: member="iblEmif4p0_s::priClassSvceMap" ref="aeee9d593ff0901ec99ca9e7ebb3fa2f6" args="" -->
 274 <div class="memitem">
 275 <div class="memproto">
 276       <table class="memname">
 277         <tr>
 278           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#aeee9d593ff0901ec99ca9e7ebb3fa2f6">priClassSvceMap</a></td>
 279         </tr>
 280       </table>
 281 </div>
 282 <div class="memdoc">
 283 <p>DDR Priority to Class of Service Mapping Register </p>
 284
 285 </div>
 286 </div>
 287 <a class="anchor" id="a512ad045f76a8a93b5bdad6a80cd2454"></a><!-- doxytag: member="iblEmif4p0_s::rdWrtExcThresh" ref="a512ad045f76a8a93b5bdad6a80cd2454" args="" -->
 288 <div class="memitem">
 289 <div class="memproto">
 290       <table class="memname">
 291         <tr>
 292           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a512ad045f76a8a93b5bdad6a80cd2454">rdWrtExcThresh</a></td>
 293         </tr>
 294       </table>
 295 </div>
 296 <div class="memdoc">
 297 <p>Read Write Execution Threshold Register </p>
 298
 299 </div>
 300 </div>
 301 <a class="anchor" id="ae792d7050596145b63d50117d6220de3"></a><!-- doxytag: member="iblEmif4p0_s::readIdleCtl" ref="ae792d7050596145b63d50117d6220de3" args="" -->
 302 <div class="memitem">
 303 <div class="memproto">
 304       <table class="memname">
 305         <tr>
 306           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#ae792d7050596145b63d50117d6220de3">readIdleCtl</a></td>
 307         </tr>
 308       </table>
 309 </div>
 310 <div class="memdoc">
 311 <p>Read Idle Control Register </p>
 312
 313 </div>
 314 </div>
 315 <a class="anchor" id="afc32bc65ce2cf71dd3c6e30a239af47e"></a><!-- doxytag: member="iblEmif4p0_s::registerMask" ref="afc32bc65ce2cf71dd3c6e30a239af47e" args="" -->
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 320           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#afc32bc65ce2cf71dd3c6e30a239af47e">registerMask</a></td>
 321         </tr>
 322       </table>
 323 </div>
 324 <div class="memdoc">
 325 <p>Identifies which registers will be configured </p>
 326
 327 </div>
 328 </div>
 329 <a class="anchor" id="a5faf82fad83d39e53de237a13d512220"></a><!-- doxytag: member="iblEmif4p0_s::sdRamConfig" ref="a5faf82fad83d39e53de237a13d512220" args="" -->
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 335         </tr>
 336       </table>
 337 </div>
 338 <div class="memdoc">
 339 <p>SDRAM Config Register </p>
 340
 341 </div>
 342 </div>
 343 <a class="anchor" id="a8a03c562a21ec31b59c17c72bcddb4ec"></a><!-- doxytag: member="iblEmif4p0_s::sdRamConfig2" ref="a8a03c562a21ec31b59c17c72bcddb4ec" args="" -->
 344 <div class="memitem">
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 348           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a8a03c562a21ec31b59c17c72bcddb4ec">sdRamConfig2</a></td>
 349         </tr>
 350       </table>
 351 </div>
 352 <div class="memdoc">
 353 <p>SDRAM Config2 Register </p>
 354
 355 </div>
 356 </div>
 357 <a class="anchor" id="a24b8b8f644cab72d004375d7ef597322"></a><!-- doxytag: member="iblEmif4p0_s::sdRamOutImpdedCalCfg" ref="a24b8b8f644cab72d004375d7ef597322" args="" -->
 358 <div class="memitem">
 359 <div class="memproto">
 360       <table class="memname">
 361         <tr>
 362           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a24b8b8f644cab72d004375d7ef597322">sdRamOutImpdedCalCfg</a></td>
 363         </tr>
 364       </table>
 365 </div>
 366 <div class="memdoc">
 367 <p>SDRAM Output Impedance Calibratin Config Register </p>
 368
 369 </div>
 370 </div>
 371 <a class="anchor" id="afc1d0b4e38a8ce09b240abb20bc60116"></a><!-- doxytag: member="iblEmif4p0_s::sdRamRefreshCtl" ref="afc1d0b4e38a8ce09b240abb20bc60116" args="" -->
 372 <div class="memitem">
 373 <div class="memproto">
 374       <table class="memname">
 375         <tr>
 376           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#afc1d0b4e38a8ce09b240abb20bc60116">sdRamRefreshCtl</a></td>
 377         </tr>
 378       </table>
 379 </div>
 380 <div class="memdoc">
 381 <p>SDRAM Refresh Control Register </p>
 382
 383 </div>
 384 </div>
 385 <a class="anchor" id="ae330e2ac1c489536400107dabe14229a"></a><!-- doxytag: member="iblEmif4p0_s::sdRamTiming1" ref="ae330e2ac1c489536400107dabe14229a" args="" -->
 386 <div class="memitem">
 387 <div class="memproto">
 388       <table class="memname">
 389         <tr>
 390           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#ae330e2ac1c489536400107dabe14229a">sdRamTiming1</a></td>
 391         </tr>
 392       </table>
 393 </div>
 394 <div class="memdoc">
 395 <p>SDRAM Timing 1 Register </p>
 396
 397 </div>
 398 </div>
 399 <a class="anchor" id="ad34082e05339f2632e978dc42389a9e7"></a><!-- doxytag: member="iblEmif4p0_s::sdRamTiming2" ref="ad34082e05339f2632e978dc42389a9e7" args="" -->
 400 <div class="memitem">
 401 <div class="memproto">
 402       <table class="memname">
 403         <tr>
 404           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#ad34082e05339f2632e978dc42389a9e7">sdRamTiming2</a></td>
 405         </tr>
 406       </table>
 407 </div>
 408 <div class="memdoc">
 409 <p>SDRAM Timing 2 Register </p>
 410
 411 </div>
 412 </div>
 413 <a class="anchor" id="a9bdbcede174de1bd60c4a2d06549d672"></a><!-- doxytag: member="iblEmif4p0_s::sdRamTiming3" ref="a9bdbcede174de1bd60c4a2d06549d672" args="" -->
 414 <div class="memitem">
 415 <div class="memproto">
 416       <table class="memname">
 417         <tr>
 418           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a9bdbcede174de1bd60c4a2d06549d672">sdRamTiming3</a></td>
 419         </tr>
 420       </table>
 421 </div>
 422 <div class="memdoc">
 423 <p>SDRAM Timing 3 Register </p>
 424
 425 </div>
 426 </div>
 427 <a class="anchor" id="aa6f4e601d939f54af799f78571f24cbc"></a><!-- doxytag: member="iblEmif4p0_s::sysVbusmIntEnSet" ref="aa6f4e601d939f54af799f78571f24cbc" args="" -->
 428 <div class="memitem">
 429 <div class="memproto">
 430       <table class="memname">
 431         <tr>
 432           <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#aa6f4e601d939f54af799f78571f24cbc">sysVbusmIntEnSet</a></td>
 433         </tr>
 434       </table>
 435 </div>
 436 <div class="memdoc">
 437 <p>VBUSM Interrupt Enable Set Register </p>
 438
 439 </div>
 440 </div>
 441 <a class="anchor" id="ac27fa6e3bf375487950e5a3b4a429ba7"></a><!-- doxytag: member="iblEmif4p0_s::tempAlterCfg" ref="ac27fa6e3bf375487950e5a3b4a429ba7" args="" -->
 442 <div class="memitem">
 443 <div class="memproto">
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 447         </tr>
 448       </table>
 449 </div>
 450 <div class="memdoc">
 451 <p>Temperature Alert Config Register </p>
 452
 453 </div>
 454 </div>
 455 <hr/>The documentation for this struct was generated from the following file:<ul>
 456 <li><a class="el" href="ibl_8h_source.html">ibl.h</a></li>
 457 </ul>
 458 </div>
 459 <!-- window showing the filter options -->
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 473 <hr class="footer"/><address class="footer"><small>Generated on Mon May 2 2011 12:50:34 for IBL Configuration by&#160;
 474 <a href="http://www.doxygen.org/index.html">
 475 <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.4 </small></address>
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