bffe7f0aed14eda98dd4cc4fc1fec10cf8e8e114
1 /*
2 *
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
38 /**************************************************************************
39 * FILE PURPOSE: Target specific definitions
40 **************************************************************************
41 * FILE NAME: target.h
42 *
43 * DESCRIPTION: This file defines target specific values used by low level
44 * drivers.
45 *
46 * @file target.h
47 *
48 * @brief
49 * Low level target specific values are defined
50 *
51 ***************************************************************************/
53 /**
54 * @brief
55 * Device EMAC definitions
56 */
57 #define TARGET_DEVICE_CPMAC
59 #define TARGET_EMAC_N_PORTS 1
61 #define TARGET_EMAC_BASE_ADDRESSES { 0x02c80000u }
62 #define TARGET_EMAC_DSC_BASE_ADDR { 0x02c82000u }
65 /* No chip level reset required for ethernet, the function call is made a void statment */
66 #define deviceSetEthResetState(x,y)
68 /* There is no sgmii on the 6455, so the sgmii config is defined to a void statement */
69 #define hwSgmiiConfig(x,y)
71 /* Mdio is handled outside the emac driver */
72 #define dev_mdio_open() 1
74 #define TARGET_MAC_CONTROL (1 << 5) /* gmii enable */ \
75 | (1 << 0) /* full duplex */
77 /**
78 * @brief
79 * Device Timer definitions
80 */
81 #define TIMER0_BASE 0x02940000u
82 #define TIMER_INPUT_DIVIDER 6 /* Timer driven from cpu clock / 6 */
86 /**
87 * @def MAIN_PLL
88 */
89 #define MAIN_PLL 0 /**< The index to the main PLL */
91 /**
92 * @def NET_PLL
93 */
94 #define NET_PLL 1 /**< The index to the network PLL */
96 /**
97 * @def DDR_PLL
98 */
99 #define DDR_PLL 2 /**< The index to the DDR PLL */
102 /**
103 * @brief
104 * Device PLL definitions
105 */
106 #define DEVICE_PLL_BASE(x) ((x) == MAIN_PLL ? 0x29a0000 : ((x) == NET_PLL ? 0x29c0000 : 0))
109 /**
110 * @brief
111 * Flag to indicate ethernet power up requested
112 */
113 #define TARGET_PWR_ETH(x) 1
115 /**
116 * @brief
117 * Flag to indicate DDR power up requested
118 */
119 #define TARGET_PWR_DDR 2
121 /**
122 * @brief
123 * Flag to indicate timer 0 power up requested
124 */
125 #define TARGET_PWR_TIMER_0 3
128 /**
129 * @brief
130 * The nand is done through gpio, which is always powered up.
131 * A value < 0 tells the low level psc driver to simply return success
132 */
133 #define TARGET_PWR_NAND -1
136 /**
137 * @brief
138 * Device DDR controller definitions
139 */
140 #define DEVICE_DDR_BASE 0x78000000
142 /**
143 * @brief
144 * The base address of MDIO
145 */
146 #define TARGET_MDIO_BASE 0x2c81800
150 /**
151 * @brief
152 * GPIO address
153 */
154 #define GPIO_GPIOPID_REG 0x02B00000
155 #define GPIO_GPIOEMU_REG 0x02B00004
156 #define GPIO_BINTEN_REG 0x02B00008
157 #define GPIO_DIR_REG 0x02B00010
158 #define GPIO_OUT_DATA_REG 0x02B00014
159 #define GPIO_SET_DATA_REG 0x02B00018
160 #define GPIO_CLEAR_DATA_REG 0x02B0001C
161 #define GPIO_IN_DATA_REG 0x02B00020
162 #define GPIO_SET_RIS_TRIG_REG 0x02B00024
163 #define GPIO_CLR_RIS_TRIG_REG 0x02B00028
164 #define GPIO_SET_FAL_TRIG_REG 0x02B0002C
165 #define GPIO_CLR_FAL_TRIG_REG 0x02B00030
168 /**
169 * @brief
170 * The base address of the I2C peripheral, and the module divisor of the cpu clock
171 */
172 #define DEVICE_I2C_BASE 0x02b04000
173 #define DEVICE_I2C_MODULE_DIVISOR 6
176 /**
177 * @brief
178 * Register access macros
179 */
180 #define DEVICE_REG32_W(x,y) *(volatile unsigned int *)(x)=(y)
181 #define DEVICE_REG32_R(x) (*(volatile unsigned int *)(x))
183 #define BOOTBITMASK(x,y) ( ( ( ((UINT32)1 << (((UINT32)x)-((UINT32)y)+(UINT32)1) ) - (UINT32)1 ) ) << ((UINT32)y) )
184 #define BOOT_READ_BITFIELD(z,x,y) (((UINT32)z) & BOOTBITMASK(x,y)) >> (y)
185 #define BOOT_SET_BITFIELD(z,f,x,y) (((UINT32)z) & ~BOOTBITMASK(x,y)) | ( (((UINT32)f) << (y)) & BOOTBITMASK(x,y) )