1 /*
2 *
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
38 /**************************************************************************
39 * FILE PURPOSE: Target specific definitions
40 **************************************************************************
41 * FILE NAME: target.h
42 *
43 * DESCRIPTION: This file defines target specific values used by low level
44 * drivers.
45 *
46 * @file target.h
47 *
48 * @brief
49 * Low level target specific values are defined
50 *
51 ***************************************************************************/
54 /**
55 * @brief
56 * Device EMAC definitions
57 */
58 #define TARGET_DEVICE_CPMAC
60 #define TARGET_EMAC_N_PORTS 2
62 #define TARGET_EMAC_BASE_ADDRESSES { 0x02c80000u, 0x02cc0000u }
63 #define TARGET_EMAC_DSC_BASE_ADDR { 0x02c82000u, 0x02cc2000u }
65 /* Leave mdio disabled */
66 #define dev_mdio_open() 1
68 /* No chip level reset required for ethernet, the function call is made a void statment */
69 #define deviceSetEthResetState(x,y)
71 /* The mac control register values used */
72 #define TARGET_MAC_CONTROL CPMAC_MACCONTROL_RXOWNERSHIP | \
73 CPMAC_MACCONTROL_RXOFFLENBLOCK | \
74 CPMAC_MACCONTROL_MIIEN
76 /* There is no sgmii on the 6472, so the sgmii config is defined to a void statement */
77 #define hwSgmiiConfig(x,y)
81 /**
82 * @brief
83 * Device Timer definitions
84 */
85 #define TIMER0_BASE 0x025e0000u
87 #define TIMER_INPUT_DIVIDER 6 /* Timer driven from cpu clock / 6 */
90 /**
91 * @def MAIN_PLL
92 */
93 #define MAIN_PLL 0 /**< The index to the main PLL */
95 /**
96 * @def NET_PLL
97 */
98 #define NET_PLL 1 /**< The index to the network PLL */
100 /**
101 * @def DDR_PLL
102 */
103 #define DDR_PLL 2 /**< The index to the DDR PLL */
106 /**
107 * @brief
108 * Device PLL definitions
109 */
110 #define DEVICE_PLL_BASE(x) ((x) == MAIN_PLL ? 0x29a0000 : ((x) == NET_PLL ? 0x29c0000 : 0x29c0400))
113 /**
114 * @brief
115 * Device PSC definitions
116 */
117 #define DEVICE_PSC_BASE 0x02ae0000u
119 /**
120 * @brief
121 * The PSC number for ethernet port 0 is 7, and for port 1 it is 8 */
122 #define TARGET_PWR_ETH(x) ((x) == 0 ? 7 : 8)
124 /**
125 * @brief
126 * The nand is done through gpio, which is always powered up.
127 * A value < 0 tells the low level psc driver to simply return success
128 */
129 #define TARGET_PWR_NAND -1
131 /**
132 * @brief
133 * Flag to indicate timer 0 power up requested. The time is always on in the 6472
134 */
135 #define TARGET_PWR_TIMER_0 -1
137 /**
138 * @brief
139 * Device DDR controller definitions
140 */
141 #define DEVICE_DDR_BASE 0x78000000
143 /**
144 * @brief
145 * The highest module number
146 */
147 #define TARGET_PWR_MAX_MOD 13
150 /**
151 * @brief
152 * The base address of MDIO
153 */
154 #define TARGET_MDIO_BASE 0x2c81800
156 /**
157 * @brief
158 * GPIO address
159 */
160 #define GPIO_GPIOPID_REG 0x02B00000
161 #define GPIO_GPIOEMU_REG 0x02B00004
162 #define GPIO_BINTEN_REG 0x02B00008
163 #define GPIO_DIR_REG 0x02B00010
164 #define GPIO_OUT_DATA_REG 0x02B00014
165 #define GPIO_SET_DATA_REG 0x02B00018
166 #define GPIO_CLEAR_DATA_REG 0x02B0001C
167 #define GPIO_IN_DATA_REG 0x02B00020
168 #define GPIO_SET_RIS_TRIG_REG 0x02B00024
169 #define GPIO_CLR_RIS_TRIG_REG 0x02B00028
170 #define GPIO_SET_FAL_TRIG_REG 0x02B0002C
171 #define GPIO_CLR_FAL_TRIG_REG 0x02B00030
173 /**
174 * @brief
175 * The base address of the I2C peripheral, and the module divisor of the cpu clock
176 */
177 #define DEVICE_I2C_BASE 0x02b04000
178 #define DEVICE_I2C_MODULE_DIVISOR 6