1 /**************************************************************************
2 * FILE PURPOSE: Target specific definitions
3 **************************************************************************
4 * FILE NAME: target.h
5 *
6 * DESCRIPTION: This file defines target specific values used by low level
7 * drivers.
8 *
9 * @file target.h
10 *
11 * @brief
12 * Low level target specific values are defined
13 *
14 ***************************************************************************/
17 /**
18 * @brief
19 * Device EMAC definitions
20 */
21 #define TARGET_DEVICE_CPMAC
23 #define TARGET_EMAC_N_PORTS 1
25 #define TARGET_EMAC_BASE_ADDRESSES { 0x02c80000u }
26 #define TARGET_EMAC_DSC_BASE_ADDR { 0x02c82000u }
28 #define TARGET_SGMII_BASE_ADDRESSES { 0x02c40000u }
30 /* SGMII offsets (at least the serdes configs, vary between devices, so
31 * they are defined here. */
32 #define TARGET_SGMII_IDVER 0x000
33 #define TARGET_SGMII_SOFT_RESET 0x004
34 #define TARGET_SGMII_CONTROL 0x010
35 #define TARGET_SGMII_STATUS 0x014
36 #define TARGET_SGMII_MR_ADV_ABILITY 0x018
37 #define TARGET_SGMII_MR_LP_ADV_ABILITY 0x020
38 #define TARGET_SGMII_TX_CFG 0x030
39 #define TARGET_SGMII_RX_CFG 0x034
40 #define TARGET_SGMII_AUX_CFG 0x038
42 /* Leave mdio disabled */
43 #define dev_mdio_open() 1
45 /* No chip level reset required for ethernet, the function call is made a void statment */
46 #define deviceSetEthResetState(x,y)
48 /* The mac control register values */
49 #define TARGET_MAC_CONTROL ( 1 << 18) /* EXT_EN */ \
50 | ( 0 << 9 ) /* Round robin */ \
51 | ( 1 << 7 ) /* GIG */ \
52 | ( 0 << 6 ) /* TX pacing disabled */ \
53 | ( 1 << 5 ) /* GMII RX & TX */ \
54 | ( 0 << 4 ) /* TX flow disabled */ \
55 | ( 0 << 3 ) /* RX flow disabled */ \
56 | ( 0 << 1 ) /* Loopback enabled */ \
57 | ( 1 << 0 ) /* full duplex */
60 /**
61 * @brief
62 * Device Timer definitions
63 */
64 #define TIMER0_BASE 0x02910000u
66 #define TIMER_INPUT_DIVIDER 6 /* Timer driven from cpu clock / 6 */
69 /**
70 * @def MAIN_PLL
71 */
72 #define MAIN_PLL 0 /**< The index to the main PLL */
75 /**
76 * @brief
77 * Device PLL definitions
78 */
79 #define DEVICE_PLL_BASE(x) ((x) == MAIN_PLL ? 0x29a0000 : 0)
82 /**
83 * @brief
84 * Device PSC definitions
85 */
86 #define DEVICE_PSC_BASE 0x02ac0000u
88 /**
89 * @brief
90 * The ethernet is in the always on domain */
91 #define TARGET_PWR_ETH(x) -1
93 /**
94 * @brief
95 * The nand is done through gpio, which is always powered up.
96 * A value < 0 tells the low level psc driver to simply return success
97 */
98 #define TARGET_PWR_NAND -1
100 /**
101 * @brief
102 * Flag to indicate timer 0 power up requested. The time is always on in the 6474
103 */
104 #define TARGET_PWR_TIMER_0 -1
107 /**
108 * @brief
109 * Device DDR controller definitions
110 */
111 #define DEVICE_DDR_BASE 0x70000000
113 /**
114 * @brief
115 * The highest module number
116 */
117 #define TARGET_PWR_MAX_MOD 5
120 /**
121 * @brief
122 * The base address of MDIO
123 */
124 #define TARGET_MDIO_BASE 0x2c81800
126 /**
127 * @brief
128 * GPIO address
129 */
130 #define GPIO_GPIOPID_REG 0x02B00000
131 #define GPIO_GPIOEMU_REG 0x02B00004
132 #define GPIO_BINTEN_REG 0x02B00008
133 #define GPIO_DIR_REG 0x02B00010
134 #define GPIO_OUT_DATA_REG 0x02B00014
135 #define GPIO_SET_DATA_REG 0x02B00018
136 #define GPIO_CLEAR_DATA_REG 0x02B0001C
137 #define GPIO_IN_DATA_REG 0x02B00020
138 #define GPIO_SET_RIS_TRIG_REG 0x02B00024
139 #define GPIO_CLR_RIS_TRIG_REG 0x02B00028
140 #define GPIO_SET_FAL_TRIG_REG 0x02B0002C
141 #define GPIO_CLR_FAL_TRIG_REG 0x02B00030
143 /**
144 * @brief
145 * GPIO pin mapping
146 */
147 #define NAND_CLE_GPIO_PIN GPIO_8 // High: Command Cycle occuring
148 #define NAND_ALE_GPIO_PIN GPIO_9 // High: Address input cycle oddcuring
149 #define NAND_NWE_GPIO_PIN GPIO_10
150 #define NAND_NRE_GPIO_PIN GPIO_12
151 #define NAND_NCE_GPIO_PIN GPIO_13
152 #define NAND_MODE_GPIO GPIO_14
154 /**
155 * @brief
156 * The standard NAND delay must be big enough to handle the highest possible
157 * operating frequency of the device */
158 #define TARGET_NAND_STD_DELAY 25 // In cpu cycles
160 /**
161 * @brief
162 * The base address of the I2C peripheral, and the module divisor of the cpu clock
163 */
164 #define DEVICE_I2C_BASE 0x02b04000
165 #define DEVICE_I2C_MODULE_DIVISOR 6