1 /*
2 *
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
38 /**************************************************************************
39 * FILE PURPOSE: Target specific definitions
40 **************************************************************************
41 * FILE NAME: target.h
42 *
43 * DESCRIPTION: This file defines target specific values used by low level
44 * drivers.
45 *
46 * @file target.h
47 *
48 * @brief
49 * Low level target specific values are defined
50 *
51 ***************************************************************************/
54 /**
55 * @brief
56 * Device EMAC definitions
57 */
58 #define TARGET_DEVICE_CPMAC
60 #define TARGET_EMAC_N_PORTS 1
62 #define TARGET_EMAC_BASE_ADDRESSES { 0x02c80000u }
63 #define TARGET_EMAC_DSC_BASE_ADDR { 0x02c82000u }
65 #define TARGET_SGMII_BASE_ADDRESSES { 0x02c40000u }
67 /* SGMII offsets (at least the serdes configs, vary between devices, so
68 * they are defined here. */
69 #define TARGET_SGMII_IDVER 0x000
70 #define TARGET_SGMII_SOFT_RESET 0x004
71 #define TARGET_SGMII_CONTROL 0x010
72 #define TARGET_SGMII_STATUS 0x014
73 #define TARGET_SGMII_MR_ADV_ABILITY 0x018
74 #define TARGET_SGMII_MR_LP_ADV_ABILITY 0x020
75 #define TARGET_SGMII_TX_CFG 0x030
76 #define TARGET_SGMII_RX_CFG 0x034
77 #define TARGET_SGMII_AUX_CFG 0x038
79 /* Leave mdio disabled */
80 #define dev_mdio_open() 1
82 /* No chip level reset required for ethernet, the function call is made a void statment */
83 #define deviceSetEthResetState(x,y)
85 /* The mac control register values */
86 #define TARGET_MAC_CONTROL ( 1 << 18) /* EXT_EN */ \
87 | ( 0 << 9 ) /* Round robin */ \
88 | ( 1 << 7 ) /* GIG */ \
89 | ( 0 << 6 ) /* TX pacing disabled */ \
90 | ( 1 << 5 ) /* GMII RX & TX */ \
91 | ( 0 << 4 ) /* TX flow disabled */ \
92 | ( 0 << 3 ) /* RX flow disabled */ \
93 | ( 0 << 1 ) /* Loopback enabled */ \
94 | ( 1 << 0 ) /* full duplex */
97 /**
98 * @brief
99 * Device Timer definitions
100 */
101 #define TIMER0_BASE 0x02910000u
103 #define TIMER_INPUT_DIVIDER 6 /* Timer driven from cpu clock / 6 */
106 /**
107 * @def MAIN_PLL
108 */
109 #define MAIN_PLL 0 /**< The index to the main PLL */
112 /**
113 * @brief
114 * Device PLL definitions
115 */
116 #define DEVICE_PLL_BASE(x) ((x) == MAIN_PLL ? 0x29a0000 : 0)
119 /**
120 * @brief
121 * Device PSC definitions
122 */
123 #define DEVICE_PSC_BASE 0x02ac0000u
125 /**
126 * @brief
127 * The ethernet is in the always on domain */
128 #define TARGET_PWR_ETH(x) -1
130 /**
131 * @brief
132 * The nand is done through gpio, which is always powered up.
133 * A value < 0 tells the low level psc driver to simply return success
134 */
135 #define TARGET_PWR_NAND -1
137 /**
138 * @brief
139 * Flag to indicate timer 0 power up requested. The time is always on in the 6474
140 */
141 #define TARGET_PWR_TIMER_0 -1
144 /**
145 * @brief
146 * Device DDR controller definitions
147 */
148 #define DEVICE_DDR_BASE 0x70000000
150 /**
151 * @brief
152 * The highest module number
153 */
154 #define TARGET_PWR_MAX_MOD 5
157 /**
158 * @brief
159 * The base address of MDIO
160 */
161 #define TARGET_MDIO_BASE 0x2c81800
163 /**
164 * @brief
165 * GPIO address
166 */
167 #define GPIO_GPIOPID_REG 0x02B00000
168 #define GPIO_GPIOEMU_REG 0x02B00004
169 #define GPIO_BINTEN_REG 0x02B00008
170 #define GPIO_DIR_REG 0x02B00010
171 #define GPIO_OUT_DATA_REG 0x02B00014
172 #define GPIO_SET_DATA_REG 0x02B00018
173 #define GPIO_CLEAR_DATA_REG 0x02B0001C
174 #define GPIO_IN_DATA_REG 0x02B00020
175 #define GPIO_SET_RIS_TRIG_REG 0x02B00024
176 #define GPIO_CLR_RIS_TRIG_REG 0x02B00028
177 #define GPIO_SET_FAL_TRIG_REG 0x02B0002C
178 #define GPIO_CLR_FAL_TRIG_REG 0x02B00030
180 /**
181 * @brief
182 * GPIO pin mapping
183 */
184 #define NAND_CLE_GPIO_PIN GPIO_8 // High: Command Cycle occuring
185 #define NAND_ALE_GPIO_PIN GPIO_9 // High: Address input cycle oddcuring
186 #define NAND_NWE_GPIO_PIN GPIO_10
187 #define NAND_NRE_GPIO_PIN GPIO_12
188 #define NAND_NCE_GPIO_PIN GPIO_13
189 #define NAND_MODE_GPIO GPIO_14
191 /**
192 * @brief
193 * The standard NAND delay must be big enough to handle the highest possible
194 * operating frequency of the device */
195 #define TARGET_NAND_STD_DELAY 25 // In cpu cycles
197 /**
198 * @brief
199 * The base address of the I2C peripheral, and the module divisor of the cpu clock
200 */
201 #define DEVICE_I2C_BASE 0x02b04000
202 #define DEVICE_I2C_MODULE_DIVISOR 6