1 /**************************************************************************\r
2 * FILE PURPOSE: Target specific definitions\r
3 **************************************************************************\r
4 * FILE NAME: target.h\r
5 *\r
6 * DESCRIPTION: This file defines target specific values used by low level\r
7 * drivers.\r
8 *\r
9 * @file target.h\r
10 *\r
11 * @brief\r
12 * Low level target specific values are defined\r
13 *\r
14 ***************************************************************************/\r
15 \r
16 \r
17 /** \r
18 * @brief\r
19 * Device EMAC definitions\r
20 */\r
21 #define TARGET_DEVICE_CPMAC\r
22 \r
23 #define TARGET_EMAC_N_PORTS 1\r
24 \r
25 #define TARGET_EMAC_BASE_ADDRESSES { 0x02c80000u }\r
26 #define TARGET_EMAC_DSC_BASE_ADDR { 0x02c82000u }\r
27 \r
28 #define TARGET_SGMII_BASE_ADDRESSES { 0x02c40000u }\r
29 \r
30 /* SGMII offsets (at least the serdes configs, vary between devices, so\r
31 * they are defined here. */\r
32 #define TARGET_SGMII_IDVER 0x000\r
33 #define TARGET_SGMII_SOFT_RESET 0x004\r
34 #define TARGET_SGMII_CONTROL 0x010\r
35 #define TARGET_SGMII_STATUS 0x014\r
36 #define TARGET_SGMII_MR_ADV_ABILITY 0x018\r
37 #define TARGET_SGMII_MR_LP_ADV_ABILITY 0x020\r
38 #define TARGET_SGMII_TX_CFG 0x030\r
39 #define TARGET_SGMII_RX_CFG 0x034\r
40 #define TARGET_SGMII_AUX_CFG 0x038\r
41 \r
42 /* Leave mdio disabled */\r
43 #define dev_mdio_open() 1\r
44 \r
45 /* No chip level reset required for ethernet, the function call is made a void statment */\r
46 #define deviceSetEthResetState(x,y)\r
47 \r
48 /* The mac control register values */\r
49 #define TARGET_MAC_CONTROL ( 1 << 18) /* EXT_EN */ \\r
50 | ( 0 << 9 ) /* Round robin */ \\r
51 | ( 1 << 7 ) /* GIG */ \\r
52 | ( 0 << 6 ) /* TX pacing disabled */ \\r
53 | ( 1 << 5 ) /* GMII RX & TX */ \\r
54 | ( 0 << 4 ) /* TX flow disabled */ \\r
55 | ( 0 << 3 ) /* RX flow disabled */ \\r
56 | ( 0 << 1 ) /* Loopback enabled */ \\r
57 | ( 1 << 0 ) /* full duplex */\r
58 \r
59 \r
60 /**\r
61 * @brief\r
62 * Device Timer definitions\r
63 */\r
64 #define TIMER0_BASE 0x02910000u\r
65 \r
66 #define TIMER_INPUT_DIVIDER 6 /* Timer driven from cpu clock / 6 */\r
67 \r
68 \r
69 /**\r
70 * @def MAIN_PLL\r
71 */\r
72 #define MAIN_PLL 0 /**< The index to the main PLL */\r
73 \r
74 \r
75 /**\r
76 * @brief\r
77 * Device PLL definitions\r
78 */\r
79 #define DEVICE_PLL_BASE(x) ((x) == MAIN_PLL ? 0x29a0000 : 0)\r
80 \r
81 \r
82 /**\r
83 * @brief \r
84 * Device PSC definitions\r
85 */\r
86 #define DEVICE_PSC_BASE 0x02ac0000u\r
87 \r
88 /**\r
89 * @brief\r
90 * The ethernet is in the always on domain */\r
91 #define TARGET_PWR_ETH(x) -1\r
92 \r
93 /**\r
94 * @brief\r
95 * The nand is done through gpio, which is always powered up.\r
96 * A value < 0 tells the low level psc driver to simply return success\r
97 */\r
98 #define TARGET_PWR_NAND -1\r
99 \r
100 /**\r
101 * @brief\r
102 * Flag to indicate timer 0 power up requested. The time is always on in the 6474\r
103 */\r
104 #define TARGET_PWR_TIMER_0 -1\r
105 \r
106 \r
107 /**\r
108 * @brief\r
109 * Device DDR controller definitions\r
110 */\r
111 #define DEVICE_DDR_BASE 0x70000000\r
112 \r
113 /**\r
114 * @brief\r
115 * The highest module number\r
116 */\r
117 #define TARGET_PWR_MAX_MOD 5\r
118 \r
119 \r
120 /**\r
121 * @brief\r
122 * The base address of MDIO \r
123 */\r
124 #define TARGET_MDIO_BASE 0x2c81800\r
125 \r
126 /**\r
127 * @brief\r
128 * GPIO address\r
129 */\r
130 #define GPIO_GPIOPID_REG 0x02B00000\r
131 #define GPIO_GPIOEMU_REG 0x02B00004\r
132 #define GPIO_BINTEN_REG 0x02B00008\r
133 #define GPIO_DIR_REG 0x02B00010\r
134 #define GPIO_OUT_DATA_REG 0x02B00014\r
135 #define GPIO_SET_DATA_REG 0x02B00018\r
136 #define GPIO_CLEAR_DATA_REG 0x02B0001C\r
137 #define GPIO_IN_DATA_REG 0x02B00020\r
138 #define GPIO_SET_RIS_TRIG_REG 0x02B00024\r
139 #define GPIO_CLR_RIS_TRIG_REG 0x02B00028\r
140 #define GPIO_SET_FAL_TRIG_REG 0x02B0002C\r
141 #define GPIO_CLR_FAL_TRIG_REG 0x02B00030\r
142 \r
143 /**\r
144 * @brief\r
145 * GPIO pin mapping \r
146 */\r
147 #define NAND_CLE_GPIO_PIN GPIO_8 // High: Command Cycle occuring\r
148 #define NAND_ALE_GPIO_PIN GPIO_9 // High: Address input cycle oddcuring\r
149 #define NAND_NWE_GPIO_PIN GPIO_10\r
150 #define NAND_NRE_GPIO_PIN GPIO_12\r
151 #define NAND_NCE_GPIO_PIN GPIO_13\r
152 #define NAND_MODE_GPIO GPIO_14\r
153 \r
154 /**\r
155 * @brief\r
156 * The standard NAND delay must be big enough to handle the highest possible\r
157 * operating frequency of the device */\r
158 #define TARGET_NAND_STD_DELAY 25 // In cpu cycles\r
159 \r
160 /**\r
161 * @brief\r
162 * The base address of the I2C peripheral, and the module divisor of the cpu clock\r
163 */\r
164 #define DEVICE_I2C_BASE 0x02b04000\r
165 #define DEVICE_I2C_MODULE_DIVISOR 6\r
166 \r