1 /*
2 *
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
38 /**************************************************************************
39 * FILE PURPOSE: Target specific definitions
40 **************************************************************************
41 * FILE NAME: target.h
42 *
43 * DESCRIPTION: This file defines target specific values used by low level
44 * drivers.
45 *
46 * @file target.h
47 *
48 * @brief
49 * Low level target specific values are defined
50 *
51 ***************************************************************************/
52 #ifndef _TARGET_H
53 #define _TARGET_H
54 #include "types.h"
57 /**
58 * @brief
59 * Device EMAC definitions
60 */
63 /**
64 * @brief
65 * Device Timer definitions
66 */
67 #define TIMER0_BASE 0x02200000u
69 #define TIMER_INPUT_DIVIDER 6 /* Timer driven from cpu clock / 6 */
72 /**
73 * @def MAIN_PLL
74 */
75 #define MAIN_PLL 0 /**< The index to the main PLL */
77 /**
78 * @def NET_PLL
79 */
80 #define NET_PLL 1 /**< The index to the network PLL */
82 /**
83 * @def DDR_PLL
84 */
85 #define DDR_PLL 2 /**< The index to the DDR PLL */
88 /**
89 * @brief
90 * Device PLL definitions
91 */
92 #define DEVICE_PLL_BASE(x) ((x) == MAIN_PLL ? 0x2310000 : ((x) == NET_PLL ? 0x2620338 : 0x2620330))
93 #define DEVICE_MAIN_PLL_CTL_0 0x2620328
94 #define DEVICE_MAIN_PLL_CTL_1 0x262032c
97 /**
98 * @brief
99 * The c661x devices use a register external to the PLL controller for prediv configuration
100 */
101 #define chipPllExternalPrediv(x) TRUE
103 /**
104 * @brief
105 * Device PSC definitions
106 */
107 #define DEVICE_PSC_BASE 0x02350000u
109 /**
110 * @brief
111 * The SPI module base and module divider
112 */
113 #define DEVICE_SPI_BASE(x) 0x20bf0000u
114 #define DEVICE_SPI_MOD_DIVIDER 6
115 #define DEVICE_SPI_MAX_DIVIDER 0xff
117 /**
118 * @brief
119 * The PSC number for the PA sub-system */
120 #define TARGET_PWR_PA 7
122 /**
123 * @brief
124 * The PSC number for the SGMII */
125 #define TARGET_PWR_ETH(x) 8
127 /**
128 * @brief
129 * The PSC numbers for EMIF16 and SPI vary between devices. The devices are run time
130 * identified by reading the JTAG ID register
131 */
132 #define DEVICE_C6616_JTAG_ID_VAL 0x9d02f /* C6670 */
133 #define DEVICE_C6618_JTAG_ID_VAL 0x9e02f /* C6678 */
134 #define DEVICE_JTAG_ID_REG 0x2620018
137 /**
138 * @brief
139 * The PSC number for NAND depends on the device
140 */
141 #define TARGET_PWR_EMIF deviceEmifPscNum()
142 #define TARGET_PWR_EMIF_C6618 3
144 /*
145 * @brief
146 * The PSC number for SPI depends on the device
147 */
148 #define TARGET_PWR_SPI deviceSpiPscNum()
150 /**
151 * @brief
152 * The PSC number for GPIO. GPIO is in the always on domain
153 */
154 #define TARGET_PWR_GPIO -1
156 /**
157 * @brief
158 * Flag to indicate timer 0 power up requested. The time is always on in the 6472
159 */
160 #define TARGET_PWR_TIMER_0 -1
162 /**
163 * @brief
164 * Device DDR controller definitions
165 */
166 #define DEVICE_EMIF4_BASE 0x21000000
167 #define targetEmifType() ibl_EMIF_TYPE_40
169 /**
170 * @brief
171 * Device EMIF 2.5 controller definitions
172 */
173 #define DEVICE_EMIF25_BASE 0x20c00000
175 /**
176 * @brief
177 * NAND memory regions
178 */
179 #define TARGET_MEM_NAND_CS_2 0x70000000
180 #define TARGET_MEM_NAND_CS_3 0x74000000
181 #define TARGET_MEM_NAND_CS_4 0x78000000
182 #define TARGET_MEM_NAND_CS_5 0x7c000000
183 uint32 deviceNandMemBase (int32 cs);
184 #define TARGET_SHFL(x) _shfl(x) /* The shuffle intrinsic */
187 /**
188 * @brief
189 * The highest module number. The value for nyquist is used
190 */
191 #define TARGET_PWR_MAX_MOD 30
194 /**
195 * @brief
196 * The base address of MDIO
197 */
198 #define TARGET_MDIO_BASE 0x2090300
200 /**
201 * @brief
202 * The number of external ethernet ports
203 */
204 #define TARGET_EMAC_N_PORTS 2
208 /**
209 * @brief
210 * The base address of the I2C peripheral, and the module divisor of the cpu clock
211 */
212 #define DEVICE_I2C_BASE 0x02530000
213 #define DEVICE_I2C_MODULE_DIVISOR 6
215 /**
216 * @brief
217 * The address of the DEVSTAT register
218 */
219 #define DEVICE_REG_DEVSTAT 0x02620020
221 /**
222 * @brief
223 * Prototypes for the PLL functions handled outside the main PLL registers
224 */
225 SINT16 chipPllSetExternalPrediv(UINT16 pllNum, UINT32 predivRegVal);
226 SINT16 chipPllExternalBwAdj (UINT16 pllNum, UINT16 mult);
227 UINT32 chipPllExternalMult (UINT16 pllNum, UINT16 mult);
230 /**
231 * @brief
232 * Hardware network subsystem support, ethernet switch
233 */
234 #define DEVICE_CPSW
235 #define DEVICE_CPSW_NUM_PORTS 3 /* 3 switch ports */
236 #define DEVICE_CPSW_BASE (0x02090800)
237 #define targetGetSwitchCtl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
238 #define targetGetSwitchMaxPktSize() 9000
240 #define DEVICE_QM
241 #define DEVICE_QM_MANAGER_BASE 0x02a68000
242 #define DEVICE_QM_DESC_SETUP_BASE 0x02a6a000
243 #define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a20000
244 #define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02a40000
245 #define DEVICE_QM_QUEUE_STATUS_BASE 0x02a00000
246 #define DEVICE_QM_NUM_LINKRAMS 2
247 #define DEVICE_QM_NUM_MEMREGIONS 20
248 void *targetGetQmConfig(void);
249 void targetInitQs (void);
251 #define chipLmbd(x,y) _lmbd(x,y)
256 #define DEVICE_CPDMA
258 #define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
259 #define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
260 #define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
261 #define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
263 #define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
264 #define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
265 #define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
268 #define DEVICE_QM_FREE_Q 910
269 #define DEVICE_QM_LNK_BUF_Q 911
270 #define DEVICE_QM_RCV_Q 912
271 #define DEVICE_QM_TX_Q 913
272 #define DEVICE_QM_PA_CFG_Q 640
273 #define DEVICE_QM_ETH_TX_Q 648
275 #define DEVICE_RX_CDMA_TIMEOUT_COUNT 1000
279 #define DEVICE_PA
280 #define DEVICE_PA_BASE 0x02000000
281 #define DEVICE_PA_NUM_PDSPS 6
282 #define DEVICE_PA_RUN_CHECK_COUNT 100 /* Number of loops to verify PA firmware is running */
283 #define DEVICE_PA_PLL_BASE 0x02620338
284 #define chipLower8(x) ((x) & 0x00ff)
287 #define TARGET_SGMII_EXTERNAL_SERDES
288 #define TARGET_SGMII_TYPE_2 /* Use second sgmii setup sequence */
289 #define TARGET_SGMII_BASE_ADDRESSES { 0x02090100, 0x02090200 }
290 #define TARGET_SGMII_SERDES_BASE 0x2620340
291 #define TARGET_SGMII_SERDES_STATUS_BASE 0x2620158
292 #define TARGET_SGMII_SOFT_RESET 0x04
293 #define TARGET_SGMII_CONTROL 0x10
294 #define TARGET_SGMII_MR_ADV_ABILITY 0x18
295 void targetSgmiiSerdesConfig (int32 port, void *cfg);
296 #define chipKickOpenSerdes(x) *((uint32 *)0x2620038) = 0x83e70b13; *((uint32 *)0x262003c) = 0x95a4f1e0
297 #define chipKickClosedSerdes(x) ; /* never lock the registers */
298 #define TARGET_SERDES_LOCK_DELAY (1600*1000)
300 #define DEVICE_EMACSL_BASE(x) (0x02090900 + (x)*0x040)
301 #define DEVICE_N_GMACSL_PORTS 2
302 #define DEVICE_EMACSL_RESET_POLL_COUNT 100
303 Int32 targetMacSend (void *ptr_device, Uint8* buffer, int num_bytes);
304 Int32 targetMacRcv (void *ptr_device, UINT8 *buffer);
306 #define DEVICE_SS
307 #define DEVICE_PSTREAM_CFG_REG_ADDR 0x2000604
308 #define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0 0
309 #define hwConfigStreamingSwitch() DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0);
312 /**
313 * @brief
314 * Register access macros
315 */
316 #define DEVICE_REG32_W(x,y) *(volatile unsigned int *)(x)=(y)
317 #define DEVICE_REG32_R(x) (*(volatile unsigned int *)(x))
319 #define BOOTBITMASK(x,y) ( ( ( ((UINT32)1 << (((UINT32)x)-((UINT32)y)+(UINT32)1) ) - (UINT32)1 ) ) << ((UINT32)y) )
320 #define BOOT_READ_BITFIELD(z,x,y) (((UINT32)z) & BOOTBITMASK(x,y)) >> (y)
321 #define BOOT_SET_BITFIELD(z,f,x,y) (((UINT32)z) & ~BOOTBITMASK(x,y)) | ( (((UINT32)f) << (y)) & BOOTBITMASK(x,y) )
323 /**
324 * @brief
325 * Mpax configuration registers
326 */
327 #define DEVICE_REG_XMPAX_L(x) *((volatile unsigned int *)(0x08000000 + (8*(x))))
328 #define DEVICE_REG_XMPAX_H(x) *((volatile unsigned int *)(0x08000004 + (8*(x))))
331 /**
332 * @brief
333 * ROM boot loader boot modes and table locations
334 */
335 #define BOOT_MODE_I2C 40
336 #define BOOT_MODE_SPI 50
339 #define ROM_BOOT_PARAMS_ADDR_C6618 0x873680
340 #define ROM_BOOT_PARAMS_ADDR_C6616 0x8f3680
342 /**
343 * @brief
344 * No device specific configuration required for NOR boot, so
345 * the function call is defined to return success.
346 */
347 #define deviceConfigureForNor() 0
350 /**
351 * @brief
352 * Support for PLL workaround to re-enter ROM boot loader.
353 */
354 #define IBL_ENTER_ROM 1
356 /**
357 * @brief
358 * Support for enabling EDC for internal memory.
359 */
360 #define IBL_ENABLE_EDC 1
362 #endif /* _TARGET_H */