1 /**
2 * @file c66xutil.c
3 *
4 * @brief
5 * c66x functions used by both the ibl and utility programs
6 */
8 #include "device.h"
9 #include "target.h"
10 #include "pllapi.h"
11 #include "types.h"
13 /**
14 * @brief
15 * Configure the predivider for the main PLL, which resides outside the PLL controller
16 */
17 SINT16 chipPllSetExternalPrediv(UINT16 pllNum, UINT32 predivRegVal)
18 {
19 UINT32 reg;
21 reg = DEVICE_REG32_R (DEVICE_MAIN_PLL_CTL_0);
22 reg = BOOT_SET_BITFIELD(reg, predivRegVal, 5, 0);
23 DEVICE_REG32_W (DEVICE_MAIN_PLL_CTL_0, reg);
26 return (0);
28 } /* chipPllSetExternalPrediv */
31 /**
32 * @brief
33 * Configure the bandwidth adjustment for the main PLL, which resides outside the PLL controller
34 */
35 SINT16 chipPllExternalBwAdj (UINT16 pllNum, UINT16 mult)
36 {
37 UINT32 reg;
38 UINT32 bwAdj;
40 bwAdj = (mult >> 1) - 1;
42 reg = DEVICE_REG32_R (DEVICE_MAIN_PLL_CTL_0);
43 reg = BOOT_SET_BITFIELD(reg, bwAdj & 0x00ff, 31, 24);
44 DEVICE_REG32_W (DEVICE_MAIN_PLL_CTL_0, reg);
46 reg = DEVICE_REG32_R (DEVICE_MAIN_PLL_CTL_1);
47 reg = BOOT_SET_BITFIELD(reg, bwAdj >> 8, 3, 0);
48 DEVICE_REG32_W (DEVICE_MAIN_PLL_CTL_1, reg);
50 return (0);
52 } /* chipPllExternalBwAdj */
55 /**
56 * @brief
57 * Configure the multiplier fields for the main PLL which reside outside the PLL controller
58 */
59 UINT32 chipPllExternalMult (UINT16 pllNum, UINT16 mult)
60 {
61 UINT32 pmult;
62 UINT32 reg;
63 UINT32 v;
66 pmult = mult-1;
68 v = BOOT_READ_BITFIELD(pmult, 12, 6);
71 reg = DEVICE_REG32_R (DEVICE_MAIN_PLL_CTL_0);
72 reg = BOOT_SET_BITFIELD(reg, v, 18, 12);
73 DEVICE_REG32_W (DEVICE_MAIN_PLL_CTL_0, reg);
76 v = BOOT_READ_BITFIELD(pmult, 5, 0);
78 return (v);
80 } /* chipPllExternalMult */
82 /**
83 * @brief return the PSC module number for SPI
84 */
85 int32 deviceEMACPscNum (void)
86 {
87 uint32 v;
89 /* EMAC is module number 3 only on the c6657. */
90 v = *((Uint32 *)DEVICE_JTAG_ID_REG);
91 v &= DEVICE_JTAG_ID_MASK;
92 if (v == DEVICE_C6657_JTAG_ID_VAL)
93 return (3);
95 return (-1); /* A negative number indicates the always on domain */
96 }
98 /**
99 * @brief Power up a peripheral
100 *
101 * @details
102 * Boot peripherals are powered up
103 */
104 int32 devicePowerPeriph (int32 modNum)
105 {
106 int32 ret;
108 /* If the input value is < 0 there is nothing to power up */
109 if (modNum < 0)
110 return (0);
113 if (modNum >= TARGET_PWR_MAX_MOD)
114 return (-1);
117 return ((int32)pscEnableModule(modNum));
119 }
121 /*
122 * @brief
123 * Selects multiplexed GPIO's functionality
124 */
125 void configureGPIO(void)
126 {
127 uint32 reg;
129 reg = DEVICE_REG32_R (PIN_CONTROL_0);
130 reg = reg & 0x000f;
131 DEVICE_REG32_W (PIN_CONTROL_0, reg);
132 }
134 #ifdef PLL_REINIT_WORKAROUND
135 /**
136 * @brief Simple DDR3 test
137 *
138 * @details
139 * This function performs a simple DDR3 test for a memory range
140 * specified below and returns -1 for failure and 0 for success.
141 */
144 UINT32 ddr3_memory_test (void)
145 {
146 UINT32 index, value;
148 /* Write a pattern */
149 for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
150 *(VUint32 *) index = (UINT32)index;
151 }
153 /* Read and check the pattern */
154 for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
156 value = *(UINT32 *) index;
158 if (value != index) {
159 return -1;
160 }
161 }
163 /* Write a pattern for complementary values */
164 for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
165 *(VUint32 *) index = (UINT32)~index;
166 }
168 /* Read and check the pattern */
169 for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
171 value = *(UINT32 *) index;
173 if (value != ~index) {
174 return -1;
175 }
176 }
178 return 0;
179 }
181 #endif