1 /*
2 *
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
38 /************************************************************************************
39 * FILE PURPOSE: C66x Device Specific functions
40 ************************************************************************************
41 * FILE NAME: c66x.c
42 *
43 * DESCRIPTION: Implements the device specific functions for the IBL
44 *
45 * @file c66x.c
46 *
47 * @brief
48 * This file implements the device specific functions for the IBL
49 *
50 ************************************************************************************/
51 #include "ibl.h"
52 #include "iblloc.h"
53 #include "iblcfg.h"
54 #include "device.h"
55 #include "pllapi.h"
56 #include "emif31api.h"
57 #include "pscapi.h"
58 #include "gpio.h"
59 #include "qm_api.h"
60 #include "cpdma_api.h"
61 #include "pa_api.h"
62 #include "serdes_api.h"
63 #include "net.h"
64 #include "nandhwapi.h"
65 #include "nor_api.h"
66 #include "spi_api.h"
67 #include <string.h>
68 #include <stdint.h>
69 #include "target.h"
70 #include "uart.h"
72 #define PLL_DDR_INIT_LOOPMAX 10
73 #define IBL_RESULT_CODE_STR_LEN 20
74 #define IBL_RESULT_CODE_LOC 17
76 extern cregister unsigned int DNUM;
78 /**
79 * @brief Determine if an address is local
80 *
81 * @details
82 * Examines an input address to determine if it is a local address. Using the largest
83 * L2 size on the C6670.
84 */
85 bool address_is_local (Uint32 addr)
86 {
87 /* L2 */
88 if ((addr >= 0x00800000) && (addr < 0x00900000))
89 return (TRUE);
91 /* L1P */
92 if ((addr >= 0x00e00000) && (addr < 0x00e08000))
93 return (TRUE);
95 /* L2D */
96 if ((addr >= 0x00f00000) && (addr < 0x00f08000))
97 return (TRUE);
99 return (FALSE);
101 }
104 /**
105 * @brief Convert a local l1d, l1p or l2 address to a global address
106 *
107 * @details
108 * The global address is formed. If the address is not local then
109 * the input address is returned
110 */
111 Uint32 deviceLocalAddrToGlobal (Uint32 addr)
112 {
114 if (address_is_local (addr))
115 addr = (1 << 28) | (DNUM << 24) | addr;
117 return (addr);
119 }
122 /**
123 * @brief
124 * Enable the DDR
125 *
126 * @details
127 * The DDR controller on the c66x is an emif 4.0. The controller is
128 * initialized directly with the supplied values
129 */
130 void deviceDdrConfig (void)
131 {
132 uint32 loopcount=0;
133 int8 ddr_result_code_str[IBL_RESULT_CODE_STR_LEN] = "IBL Result code 0";
134 /* The emif registers must be made visible. MPAX mapping 2 is used */
135 DEVICE_REG_XMPAX_L(2) = 0x10000000 | 0xff; /* replacement addr + perm*/
136 DEVICE_REG_XMPAX_H(2) = 0x2100000B; /* base addr + seg size (64KB)*/
138 if (ibl.ddrConfig.configDdr != 0)
139 hwEmif4p0Enable (&ibl.ddrConfig.uEmif.emif4p0);
141 #ifdef PLL_REINIT_WORKAROUND
142 for (loopcount = 0; loopcount < PLL_DDR_INIT_LOOPMAX; loopcount++)
143 {
144 /* Calling MAIN, PA, DDR PLL init */
145 if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
146 hwPllSetPll (MAIN_PLL,
147 ibl.pllConfig[ibl_MAIN_PLL].prediv,
148 ibl.pllConfig[ibl_MAIN_PLL].mult,
149 ibl.pllConfig[ibl_MAIN_PLL].postdiv);
151 if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE)
152 hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL),
153 ibl.pllConfig[ibl_NET_PLL].prediv,
154 ibl.pllConfig[ibl_NET_PLL].mult,
155 ibl.pllConfig[ibl_NET_PLL].postdiv,
156 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
157 ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz);
159 if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
160 hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),
161 ibl.pllConfig[ibl_DDR_PLL].prediv,
162 ibl.pllConfig[ibl_DDR_PLL].mult,
163 ibl.pllConfig[ibl_DDR_PLL].postdiv,
164 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
165 ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);
167 if (ibl.ddrConfig.configDdr != 0)
168 hwEmif4p0Enable (&ibl.ddrConfig.uEmif.emif4p0);
170 if (ddr3_memory_test() == 0)
171 {
172 break;
173 }
174 }
175 /* Init UART again because we are re-initializing the PLL's */
176 uart_init();
178 if (loopcount < 10)
179 {
180 ddr_result_code_str[IBL_RESULT_CODE_LOC] = loopcount + '0';
181 }
182 else if ((loopcount >= 10) && (loopcount < 35))
183 {
184 ddr_result_code_str[IBL_RESULT_CODE_LOC] = loopcount + 'A';
185 }
186 else
187 {
188 ddr_result_code_str[IBL_RESULT_CODE_LOC] = loopcount + 'Z';
189 }
191 if (loopcount == PLL_DDR_INIT_LOOPMAX)
192 {
193 uart_write_string("IBL: DDR INITIALIZATION FAILED",0);
194 }
195 else
196 {
197 uart_write_string("IBL: PLL and DDR Initialization Complete",0);
198 }
199 uart_write_string(ddr_result_code_str,0);
200 #endif
201 }
205 /**
206 * @brief Enable EMIF25 or SPI interface to the NAND
207 *
208 */
209 int32 deviceConfigureForNand(void)
210 {
212 return (0);
214 }
216 /**
217 * @brief
218 * Return the base memory address for emif25 in a given chip select space
219 */
220 uint32 deviceEmif25MemBase (int32 cs)
221 {
222 switch (cs) {
224 case 2: return (TARGET_MEM_NAND_CS_2);
226 case 3: return (TARGET_MEM_NAND_CS_3);
228 case 4: return (TARGET_MEM_NAND_CS_4);
230 case 5: return (TARGET_MEM_NAND_CS_5);
232 }
234 return (0xffffffff);
236 }
239 /**
240 * @brief
241 * Return the PSC number for NAND/NOR through emif. Only 6678 has the emif
242 */
243 Int32 deviceEmifPscNum (void)
244 {
245 Uint32 v;
247 v = *((Uint32 *)DEVICE_JTAG_ID_REG);
248 v &= DEVICE_JTAG_ID_MASK;
249 if (v == DEVICE_C6678_JTAG_ID_VAL)
250 return (TARGET_PWR_EMIF_C6678);
252 /* Return a negative number to indicate no PSC module is associated with NAND */
253 return (-1);
255 }
259 /**
260 * @brief
261 * The e-fuse mac address is loaded
262 */
263 void deviceLoadDefaultEthAddress (uint8 *maddr)
264 {
265 uint32 macA, macB;
267 /* Read the e-fuse mac address */
268 macA = *((uint32 *)0x2620110);
269 macB = *((uint32 *)0x2620114);
271 maddr[0] = (macB >> 8) & 0xff;
272 maddr[1] = (macB >> 0) & 0xff;
273 maddr[2] = (macA >> 24) & 0xff;
274 maddr[3] = (macA >> 16) & 0xff;
275 maddr[4] = (macA >> 8) & 0xff;
276 maddr[5] = (macA >> 0) & 0xff;
277 }
280 /**
281 * @brief
282 * Compile time queue manager information
283 */
284 #define DEVICE_NUM_RX_CPPIS 1
285 #define DEVICE_NUM_TX_CPPIS 1
286 #define DEVICE_NUM_CPPIS (DEVICE_NUM_RX_CPPIS + DEVICE_NUM_TX_CPPIS)
288 /* The linking RAM */
289 #pragma DATA_SECTION(qm_linkram_buf, ".linkram")
290 #pragma DATA_ALIGN(qm_linkram_buf, 16)
291 uint8 qm_linkram_buf[DEVICE_NUM_CPPIS * 2 * (sizeof(uint32)/sizeof(uint8))];
294 /* The CPPI RAM */
295 #pragma DATA_SECTION(qm_cppi_buf, ".cppi")
296 #pragma DATA_ALIGN(qm_cppi_buf, 16)
297 uint8 qm_cppi_buf[QM_DESC_SIZE_BYTES * DEVICE_NUM_CPPIS];
300 /* The rx data buffers */
301 #pragma DATA_SECTION(qm_buffer, ".mac_buffer")
302 #pragma DATA_ALIGN(qm_buffer, 16)
303 uint8 qm_buffer[MAX_SIZE_STREAM_BUFFER * DEVICE_NUM_RX_CPPIS];
305 const qmConfig_t qmConfig = {
306 (UINT32) qm_linkram_buf,
307 sizeof (qm_cppi_buf),
308 (UINT32) qm_cppi_buf,
310 DEVICE_NUM_CPPIS,
311 DEVICE_QM_FREE_Q
312 };
314 /**
315 * @brief
316 * Return the queue manager memory configuration information
317 */
318 void *targetGetQmConfig (void)
319 {
320 return ((void *)&qmConfig);
321 }
323 /**
324 * @brief
325 * Attach a packet buffer to each descriptor and push onto the linked buffer queue
326 */
327 void targetInitQs (void)
328 {
329 int32 i;
330 qmHostDesc_t *hd;
332 for (i = 0; i < DEVICE_NUM_RX_CPPIS; i++) {
334 hd = hwQmQueuePop (DEVICE_QM_FREE_Q);
335 hd->buffLen = sizeof (qm_buffer) / DEVICE_NUM_CPPIS;
336 hd->buffPtr = (UINT32) &(qm_buffer[MAX_SIZE_STREAM_BUFFER * i]);
337 hd->nextBDPtr = 0;
338 hd->origBufferLen = MAX_SIZE_STREAM_BUFFER;
339 hd->origBuffPtr = hd->buffPtr;
341 hwQmQueuePush (hd, DEVICE_QM_LNK_BUF_Q, QM_DESC_SIZE_BYTES);
343 }
346 for (i = 0; i < DEVICE_NUM_TX_CPPIS; i++) {
348 hd = hwQmQueuePop (DEVICE_QM_FREE_Q);
349 hd->buffLen = 0;
350 hd->buffPtr = 0;
351 hd->nextBDPtr = 0;
352 hd->origBufferLen = 0;
353 hd->origBuffPtr = 0;
355 hwQmQueuePush (hd, DEVICE_QM_TX_Q, QM_DESC_SIZE_BYTES);
357 }
360 }
364 const cpdmaRxCfg_t cpdmaEthRxCfg = {
366 DEVICE_PA_CDMA_RX_CHAN_CFG_BASE, /* Base address of PA CPDMA rx config registers */
367 DEVICE_PA_CDMA_RX_NUM_CHANNELS, /* Number of rx channels */
369 DEVICE_PA_CDMA_RX_FLOW_CFG_BASE, /* Base address of PA CPDMA rx flow registers */
370 DEVICE_PA_CDMA_RX_NUM_FLOWS, /* Number of rx flows */
372 0, /* Queue manager for descriptor / buffer for received packets */
373 DEVICE_QM_LNK_BUF_Q, /* Queue of descriptors /buffers for received packets */
375 0, /* Queue manager for received packets */
376 DEVICE_QM_RCV_Q, /* Queue for received packets (overridden by PA) */
378 DEVICE_RX_CDMA_TIMEOUT_COUNT /* Teardown maximum loop wait */
379 };
382 /**
383 * @brief
384 * Return the cpdma configuration information
385 */
386 void *targetGetCpdmaRxConfig (void)
387 {
388 return ((void *)&cpdmaEthRxCfg);
390 }
393 const cpdmaTxCfg_t cpdmaEthTxCfg = {
395 DEVICE_PA_CDMA_GLOBAL_CFG_BASE, /* Base address of global config registers */
396 DEVICE_PA_CDMA_TX_CHAN_CFG_BASE, /* Base address of PA CPDMA tx config registers */
397 DEVICE_PA_CDMA_TX_NUM_CHANNELS /* Number of tx channels */
399 };
402 /**
403 * @brief
404 * return the tx cpdma configuration information
405 */
406 void *targetGetCpdmaTxConfig (void)
407 {
408 return ((void *)&cpdmaEthTxCfg);
410 }
412 /**
413 * @brief
414 * Configure the PA
415 */
416 void targetPaConfig (uint8 *macAddr)
417 {
418 paConfig_t paCfg;
419 qmHostDesc_t *hd;
420 SINT16 ret;
422 /* Filter everything except the desired mac address and the broadcast mac */
423 paCfg.mac0ms = ((uint32)macAddr[0] << 24) | ((uint32)macAddr[1] << 16) | ((uint32)macAddr[2] << 8) | (uint32)(macAddr[3]);
424 paCfg.mac0ls = ((uint32)macAddr[4] << 24) | ((uint32)macAddr[5] << 16);
426 paCfg.mac1ms = 0xffffffff;
427 paCfg.mac1ls = 0xffff0000;
429 paCfg.rxQnum = DEVICE_QM_RCV_Q;
431 /* Form the configuration command in a buffer linked to a descriptor */
432 hd = hwQmQueuePop (DEVICE_QM_LNK_BUF_Q);
433 paCfg.cmdBuf = (uint8 *)hd->origBuffPtr;
435 ret = hwPaEnable (&paCfg);
436 if (ret != 0) {
437 iblStatus.iblFail = ibl_FAIL_CODE_PA;
438 return;
439 }
442 /* Send the command to the PA through the QM */
443 hd->softwareInfo0 = PA_MAGIC_ID;
444 hd->buffLen = 16;
445 QM_DESC_DESCINFO_SET_PKT_LEN(hd->descInfo, 16);
447 /* Set the return Queue */
448 QM_DESC_PINFO_SET_QM (hd->packetInfo, 0);
449 QM_DESC_PINFO_SET_QUEUE (hd->packetInfo, DEVICE_QM_LNK_BUF_Q);
451 hwQmQueuePush (hd, DEVICE_QM_PA_CFG_Q, QM_DESC_SIZE_BYTES);
454 }
456 /**
457 * @brief
458 * Chip level SGMII serdes configuration
459 *
460 * @details
461 * Both lanes are always setup, regardless of the port value
462 */
463 void targetSgmiiSerdesConfig (int32 port, void *viblSgmii)
464 {
465 serdesConfig_t scfg;
466 iblSgmii_t *sgmii = (iblSgmii_t *)viblSgmii;
468 scfg.cfg = sgmii->auxConfig;
469 scfg.nLanes = 2;
470 scfg.rxCfg[0] = scfg.rxCfg[1] = sgmii->rxConfig;
471 scfg.txCfg[0] = scfg.txCfg[1] = sgmii->txConfig;
473 hwSerdesConfig (TARGET_SGMII_SERDES_BASE, &scfg);
475 hwSerdesWaitLock (TARGET_SGMII_SERDES_STATUS_BASE);
477 }
480 Int32 targetMacSend (void *vptr_device, Uint8* buffer, int num_bytes)
481 {
482 qmHostDesc_t *hd;
483 NET_DRV_DEVICE *ptr_device = (NET_DRV_DEVICE *)vptr_device;
484 int i;
487 /* Must always setup the descriptor to have the minimum packet length */
488 if (num_bytes < 64)
489 num_bytes = 64;
492 for (i = 0, hd = NULL; hd == NULL; i++, chipDelay32 (1000))
493 hd = hwQmQueuePop (DEVICE_QM_TX_Q);
495 if (hd == NULL)
496 return (-1);
498 QM_DESC_DESCINFO_SET_PKT_LEN(hd->descInfo, num_bytes);
500 hd->buffLen = num_bytes;
501 hd->origBufferLen = num_bytes;
503 hd->buffPtr = deviceLocalAddrToGlobal((UINT32)buffer);
504 hd->origBuffPtr = deviceLocalAddrToGlobal((UINT32)buffer);
507 /* Return the descriptor back to the transmit queue */
508 QM_DESC_PINFO_SET_QM(hd->packetInfo, 0);
509 QM_DESC_PINFO_SET_QUEUE(hd->packetInfo, DEVICE_QM_TX_Q);
511 hwQmQueuePush (hd, DEVICE_QM_ETH_TX_Q, QM_DESC_SIZE_BYTES);
513 return (0);
515 }
518 Int32 targetMacRcv (void *vptr_device, UINT8 *buffer)
519 {
520 Int32 pktSizeBytes;
521 qmHostDesc_t *hd;
522 NET_DRV_DEVICE *ptr_device = (NET_DRV_DEVICE *)vptr_device;
524 hd = hwQmQueuePop (DEVICE_QM_RCV_Q);
525 if (hd == NULL)
526 return (0);
528 pktSizeBytes = QM_DESC_DESCINFO_GET_PKT_LEN(hd->descInfo);
529 iblMemcpy ((void *)buffer, (void *)hd->buffPtr, pktSizeBytes);
531 hd->buffLen = hd->origBufferLen;
532 hd->buffPtr = hd->origBuffPtr;
534 hwQmQueuePush (hd, DEVICE_QM_LNK_BUF_Q, QM_DESC_SIZE_BYTES);
536 return (pktSizeBytes);
538 }
540 void targetFreeQs (void)
541 {
542 qmHostDesc_t *hd;
544 do {
546 hd = hwQmQueuePop (DEVICE_QM_FREE_Q);
548 } while (hd != NULL);
550 do {
552 hd = hwQmQueuePop (DEVICE_QM_LNK_BUF_Q);
554 } while (hd != NULL);
556 do {
558 hd = hwQmQueuePop (DEVICE_QM_RCV_Q);
560 } while (hd != NULL);
562 do {
564 hd = hwQmQueuePop (DEVICE_QM_TX_Q);
566 } while (hd != NULL);
568 }
570 extern nandCtbl_t nandEmifCtbl;
571 /**
572 * @brief Return the NAND interface (GPIO, EMIF25 or SPI) used based on the value
573 * of interface
574 */
575 #ifndef EXCLUDE_NAND_GPIO
576 nandCtbl_t nandGpioCtbl = {
578 nandHwGpioDriverInit,
579 nandHwGpioDriverReadBytes,
580 nandHwGpioDriverReadPage,
581 nandHwGpioDriverClose
583 };
584 #endif
586 #ifndef EXCLUDE_NAND_EMIF
587 extern Int32 nandHwEmifDriverInit (int32 cs, void *vdevInfo);
588 extern Int32 nandHwEmifDriverReadBytes (Uint32 block, Uint32 page, Uint32 byte, Uint32 nbytes, Uint8 *data);
589 extern Int32 nandHwEmifDriverReadPage (Uint32 block, Uint32 page, Uint8 *data);
590 extern Int32 nandHwEmifDriverClose (void);
592 nandCtbl_t nandEmifCtbl = {
594 nandHwEmifDriverInit,
595 nandHwEmifDriverReadBytes,
596 nandHwEmifDriverReadPage,
597 nandHwEmifDriverClose
599 };
600 #endif
602 #ifndef EXCLUDE_NAND_SPI
603 nandCtbl_t nandSpiCtbl = {
606 nandHwSpiDriverInit,
607 nandHwSpiDriverReadBytes,
608 nandHwSpiDriverReadPage,
609 nandHwSpiDriverClose
611 };
612 #endif
614 nandCtbl_t *deviceGetNandCtbl (int32 interface)
615 {
616 #ifndef EXCLUDE_NAND_GPIO
618 if (interface == ibl_PMEM_IF_GPIO)
619 return (&nandGpioCtbl);
621 #endif
623 #ifndef EXCLUDE_NAND_SPI
625 if (interface == ibl_PMEM_IF_SPI)
626 return (&nandSpiCtbl);
628 #endif
630 #ifndef EXCLUDE_NAND_EMIF
632 if ((interface >= ibl_PMEM_IF_CHIPSEL_2) && (interface <= ibl_PMEM_IF_CHIPSEL_5))
633 return (&nandEmifCtbl);
635 #endif
637 return (NULL);
639 }
642 /**
643 * @brief
644 * Get the nor call table for the specified nor interface
645 */
647 #ifndef EXCLUDE_NOR_EMIF
648 norCtbl_t norEmifCtbl = {
650 norHwEmifDriverInit,
651 norHwEmifDriverReadBytes,
652 norHwEmifDriverClose
654 };
656 #endif
658 #ifndef EXCLUDE_NOR_SPI
660 norCtbl_t norSpiCtbl = {
662 norHwSpiDriverInit,
663 norHwSpiDriverReadBytes,
664 norHwSpiDriverClose
666 };
668 #endif
670 norCtbl_t *deviceGetNorCtbl (int32 interface)
671 {
673 #ifndef EXCLUDE_NOR_SPI
675 if (interface == ibl_PMEM_IF_SPI)
676 return (&norSpiCtbl);
678 #endif
680 #ifndef EXCLUDE_NOR_EMIF
682 if ((interface >= ibl_PMEM_IF_CHIPSEL_2) && (interface <= ibl_PMEM_IF_CHIPSEL_5))
683 return (&norEmifCtbl);
685 #endif
687 return (NULL);
689 }