1 /*
2 *
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
38 /**************************************************************************
39 * FILE PURPOSE: Target specific definitions
40 **************************************************************************
41 * FILE NAME: target.h
42 *
43 * DESCRIPTION: This file defines target specific values used by low level
44 * drivers.
45 *
46 * @file target.h
47 *
48 * @brief
49 * Low level target specific values are defined
50 *
51 ***************************************************************************/
52 #ifndef _TARGET_H
53 #define _TARGET_H
54 #include "types.h"
57 /**
58 * @brief
59 * Device EMAC definitions
60 */
63 /**
64 * @brief
65 * Device Timer definitions
66 */
67 #define TIMER0_BASE 0x02200000u
69 #define TIMER_INPUT_DIVIDER 6 /* Timer driven from cpu clock / 6 */
72 /**
73 * @def MAIN_PLL
74 */
75 #define MAIN_PLL 0 /**< The index to the main PLL */
77 /**
78 * @def NET_PLL
79 */
80 #define NET_PLL 1 /**< The index to the network PLL */
82 /**
83 * @def DDR_PLL
84 */
85 #define DDR_PLL 2 /**< The index to the DDR PLL */
88 /**
89 * @brief
90 * Device PLL definitions
91 */
92 #define DEVICE_PLL_BASE(x) ((x) == MAIN_PLL ? 0x2310000 : ((x) == NET_PLL ? 0x2620338 : 0x2620330))
93 #define DEVICE_MAIN_PLL_CTL_0 0x2620328
94 #define DEVICE_MAIN_PLL_CTL_1 0x262032c
97 /**
98 * @brief
99 * The c66x devices use a register external to the PLL controller for prediv configuration
100 */
101 #define chipPllExternalPrediv(x) TRUE
103 /**
104 * @brief
105 * Device PSC definitions
106 */
107 #define DEVICE_PSC_BASE 0x02350000u
109 /**
110 * @brief
111 * The SPI module base and module divider
112 */
113 #define DEVICE_SPI_BASE(x) 0x20bf0000u
114 #define DEVICE_SPI_MOD_DIVIDER 6
115 #define DEVICE_SPI_MAX_DIVIDER 0xff
117 /**
118 * @brief
119 * The PSC number for the PA sub-system */
120 #define TARGET_PWR_PA 7
122 /**
123 * @brief
124 * The PSC number for the SGMII */
125 #define TARGET_PWR_ETH(x) 8
127 /**
128 * @brief
129 * The PSC numbers for EMIF16 and SPI vary between devices. The devices are run time
130 * identified by reading the JTAG ID register,
131 * NOTE: Have the variant bits as zero while defining the JTAG ID
132 */
133 #define DEVICE_C6678_JTAG_ID_VAL 0x9e02f /* C6678 */
134 #define DEVICE_C6670_JTAG_ID_VAL 0xb94102f /* C6670 */
136 #define DEVICE_JTAG_ID_REG 0x2620018
137 #define DEVICE_JTAG_ID_MASK 0x0fffffff /* exclude variant bits(31:28) */
140 /**
141 * @brief
142 * The PSC number for NAND depends on the device
143 */
144 #define TARGET_PWR_EMIF deviceEmifPscNum()
145 #define TARGET_PWR_EMIF_C6678 3
147 /*
148 * @brief
149 * The PSC number for SPI depends on the device
150 */
151 #define TARGET_PWR_SPI deviceSpiPscNum()
153 /**
154 * @brief
155 * The PSC number for GPIO. GPIO is in the always on domain
156 */
157 #define TARGET_PWR_GPIO -1
159 /**
160 * @brief
161 * The LPSC number for PCIe. PCIe is 10 for C6678/C6770
162 */
163 #define TARGET_PWR_PCIE 10
165 /**
166 * @brief
167 * Flag to indicate timer 0 power up requested. The time is always on in the 6472
168 */
169 #define TARGET_PWR_TIMER_0 -1
171 /**
172 * @brief
173 * Device DDR controller definitions
174 */
175 #define DEVICE_EMIF4_BASE 0x21000000
176 #define targetEmifType() ibl_EMIF_TYPE_40
178 /**
179 * @brief
180 * Device EMIF 2.5 controller definitions
181 */
182 #define DEVICE_EMIF25_BASE 0x20c00000
184 /**
185 * @brief
186 * NAND memory regions
187 */
188 #define TARGET_MEM_NAND_CS_2 0x70000000
189 #define TARGET_MEM_NAND_CS_3 0x74000000
190 #define TARGET_MEM_NAND_CS_4 0x78000000
191 #define TARGET_MEM_NAND_CS_5 0x7c000000
192 uint32 deviceNandMemBase (int32 cs);
193 #define TARGET_SHFL(x) _shfl(x) /* The shuffle intrinsic */
196 /**
197 * @brief
198 * The highest module number. The value for nyquist is used
199 */
200 #define TARGET_PWR_MAX_MOD 30
203 /**
204 * @brief
205 * The base address of MDIO
206 */
207 #define TARGET_MDIO_BASE 0x2090300
209 /**
210 * @brief
211 * The number of external ethernet ports
212 */
213 #define TARGET_EMAC_N_PORTS 2
215 /**
216 * @brief
217 * GPIO address
218 */
219 #define GPIO_GPIOPID_REG 0x02320000
220 #define GPIO_GPIOEMU_REG 0x02320004
221 #define GPIO_BINTEN_REG 0x02320008
222 #define GPIO_DIR_REG 0x02320010
223 #define GPIO_OUT_DATA_REG 0x02320014
224 #define GPIO_SET_DATA_REG 0x02320018
225 #define GPIO_CLEAR_DATA_REG 0x0232001C
226 #define GPIO_IN_DATA_REG 0x02320020
227 #define GPIO_SET_RIS_TRIG_REG 0x02320024
228 #define GPIO_CLR_RIS_TRIG_REG 0x02320028
229 #define GPIO_SET_FAL_TRIG_REG 0x0232002C
230 #define GPIO_CLR_FAL_TRIG_REG 0x02320030
232 /**
233 * @brief
234 * The base address of the I2C peripheral, and the module divisor of the cpu clock
235 */
236 #define DEVICE_I2C_BASE 0x02530000
237 #define DEVICE_I2C_MODULE_DIVISOR 6
239 /**
240 * @brief
241 * The address of the DEVSTAT register
242 */
243 #define DEVICE_REG_DEVSTAT 0x02620020
245 /**
246 * @brief
247 * Prototypes for the PLL functions handled outside the main PLL registers
248 */
249 SINT16 chipPllSetExternalPrediv(UINT16 pllNum, UINT32 predivRegVal);
250 SINT16 chipPllExternalBwAdj (UINT16 pllNum, UINT16 mult);
251 UINT32 chipPllExternalMult (UINT16 pllNum, UINT16 mult);
254 /**
255 * @brief
256 * Hardware network subsystem support, ethernet switch
257 */
258 #define DEVICE_CPSW
259 #define DEVICE_CPSW_NUM_PORTS 3 /* 3 switch ports */
260 #define DEVICE_CPSW_BASE (0x02090800)
261 #define targetGetSwitchCtl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
262 #define targetGetSwitchMaxPktSize() 9000
264 #define DEVICE_QM
265 #define DEVICE_QM_MANAGER_BASE 0x02a68000
266 #define DEVICE_QM_DESC_SETUP_BASE 0x02a6a000
267 #define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a20000
268 #define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02a40000
269 #define DEVICE_QM_QUEUE_STATUS_BASE 0x02a00000
270 #define DEVICE_QM_NUM_LINKRAMS 2
271 #define DEVICE_QM_NUM_MEMREGIONS 20
272 void *targetGetQmConfig(void);
273 void targetInitQs (void);
275 #define chipLmbd(x,y) _lmbd(x,y)
280 #define DEVICE_CPDMA
282 #define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
283 #define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
284 #define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
285 #define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
287 #define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
288 #define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
289 #define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
292 #define DEVICE_QM_FREE_Q 910
293 #define DEVICE_QM_LNK_BUF_Q 911
294 #define DEVICE_QM_RCV_Q 912
295 #define DEVICE_QM_TX_Q 913
296 #define DEVICE_QM_PA_CFG_Q 640
297 #define DEVICE_QM_ETH_TX_Q 648
299 #define DEVICE_RX_CDMA_TIMEOUT_COUNT 1000
303 #define DEVICE_PA
304 #define DEVICE_PA_BASE 0x02000000
305 #define DEVICE_PA_NUM_PDSPS 6
306 #define DEVICE_PA_RUN_CHECK_COUNT 100 /* Number of loops to verify PA firmware is running */
307 #define DEVICE_PA_PLL_BASE 0x02620338
308 #define chipLower8(x) ((x) & 0x00ff)
311 #define TARGET_SGMII_EXTERNAL_SERDES
312 #define TARGET_SGMII_TYPE_2 /* Use second sgmii setup sequence */
313 #define TARGET_SGMII_BASE_ADDRESSES { 0x02090100, 0x02090200 }
314 #define TARGET_SGMII_SERDES_BASE 0x2620340
315 #define TARGET_SGMII_SERDES_STATUS_BASE 0x2620158
316 #define TARGET_SGMII_SOFT_RESET 0x04
317 #define TARGET_SGMII_CONTROL 0x10
318 #define TARGET_SGMII_MR_ADV_ABILITY 0x18
319 void targetSgmiiSerdesConfig (int32 port, void *cfg);
320 #define chipKickOpenSerdes(x) *((uint32 *)0x2620038) = 0x83e70b13; *((uint32 *)0x262003c) = 0x95a4f1e0
321 #define chipKickClosedSerdes(x) ; /* never lock the registers */
322 #define TARGET_SERDES_LOCK_DELAY (1600*1000)
324 #define DEVICE_EMACSL_BASE(x) (0x02090900 + (x)*0x040)
325 #define DEVICE_N_GMACSL_PORTS 2
326 #define DEVICE_EMACSL_RESET_POLL_COUNT 100
327 Int32 targetMacSend (void *ptr_device, Uint8* buffer, int num_bytes);
328 Int32 targetMacRcv (void *ptr_device, UINT8 *buffer);
330 #define DEVICE_SS
331 #define DEVICE_PSTREAM_CFG_REG_ADDR 0x2000604
332 #define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0 0
333 #define hwConfigStreamingSwitch() DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0);
335 #define ECC_BLOCK_SIZE 256
337 /* NAND address pack macro */
338 #define PACK_ADDR(col, page, block) \
339 ((col & 0x000000ff) | ((page & 0x0000001f) << 9) | ((block & 0x00000fff) << 14))
341 /**
342 * @brief
343 * Register access macros
344 */
345 #define DEVICE_REG32_W(x,y) *(volatile unsigned int *)(x)=(y)
346 #define DEVICE_REG32_R(x) (*(volatile unsigned int *)(x))
348 #define BOOTBITMASK(x,y) ( ( ( ((UINT32)1 << (((UINT32)x)-((UINT32)y)+(UINT32)1) ) - (UINT32)1 ) ) << ((UINT32)y) )
349 #define BOOT_READ_BITFIELD(z,x,y) (((UINT32)z) & BOOTBITMASK(x,y)) >> (y)
350 #define BOOT_SET_BITFIELD(z,f,x,y) (((UINT32)z) & ~BOOTBITMASK(x,y)) | ( (((UINT32)f) << (y)) & BOOTBITMASK(x,y) )
352 /**
353 * @brief
354 * Mpax configuration registers
355 */
356 #define DEVICE_REG_XMPAX_L(x) *((volatile unsigned int *)(0x08000000 + (8*(x))))
357 #define DEVICE_REG_XMPAX_H(x) *((volatile unsigned int *)(0x08000004 + (8*(x))))
360 /**
361 * @brief
362 * ROM boot loader boot modes and table locations
363 */
364 #define BOOT_MODE_I2C 40
365 #define BOOT_MODE_SPI 50
368 #define ROM_BOOT_PARAMS_ADDR_C6678 0x873680
369 #define ROM_BOOT_PARAMS_ADDR_C6670 0x8f3680
371 /**
372 * @brief
373 * No device specific configuration required for NOR boot, so
374 * the function call is defined to return success.
375 */
376 #define deviceConfigureForNor() 0
379 /****************************************************************
380 *
381 * NOTE: Following build flags enable DEVICE specific workarounds
382 * and have code which is specific to C6670/C6678 LC EVMs
383 *
384 ****************************************************************/
386 /**
387 * @brief
388 * Support for PLL workaround to re-enter ROM boot loader.
389 */
390 #define IBL_ENTER_ROM 1
392 /**
393 * @brief
394 * Support for enabling EDC for internal memory.
395 */
396 #define IBL_ENABLE_EDC 1
398 /**
399 * @brief
400 * Support for enabling PCIe workarond for C6678/C6670.
401 */
402 #define IBL_ENABLE_PCIE_WORKAROUND 1
404 /**
405 * @brief
406 * DDR start and end address needed for DDR memory test
407 */
408 #define DDR3_TEST_START_ADDRESS 0x80000000
409 #define DDR3_TEST_END_ADDRESS (DDR3_TEST_START_ADDRESS + (128 *1024))
411 /**
412 * @brief
413 * Software workaround for DDR3 memory corruption is to re-init the PLL's and DDR controller. This flag enables the workaround
414 */
415 #define PLL_REINIT_WORKAROUND
417 UINT32 ddr3_memory_test();
418 #endif /* _TARGET_H */