1 /*
2 *
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
38 /**************************************************************************
39 * FILE PURPOSE: Target specific definitions
40 **************************************************************************
41 * FILE NAME: target.h
42 *
43 * DESCRIPTION: This file defines target specific values used by low level
44 * drivers.
45 *
46 * @file target.h
47 *
48 * @brief
49 * Low level target specific values are defined
50 *
51 ***************************************************************************/
52 #ifndef _TARGET_H
53 #define _TARGET_H
54 #include "types.h"
55 #include <stdint.h>
56 #include <stdio.h>
57 #include <string.h>
58 #include <stdlib.h>
61 /**
62 * @brief
63 * Device EMAC definitions
64 */
67 /**
68 * @brief
69 * Device Timer definitions
70 */
71 #define TIMER0_BASE 0x02200000u
73 #define TIMER_INPUT_DIVIDER 6 /* Timer driven from cpu clock / 6 */
76 /**
77 * @def MAIN_PLL
78 */
79 #define MAIN_PLL 0 /**< The index to the main PLL */
81 /**
82 * @def NET_PLL
83 */
84 #define NET_PLL 1 /**< The index to the network PLL */
86 /**
87 * @def DDR_PLL
88 */
89 #define DDR_PLL 2 /**< The index to the DDR PLL */
92 /**
93 * @brief
94 * Device PLL definitions
95 */
96 #define DEVICE_PLL_BASE(x) ((x) == MAIN_PLL ? 0x2310000 : ((x) == NET_PLL ? 0x2620338 : 0x2620330))
97 #define DEVICE_MAIN_PLL_CTL_0 0x2620328
98 #define DEVICE_MAIN_PLL_CTL_1 0x262032c
101 /**
102 * @brief
103 * The c66x devices use a register external to the PLL controller for prediv configuration
104 */
105 #define chipPllExternalPrediv(x) TRUE
107 /**
108 * @brief
109 * Device PSC definitions
110 */
111 #define DEVICE_PSC_BASE 0x02350000u
113 /**
114 * @brief
115 * The SPI module base and module divider
116 */
117 #define DEVICE_SPI_BASE(x) 0x20bf0000u
118 #define DEVICE_SPI_MOD_DIVIDER 6
119 #define DEVICE_SPI_MAX_DIVIDER 0xff
121 /**
122 * @brief
123 * The PSC number for the PA sub-system */
124 #define TARGET_PWR_PA 7
126 /**
127 * @brief
128 * The PSC number for the SGMII */
129 #define TARGET_PWR_ETH(x) 8
131 /**
132 * @brief
133 * The PSC numbers for EMIF16 and SPI vary between devices. The devices are run time
134 * identified by reading the JTAG ID register,
135 * NOTE: Have the variant bits as zero while defining the JTAG ID
136 */
137 #define DEVICE_C6678_JTAG_ID_VAL 0x9e02f /* C6678 */
138 #define DEVICE_C6670_JTAG_ID_VAL 0xb94102f /* C6670 */
140 #define DEVICE_JTAG_ID_REG 0x2620018
141 #define DEVICE_JTAG_ID_MASK 0x0fffffff /* exclude variant bits(31:28) */
144 /**
145 * @brief
146 * The PSC number for NAND depends on the device
147 */
148 #define TARGET_PWR_EMIF deviceEmifPscNum()
149 #define TARGET_PWR_EMIF_C6678 3
151 /*
152 * @brief
153 * The PSC number for SPI depends on the device
154 */
155 #define TARGET_PWR_SPI deviceSpiPscNum()
157 /**
158 * @brief
159 * The PSC number for GPIO. GPIO is in the always on domain
160 */
161 #define TARGET_PWR_GPIO -1
163 /**
164 * @brief
165 * The LPSC number for PCIe. PCIe is 10 for C6678/C6770
166 */
167 #define TARGET_PWR_PCIE 10
169 /**
170 * @brief
171 * Flag to indicate timer 0 power up requested. The time is always on in the 6472
172 */
173 #define TARGET_PWR_TIMER_0 -1
175 /**
176 * @brief
177 * Device DDR controller definitions
178 */
179 #define DEVICE_EMIF4_BASE 0x21000000
180 #define targetEmifType() ibl_EMIF_TYPE_40
182 /**
183 * @brief
184 * Device EMIF 2.5 controller definitions
185 */
186 #define DEVICE_EMIF25_BASE 0x20c00000
188 /**
189 * @brief
190 * NAND memory regions
191 */
192 #define TARGET_MEM_NAND_CS_2 0x70000000
193 #define TARGET_MEM_NAND_CS_3 0x74000000
194 #define TARGET_MEM_NAND_CS_4 0x78000000
195 #define TARGET_MEM_NAND_CS_5 0x7c000000
196 uint32 deviceNandMemBase (int32 cs);
197 #define TARGET_SHFL(x) _shfl(x) /* The shuffle intrinsic */
200 /**
201 * @brief
202 * The highest module number. The value for nyquist is used
203 */
204 #define TARGET_PWR_MAX_MOD 30
207 /**
208 * @brief
209 * The base address of MDIO
210 */
211 #define TARGET_MDIO_BASE 0x2090300
213 /**
214 * @brief
215 * The number of external ethernet ports
216 */
217 #define TARGET_EMAC_N_PORTS 2
219 /**
220 * @brief
221 * GPIO address
222 */
223 #define GPIO_GPIOPID_REG 0x02320000
224 #define GPIO_GPIOEMU_REG 0x02320004
225 #define GPIO_BINTEN_REG 0x02320008
226 #define GPIO_DIR_REG 0x02320010
227 #define GPIO_OUT_DATA_REG 0x02320014
228 #define GPIO_SET_DATA_REG 0x02320018
229 #define GPIO_CLEAR_DATA_REG 0x0232001C
230 #define GPIO_IN_DATA_REG 0x02320020
231 #define GPIO_SET_RIS_TRIG_REG 0x02320024
232 #define GPIO_CLR_RIS_TRIG_REG 0x02320028
233 #define GPIO_SET_FAL_TRIG_REG 0x0232002C
234 #define GPIO_CLR_FAL_TRIG_REG 0x02320030
236 /**
237 * @brief
238 * The base address of the I2C peripheral, and the module divisor of the cpu clock
239 */
240 #define DEVICE_I2C_BASE 0x02530000
241 #define DEVICE_I2C_MODULE_DIVISOR 6
243 /**
244 * @brief
245 * The address of the DEVSTAT register
246 */
247 #define DEVICE_REG_DEVSTAT 0x02620020
249 /**
250 * @brief
251 * Prototypes for the PLL functions handled outside the main PLL registers
252 */
253 SINT16 chipPllSetExternalPrediv(UINT16 pllNum, UINT32 predivRegVal);
254 SINT16 chipPllExternalBwAdj (UINT16 pllNum, UINT16 mult);
255 UINT32 chipPllExternalMult (UINT16 pllNum, UINT16 mult);
258 /**
259 * @brief
260 * Hardware network subsystem support, ethernet switch
261 */
262 #define DEVICE_CPSW
263 #define DEVICE_CPSW_NUM_PORTS 3 /* 3 switch ports */
264 #define DEVICE_CPSW_BASE (0x02090800)
265 #define targetGetSwitchCtl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
266 #define targetGetSwitchMaxPktSize() 9000
268 #define DEVICE_QM
269 #define DEVICE_QM_MANAGER_BASE 0x02a68000
270 #define DEVICE_QM_DESC_SETUP_BASE 0x02a6a000
271 #define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a20000
272 #define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02a40000
273 #define DEVICE_QM_QUEUE_STATUS_BASE 0x02a00000
274 #define DEVICE_QM_NUM_LINKRAMS 2
275 #define DEVICE_QM_NUM_MEMREGIONS 20
276 void *targetGetQmConfig(void);
277 void targetInitQs (void);
279 #define chipLmbd(x,y) _lmbd(x,y)
284 #define DEVICE_CPDMA
286 #define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
287 #define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
288 #define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
289 #define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
291 #define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
292 #define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
293 #define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
296 #define DEVICE_QM_FREE_Q 910
297 #define DEVICE_QM_LNK_BUF_Q 911
298 #define DEVICE_QM_RCV_Q 912
299 #define DEVICE_QM_TX_Q 913
300 #define DEVICE_QM_PA_CFG_Q 640
301 #define DEVICE_QM_ETH_TX_Q 648
303 #define DEVICE_RX_CDMA_TIMEOUT_COUNT 1000
307 #define DEVICE_PA
308 #define DEVICE_PA_BASE 0x02000000
309 #define DEVICE_PA_NUM_PDSPS 6
310 #define DEVICE_PA_RUN_CHECK_COUNT 100 /* Number of loops to verify PA firmware is running */
311 #define DEVICE_PA_PLL_BASE 0x02620338
312 #define chipLower8(x) ((x) & 0x00ff)
315 #define TARGET_SGMII_EXTERNAL_SERDES
316 #define TARGET_SGMII_TYPE_2 /* Use second sgmii setup sequence */
317 #define TARGET_SGMII_BASE_ADDRESSES { 0x02090100, 0x02090200 }
318 #define TARGET_SGMII_SERDES_BASE 0x2620340
319 #define TARGET_SGMII_SERDES_STATUS_BASE 0x2620158
320 #define TARGET_SGMII_SOFT_RESET 0x04
321 #define TARGET_SGMII_CONTROL 0x10
322 #define TARGET_SGMII_MR_ADV_ABILITY 0x18
323 void targetSgmiiSerdesConfig (int32 port, void *cfg);
324 #define chipKickOpenSerdes(x) *((uint32 *)0x2620038) = 0x83e70b13; *((uint32 *)0x262003c) = 0x95a4f1e0
325 #define chipKickClosedSerdes(x) ; /* never lock the registers */
326 #define TARGET_SERDES_LOCK_DELAY (1600*1000)
328 #define DEVICE_EMACSL_BASE(x) (0x02090900 + (x)*0x040)
329 #define DEVICE_N_GMACSL_PORTS 2
330 #define DEVICE_EMACSL_RESET_POLL_COUNT 100
331 Int32 targetMacSend (void *ptr_device, Uint8* buffer, int num_bytes);
332 Int32 targetMacRcv (void *ptr_device, UINT8 *buffer);
334 #define DEVICE_SS
335 #define DEVICE_PSTREAM_CFG_REG_ADDR 0x2000604
336 #define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0 0
337 #define hwConfigStreamingSwitch() DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0);
339 #define ECC_BLOCK_SIZE 256
341 /* NAND address pack macro */
342 #define PACK_ADDR(col, page, block) \
343 ((col & 0x000000ff) | ((page & 0x0000001f) << 9) | ((block & 0x00000fff) << 14))
345 /**
346 * @brief
347 * Register access macros
348 */
349 #define DEVICE_REG32_W(x,y) *(volatile unsigned int *)(x)=(y)
350 #define DEVICE_REG32_R(x) (*(volatile unsigned int *)(x))
352 #define BOOTBITMASK(x,y) ( ( ( ((UINT32)1 << (((UINT32)x)-((UINT32)y)+(UINT32)1) ) - (UINT32)1 ) ) << ((UINT32)y) )
353 #define BOOT_READ_BITFIELD(z,x,y) (((UINT32)z) & BOOTBITMASK(x,y)) >> (y)
354 #define BOOT_SET_BITFIELD(z,f,x,y) (((UINT32)z) & ~BOOTBITMASK(x,y)) | ( (((UINT32)f) << (y)) & BOOTBITMASK(x,y) )
356 /**
357 * @brief
358 * Mpax configuration registers
359 */
360 #define DEVICE_REG_XMPAX_L(x) *((volatile unsigned int *)(0x08000000 + (8*(x))))
361 #define DEVICE_REG_XMPAX_H(x) *((volatile unsigned int *)(0x08000004 + (8*(x))))
364 /**
365 * @brief
366 * ROM boot loader boot modes and table locations
367 */
368 #define BOOT_MODE_I2C 40
369 #define BOOT_MODE_SPI 50
372 #define ROM_BOOT_PARAMS_ADDR_C6678 0x873680
373 #define ROM_BOOT_PARAMS_ADDR_C6670 0x8f3680
375 /**
376 * @brief
377 * No device specific configuration required for NOR boot, so
378 * the function call is defined to return success.
379 */
380 #define deviceConfigureForNor() 0
383 /****************************************************************
384 *
385 * NOTE: Following build flags enable DEVICE specific workarounds
386 * and have code which is specific to C6670/C6678 LC EVMs
387 *
388 ****************************************************************/
390 /**
391 * @brief
392 * Support for PLL workaround to re-enter ROM boot loader.
393 */
394 #define IBL_ENTER_ROM 1
396 /**
397 * @brief
398 * Support for enabling EDC for internal memory.
399 */
400 #define IBL_ENABLE_EDC 1
402 /**
403 * @brief
404 * Support for enabling PCIe workarond for C6678/C6670.
405 */
406 #define IBL_ENABLE_PCIE_WORKAROUND 1
408 /**
409 * @brief
410 * DDR start and end address needed for DDR memory test
411 */
412 #define DDR3_TEST_START_ADDRESS 0x80000000
413 #define DDR3_TEST_END_ADDRESS (DDR3_TEST_START_ADDRESS + (128 *1024))
415 /**
416 * @brief
417 * Software workaround for DDR3 memory corruption is to re-init the PLL's and DDR controller. This flag enables the workaround
418 */
419 #define DDR3_TEST_ENABLE
421 extern int32_t ddr3_memory_test();
423 #endif /* _TARGET_H */