C66x: remove DDR3 PLL config
[keystone-rtos/ibl.git] / src / hw / ddrs / emif4 / emif4.c
1 /*************************************************************************************************
2  * FILE PURPOSE: EMIF4 driver
3  *************************************************************************************************
4  * FILE NAME: emif4.c
5  *
6  * DESCRIPTION: The boot emif4 driver
7  *
8  *************************************************************************************************/
9 #include "types.h"
10 #include "ibl.h"
11 #include "emif4_api.h"
12 #include "emif4_loc.h"
13 #include "device.h"
15 #define CHIP_LEVEL_REG  0x02620000
17 #define KICK0                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0038)
18 #define KICK1                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x003C)
19 #define KICK0_UNLOCK            0x83e70b13
20 #define KICK1_UNLOCK            0x95a4f1e0
22 // DDR3 definitions
23 #define DDR_BASE_ADDR 0x21000000
25 #define DDR_MIDR               (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000000))
26 #define DDR_SDCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000008))
27 #define DDR_SDRFC              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000010))
28 #define DDR_SDTIM1             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000018))
29 #define DDR_SDTIM2             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000020))
30 #define DDR_SDTIM3             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000028))
31 #define DDR_PMCTL              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000038))
32 #define DDR_RDWR_LVL_RMP_CTRL  (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
33 #define DDR_RDWR_LVL_CTRL      (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
34 #define DDR_DDRPHYC            (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000E4))
35 #define DDR_ZQCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000C8))
37 #define DATA0_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262043C))
38 #define DATA1_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620440))
39 #define DATA2_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620444))
40 #define DATA3_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620448))
41 #define DATA4_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262044C))
42 #define DATA5_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620450))
43 #define DATA6_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620454))
44 #define DATA7_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620458))
45 #define DATA8_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262045C))
47 #define DATA0_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262040C))
48 #define DATA1_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620410))
49 #define DATA2_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620414))
50 #define DATA3_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620418))
51 #define DATA4_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262041C))
52 #define DATA5_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620420))
53 #define DATA6_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620424))
54 #define DATA7_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620428))
55 #define DATA8_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262042C))
57 #define RDWR_INIT_RATIO_0       (*(volatile unsigned int*)(0x0262040C))
58 #define RDWR_INIT_RATIO_1       (*(volatile unsigned int*)(0x02620410))
59 #define RDWR_INIT_RATIO_2       (*(volatile unsigned int*)(0x02620414))
60 #define RDWR_INIT_RATIO_3       (*(volatile unsigned int*)(0x02620418))
61 #define RDWR_INIT_RATIO_4       (*(volatile unsigned int*)(0x0262041C))
62 #define RDWR_INIT_RATIO_5       (*(volatile unsigned int*)(0x02620420))
63 #define RDWR_INIT_RATIO_6       (*(volatile unsigned int*)(0x02620424))
64 #define RDWR_INIT_RATIO_7       (*(volatile unsigned int*)(0x02620428))
65 #define RDWR_INIT_RATIO_8       (*(volatile unsigned int*)(0x0262042C))
68 #define DDR3_CONFIG_REG_0   (*(volatile unsigned int*)(0x02620404))
69 #define DDR3_CONFIG_REG_12  (*(volatile unsigned int*)(0x02620434))
70 #define DDR3_CONFIG_REG_13  (*(volatile unsigned int*)(0x02620460))
71 #define DDR3_CONFIG_REG_23  (*(volatile unsigned int*)(0x02620460))
72 #define DDR3_CONFIG_REG_24  (*(volatile unsigned int*)(0x02620464))
74 #define RD_DQS_SLAVE_RATIO 0x34
75 #define WR_DQS_SLAVE_RATIO 0xA9
76 #define WR_DATA_SLAVE_RATIO 0xE9
77 #define FIFO_WE_SLAVE_RATIO 0x106
80 static void ddr3_wait (uint32 del)
81 {
82     volatile unsigned int i;
84     for (i = 0; i < del; i++);
86 }
88 /*************************************************************************************************
89  * FUNCTION PUROPSE: Initial EMIF4 setup
90  *************************************************************************************************
91  * DESCRIPTION: Emif configuration
92  *************************************************************************************************/
93 SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
94 {
95     UINT32 v, i, TEMP;
96     
97     v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
98     v &= DEVICE_JTAG_ID_MASK;
99     
100     if ( (v == DEVICE_C6678_JTAG_ID_VAL) ||
101          (v == DEVICE_C6670_JTAG_ID_VAL) )
102     {
105         KICK0 = KICK0_UNLOCK;
106         KICK1 = KICK1_UNLOCK;
108         /**************** 3.0 Leveling Register Configuration ********************/
109         /* Using partial automatic leveling due to errata */
110         
111        /**************** 3.2 Invert Clock Out ********************/
112         DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
113         DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
114         DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
115         DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15
116         DDR3_CONFIG_REG_23 |= 0x00000200;    //Set bit 9 = 1 to use forced ratio leveling for read DQS
117             
118        //Values with invertclkout = 1
119       /**************** 3.3+3.4 Partial Automatic Leveling ********************/
120       DATA0_WRLVL_INIT_RATIO = 0x5E;
121       DATA1_WRLVL_INIT_RATIO = 0x5E;
122       DATA2_WRLVL_INIT_RATIO = 0x5E;
123       DATA3_WRLVL_INIT_RATIO = 0x51;
124       DATA4_WRLVL_INIT_RATIO = 0x38;
125       DATA5_WRLVL_INIT_RATIO = 0x3A;
126       DATA6_WRLVL_INIT_RATIO = 0x24;
127       DATA7_WRLVL_INIT_RATIO = 0x20;
128       DATA8_WRLVL_INIT_RATIO = 0x44;
130       DATA0_GTLVL_INIT_RATIO = 0xDD;
131       DATA1_GTLVL_INIT_RATIO = 0xDD;
132       DATA2_GTLVL_INIT_RATIO = 0xBE;
133       DATA3_GTLVL_INIT_RATIO = 0xCA;
134       DATA4_GTLVL_INIT_RATIO = 0xA9;
135       DATA5_GTLVL_INIT_RATIO = 0xA7;
136       DATA6_GTLVL_INIT_RATIO = 0x9E;
137       DATA7_GTLVL_INIT_RATIO = 0xA1;
138       DATA8_GTLVL_INIT_RATIO = 0xBA;
139   
140       //Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0
141       DDR_DDRPHYC &= ~(0x00008000);
142       DDR_DDRPHYC |= (0x00008000);
143       DDR_DDRPHYC &= ~(0x00008000);
145       /***************** 2.3 Basic Controller and DRAM configuration ************/
146       DDR_SDRFC    = 0x00005162;    // enable configuration 
148       /* DDR_SDTIM1   = 0x1113783C; */
149        TEMP = 0;
150        TEMP |= 0x8 << 25; // T_RP bit field 28:25
151        TEMP |= 0x8 << 21; // T_RCD bit field 24:21
152        TEMP |= 0x9 << 17; // T_WR bit field 20:17
153        TEMP |= 0x17 << 12; // T_RAS bit field 16:12
154        TEMP |= 0x20 << 6; // T_RC bit field 11:6
155        TEMP |= 0x7 << 3; // T_RRD bit field 5:3
156        TEMP |= 0x4; // T_WTR bit field 2:0
157        DDR_SDTIM1 = TEMP;
159       /* DDR_SDTIM2   = 0x304F7FE3; */
160        TEMP = 0;
161        TEMP |= 0x3 << 28; // T_XP bit field 30:28
162        TEMP |= 0x4f << 16; // T_XSNR bit field 24:16
163        TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6
164        TEMP |= 0x4 << 3; // T_RTP bit field 5:3
165        TEMP |= 0x3; // T_CKE bit field 2:0
166        DDR_SDTIM2 = TEMP;
168       /*  DDR_SDTIM3   = 0x559F849F; */
169        TEMP = 0;
170        TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)
171        TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)
172        TEMP |= 0x4 << 21; // T_CKESR bit field 23:21
173        TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15
174        TEMP |= 0x49 << 4; // T_RFC bit field 12:4
175        TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value)
176        DDR_SDTIM3 = TEMP; 
178         DDR_DDRPHYC  = 0x0010010F;
179      
180         DDR_ZQCFG    = 0x70073214; 
182         DDR_PMCTL    = 0x0;
183      
184         DDR_SDRFC = 0x00005162; // enable configuration
186         /* DDR_SDCFG    = 0x63062A32; */
187         /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32;    // last config write DRAM init occurs */
188          TEMP = 0;
189          TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)
190          TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27
191          TEMP |= 0x3 << 24; // DDR_TERM bit field 26:24
192          TEMP |= 0x0 << 21; // DYN_ODT bit field 22:21
193          TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18
194          TEMP |= 0x2 << 16; // CWL bit field 17:16
195          TEMP |= 0x0 << 14; // NM bit field 15:14
196          TEMP |= 0xA << 10; // CL bit field 13:10
197          TEMP |= 0x4 << 7; // ROWSIZE bit field 9:7
198          TEMP |= 0x3 << 4; // IBANK bit field 6:4
199          TEMP |= 0x0 << 3; // EBANK bit field 3:3
200          TEMP |= 0x2; // PAGESIZE bit field 2:0
201          DDR_SDCFG = TEMP;
203         for (i = 0; i < 12000; i++) {
204                 ddr3_wait(1000);             //Wait 600us for HW init to complete
205         }
207         DDR_SDRFC = 0x00001450;       //Refresh rate = (7.8*666MHz]
209         DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
210    
211         /*Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value
212           Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.
213           Actual time = ~10-15 ms */
214         DDR_RDWR_LVL_CTRL = 0x80000000; 
216         for (i = 0; i < 30000; i++) {
217                 ddr3_wait(1000); //Wait 3ms for leveling to complete
218         }
219     }
220     else
221     {
222         /* C64x configuration */
223         /* If the config registers or refresh control registers are being written
224          * disable the initialization sequence until they are all setup */
225         if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0)  {
226             
227             v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
228             EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
229             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
230         }
231         
232         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
233             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
234         
235         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
236             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
237         
238         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
239             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
240         
241         if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
242             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
243         
244         if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
245             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
246         
247         if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
248             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
249         
250         if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
251             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
252         
253         if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
254             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
255         
256         if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
257             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
258         
259         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
260             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
261         
262         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
263             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
264         
265         if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
266             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
267         
268         if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
269             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
270         
271         if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
272             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
273         
274         if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
275             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
276         
277         if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
278             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
279         
280         if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
281             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
282         
283         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
284             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
285         
286         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
287             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
288         
289         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
290             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
291         
292         if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
293             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
294         
295         /* Allow the configuration to occur */
296         v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
297         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
298         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
299         
300         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
301             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
302         
303         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
304             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
305         
306         v = cfg->sdRamRefreshCtl;
307         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
308         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
309     }
310     
311     return (0);
313 } /* hwEmif4p0Enable */