src/hw/ddrs/emif4/emif4.c

   1 /*************************************************************************************************
   2  * FILE PURPOSE: EMIF4 driver
   3  *************************************************************************************************
   4  * FILE NAME: emif4.c
   5  *
   6  * DESCRIPTION: The boot emif4 driver
   7  *
   8  *************************************************************************************************/
   9 #include "types.h"
  10 #include "ibl.h"
  11 #include "emif4_api.h"
  12 #include "emif4_loc.h"
  13 #include "device.h"
  14
  15 #define CHIP_LEVEL_REG  0x02620000
  16
  17 #define KICK0                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0038)
  18 #define KICK1                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x003C)
  19
  20 #define DDR3PLLCTL0             *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330)
  21 #define DDR3PLLCTL1             *(unsigned int*)(CHIP_LEVEL_REG + 0x0334)
  22
  23 // DDR3 definitions
  24 #define DDR_BASE_ADDR 0x21000000
  25
  26 #define DDR_MIDR               (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000000))
  27 #define DDR_SDCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000008))
  28 #define DDR_SDRFC              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000010))
  29 #define DDR_SDTIM1             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000018))
  30 #define DDR_SDTIM2             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000020))
  31 #define DDR_SDTIM3             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000028))
  32 #define DDR_PMCTL              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000038))
  33 #define DDR_RDWR_LVL_RMP_CTRL  (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
  34 #define DDR_RDWR_LVL_CTRL      (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
  35 #define DDR_DDRPHYC            (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000E4))
  36
  37 #define DATA0_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262043C))
  38 #define DATA1_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620440))
  39 #define DATA2_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620444))
  40 #define DATA3_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620448))
  41 #define DATA4_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262044C))
  42 #define DATA5_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620450))
  43 #define DATA6_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620454))
  44 #define DATA7_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620458))
  45 #define DATA8_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262045C))
  46
  47 #define RDWR_INIT_RATIO_0       (*(volatile unsigned int*)(0x0262040C))
  48 #define RDWR_INIT_RATIO_1       (*(volatile unsigned int*)(0x02620410))
  49 #define RDWR_INIT_RATIO_2       (*(volatile unsigned int*)(0x02620414))
  50 #define RDWR_INIT_RATIO_3       (*(volatile unsigned int*)(0x02620418))
  51 #define RDWR_INIT_RATIO_4       (*(volatile unsigned int*)(0x0262041C))
  52 #define RDWR_INIT_RATIO_5       (*(volatile unsigned int*)(0x02620420))
  53 #define RDWR_INIT_RATIO_6       (*(volatile unsigned int*)(0x02620424))
  54 #define RDWR_INIT_RATIO_7       (*(volatile unsigned int*)(0x02620428))
  55 #define RDWR_INIT_RATIO_8       (*(volatile unsigned int*)(0x0262042C))
  56
  57 #define DDR3_CONFIG_REG_0   (*(volatile unsigned int*)(0x02620404))
  58 #define DDR3_CONFIG_REG_12  (*(volatile unsigned int*)(0x02620434))
  59 #define DDR3_CONFIG_REG_13  (*(volatile unsigned int*)(0x02620460))
  60 #define DDR3_CONFIG_REG_23  (*(volatile unsigned int*)(0x02620460))
  61 #define DDR3_CONFIG_REG_24  (*(volatile unsigned int*)(0x02620464))
  62
  63 #define RD_DQS_SLAVE_RATIO 0x34
  64 #define WR_DQS_SLAVE_RATIO 0xA9
  65 #define WR_DATA_SLAVE_RATIO 0xE9
  66 #define FIFO_WE_SLAVE_RATIO 0x106
  67
  68 /*************************************************************************************************
  69  * FUNCTION PUROPSE: Initial EMIF4 setup
  70  *************************************************************************************************
  71  * DESCRIPTION: Emif configuration
  72  *************************************************************************************************/
  73 SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
  74 {
  75     UINT32 v, i;
  76
  77 #if 0
  78     /* If the config registers or refresh control registers are being written
  79      * disable the initialization sequence until they are all setup */
  80     if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0)  {
  81
  82         v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
  83         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
  84         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
  85     }
  86
  87     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
  88         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
  89
  90     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
  91         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
  92
  93     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
  94         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
  95
  96     if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
  97         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
  98
  99     if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
 100         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
 101
 102     if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
 103         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
 104
 105     if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
 106         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
 107
 108     if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
 109         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
 110
 111     if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
 112         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
 113
 114     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
 115         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
 116
 117     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
 118         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
 119
 120     if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
 121         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
 122
 123     if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
 124         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
 125
 126     if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
 127         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
 128
 129     if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
 130         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
 131
 132     if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
 133         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
 134
 135     if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
 136         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
 137
 138     if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
 139         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
 140
 141     if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
 142         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
 143
 144     if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
 145         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
 146
 147     if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
 148         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
 149
 150     /* Allow the configuration to occur */
 151     v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
 152     EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
 153     DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
 154
 155     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
 156         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
 157
 158     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
 159         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
 160
 161     v = cfg->sdRamRefreshCtl;
 162     EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
 163     DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
 164 #endif
 165
 166     v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
 167
 168     /*KICK0 = 0x83E70B13;
 169     KICK1 = 0x95A4F1E0;*/
 170
 171     if (v == DEVICE_C6618_JTAG_ID_VAL)
 172     {
 173         DDR3PLLCTL0 = 0x100807C1;
 174
 175         DDR_SDTIM1   = 0x0CCF369B;
 176         DDR_SDTIM2   = 0x3A3F7FDA;
 177         DDR_SDTIM3   = 0x057F83A8;
 178         DDR_PMCTL   |= (0x9 << 4); // Set up SR_TIM to Enter self-refresh after 4096 clocks
 179
 180         DDR_DDRPHYC  = 0x0010010B;
 181
 182         DDR_SDRFC = 0x00004111; //500us
 183
 184
 185         DDR_SDCFG    = 0x63C51A32; //0x63C51A32;    //row-col = 13-10
 186
 187
 188         //Values with invertclkout = 0
 189         DATA0_GTLVL_INIT_RATIO = 0x3C;
 190         DATA1_GTLVL_INIT_RATIO = 0x3C;
 191         DATA2_GTLVL_INIT_RATIO = 0x23;
 192         DATA3_GTLVL_INIT_RATIO = 0x2D;
 193         DATA4_GTLVL_INIT_RATIO = 0x13;
 194         DATA5_GTLVL_INIT_RATIO = 0x11;
 195         DATA6_GTLVL_INIT_RATIO = 0x9;
 196         DATA7_GTLVL_INIT_RATIO = 0xC;
 197         //DATA8_GTLVL_INIT_RATIO = 0x21; //ECC byte lane. Don't care as long as you don't enable ECC by software
 198
 199         //Values with invertclkout = 0
 200         RDWR_INIT_RATIO_0 = 0x0;
 201         RDWR_INIT_RATIO_1 = 0x0;
 202         RDWR_INIT_RATIO_2 = 0x0;
 203         RDWR_INIT_RATIO_3 = 0x0;
 204         RDWR_INIT_RATIO_4 = 0x0;
 205         RDWR_INIT_RATIO_5 = 0x0;
 206         RDWR_INIT_RATIO_6 = 0x0;
 207         RDWR_INIT_RATIO_7 = 0x0;
 208         //RDWR_INIT_RATIO_8 = 0x0; //ECC byte lane. Don't care as long as you don't enable ECC by software
 209
 210
 211
 212         //GEL_TextOut("\nProgrammed initial ratios.\n");
 213
 214         DDR3_CONFIG_REG_0 = DDR3_CONFIG_REG_0 | 0xF;
 215
 216         //DDR3_CONFIG_REG_23 = RD_DQS_SLAVE_RATIO_1066 | (WR_DQS_SLAVE_RATIO_1066 << 10) | (WR_DATA_SLAVE_RATIO_1066 << 20);
 217
 218         DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS
 219         //GEL_TextOut("\nSet bit 9 = 1 for forced ratio read eye leveling.\n");
 220
 221         DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
 222         DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value                                                     //(0x34) instead
 223         //GEL_TextOut("\n Triggered full leveling.\n");
 224
 225         DDR_SDTIM1; //Read MMR to ensure full leveling is complete
 226
 227         DDR_SDRFC    = 0x00001040; //Refresh rate = Round[7.8*666.5MHz] = 0x1450
 228     }
 229     else
 230     {
 231         DDR3PLLCTL1 |= 0x00000040;    //Set ENSAT = 1
 232         DDR3PLLCTL1 |= 0x00002000;    //Set RESET bit before programming DDR3PLLCTL0
 233         DDR3PLLCTL0 = 0x02000140;
 234
 235         for(i=0;i<1000;i++); //Wait atleast 5us
 236         DDR3PLLCTL1 &= 0xFFFFDFFF;    //Clear RESET bit
 237
 238         DDR_SDRFC    = 0x800030D4;    // inhibit configuration
 239
 240         DDR_SDTIM1   = 0x0AAAE4E3;
 241         DDR_SDTIM2   = 0x20437FDA;
 242         DDR_SDTIM3   = 0x559F83FF;
 243
 244         DDR_DDRPHYC  = 0x0010010F;
 245
 246         DDR_SDRFC    = 0x000030D4;    // enable configuration
 247
 248         DDR_SDCFG    = 0x63222AB2;    // DRAM Mode Register writes occur here - 31.25us long refresh periods
 249
 250         DDR3_CONFIG_REG_0 |= 0xF;         // set dll_lock_diff to 15
 251         DDR3_CONFIG_REG_0 &= 0xFF801FFF;  // clear ctrl_slave_ratio field
 252         DDR3_CONFIG_REG_0 |= 0x00200000;  // set ctrl_slave_ratio field to 256 since INV_CLKOUT = 1
 253
 254         DDR3_CONFIG_REG_12 |= 0x08000000; // Set INV_CLKOUT = 1
 255
 256         DDR3_CONFIG_REG_23 = RD_DQS_SLAVE_RATIO | (WR_DQS_SLAVE_RATIO << 10) | (WR_DATA_SLAVE_RATIO << 20);
 257         DDR3_CONFIG_REG_24 = FIFO_WE_SLAVE_RATIO;
 258
 259
 260         DDR_SDRFC    = 0x00000C30; //Refresh rate = Round[7.8*400MHz] = 0x0C30
 261     }
 262
 263     return (0);
 264
 265 } /* hwEmif4p0Enable */
 266
 267