src/hw/ddrs/emif4/emif4.c

   1 /*************************************************************************************************
   2  * FILE PURPOSE: EMIF4 driver
   3  *************************************************************************************************
   4  * FILE NAME: emif4.c
   5  *
   6  * DESCRIPTION: The boot emif4 driver
   7  *
   8  *************************************************************************************************/
   9 #include "types.h"
  10 #include "ibl.h"
  11 #include "emif4_api.h"
  12 #include "emif4_loc.h"
  13 #include "device.h"
  14
  15 #define CHIP_LEVEL_REG  0x02620000
  16
  17 #define KICK0                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0038)
  18 #define KICK1                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x003C)
  19 #define KICK0_UNLOCK            0x83e70b13
  20 #define KICK1_UNLOCK            0x95a4f1e0
  21
  22 #define DDR3PLLCTL0             *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330)
  23 #define DDR3PLLCTL1             *(unsigned int*)(CHIP_LEVEL_REG + 0x0334)
  24
  25 // DDR3 definitions
  26 #define DDR_BASE_ADDR 0x21000000
  27
  28 #define DDR_MIDR               (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000000))
  29 #define DDR_SDCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000008))
  30 #define DDR_SDRFC              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000010))
  31 #define DDR_SDTIM1             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000018))
  32 #define DDR_SDTIM2             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000020))
  33 #define DDR_SDTIM3             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000028))
  34 #define DDR_PMCTL              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000038))
  35 #define DDR_RDWR_LVL_RMP_CTRL  (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
  36 #define DDR_RDWR_LVL_CTRL      (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
  37 #define DDR_DDRPHYC            (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000E4))
  38 #define DDR_ZQCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000C8))
  39
  40 #define DATA0_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262043C))
  41 #define DATA1_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620440))
  42 #define DATA2_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620444))
  43 #define DATA3_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620448))
  44 #define DATA4_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262044C))
  45 #define DATA5_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620450))
  46 #define DATA6_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620454))
  47 #define DATA7_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620458))
  48 #define DATA8_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262045C))
  49
  50 #define DATA0_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262040C))
  51 #define DATA1_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620410))
  52 #define DATA2_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620414))
  53 #define DATA3_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620418))
  54 #define DATA4_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262041C))
  55 #define DATA5_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620420))
  56 #define DATA6_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620424))
  57 #define DATA7_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620428))
  58 #define DATA8_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262042C))
  59
  60 #define RDWR_INIT_RATIO_0       (*(volatile unsigned int*)(0x0262040C))
  61 #define RDWR_INIT_RATIO_1       (*(volatile unsigned int*)(0x02620410))
  62 #define RDWR_INIT_RATIO_2       (*(volatile unsigned int*)(0x02620414))
  63 #define RDWR_INIT_RATIO_3       (*(volatile unsigned int*)(0x02620418))
  64 #define RDWR_INIT_RATIO_4       (*(volatile unsigned int*)(0x0262041C))
  65 #define RDWR_INIT_RATIO_5       (*(volatile unsigned int*)(0x02620420))
  66 #define RDWR_INIT_RATIO_6       (*(volatile unsigned int*)(0x02620424))
  67 #define RDWR_INIT_RATIO_7       (*(volatile unsigned int*)(0x02620428))
  68 #define RDWR_INIT_RATIO_8       (*(volatile unsigned int*)(0x0262042C))
  69
  70
  71 #define DDR3_CONFIG_REG_0   (*(volatile unsigned int*)(0x02620404))
  72 #define DDR3_CONFIG_REG_12  (*(volatile unsigned int*)(0x02620434))
  73 #define DDR3_CONFIG_REG_13  (*(volatile unsigned int*)(0x02620460))
  74 #define DDR3_CONFIG_REG_23  (*(volatile unsigned int*)(0x02620460))
  75 #define DDR3_CONFIG_REG_24  (*(volatile unsigned int*)(0x02620464))
  76
  77 #define RD_DQS_SLAVE_RATIO 0x34
  78 #define WR_DQS_SLAVE_RATIO 0xA9
  79 #define WR_DATA_SLAVE_RATIO 0xE9
  80 #define FIFO_WE_SLAVE_RATIO 0x106
  81
  82
  83 static void ddr3_wait (uint32 del)
  84 {
  85     volatile unsigned int i;
  86
  87     for (i = 0; i < del; i++);
  88
  89 }
  90
  91 /*************************************************************************************************
  92  * FUNCTION PUROPSE: Initial EMIF4 setup
  93  *************************************************************************************************
  94  * DESCRIPTION: Emif configuration
  95  *************************************************************************************************/
  96 SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
  97 {
  98     UINT32 v, i, TEMP;
  99
 100     v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
 101     v &= DEVICE_JTAG_ID_MASK;
 102
 103     if ( (v == DEVICE_C6678_JTAG_ID_VAL) ||
 104          (v == DEVICE_C6670_JTAG_ID_VAL) )
 105     {
 106
 107
 108         KICK0 = KICK0_UNLOCK;
 109         KICK1 = KICK1_UNLOCK;
 110
 111         /* 1333 MHz data rate */
 112         /***************** 2.2 DDR3 PLL Configuration ************/
 113         DDR3PLLCTL1 |= 0x00000040;      //Set ENSAT bit = 1
 114         DDR3PLLCTL0 |= 0x00800000;      // Set BYPASS = 1
 115         DDR3PLLCTL1 |= 0x00002000;      //Set RESET bit = 1
 116
 117         DDR3PLLCTL0 = 0x090804C0;       //Configure CLKR, CLKF, CLKOD, BWADJ
 118
 119         for (i = 0;i < 20;i++)
 120                 ddr3_wait(1000);                //Wait for reset to complete
 121
 122         DDR3PLLCTL1 &= ~(0x00002000);   //Clear RESET bit
 123
 124         for (i = 0;i < 500;i++)
 125                 ddr3_wait(1000);                //Wait for PLL lock
 126
 127         DDR3PLLCTL0 &= ~(0x00800000);      // Set BYPASS = 0
 128
 129
 130         /**************** 3.0 Leveling Register Configuration ********************/
 131         /* Using partial automatic leveling due to errata */
 132
 133        /**************** 3.2 Invert Clock Out ********************/
 134         DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
 135         DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
 136         DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
 137         DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15
 138         DDR3_CONFIG_REG_23 |= 0x00000200;    //Set bit 9 = 1 to use forced ratio leveling for read DQS
 139
 140        //Values with invertclkout = 1
 141       /**************** 3.3+3.4 Partial Automatic Leveling ********************/
 142       DATA0_WRLVL_INIT_RATIO = 0x5E;
 143       DATA1_WRLVL_INIT_RATIO = 0x5E;
 144       DATA2_WRLVL_INIT_RATIO = 0x5E;
 145       DATA3_WRLVL_INIT_RATIO = 0x51;
 146       DATA4_WRLVL_INIT_RATIO = 0x38;
 147       DATA5_WRLVL_INIT_RATIO = 0x3A;
 148       DATA6_WRLVL_INIT_RATIO = 0x24;
 149       DATA7_WRLVL_INIT_RATIO = 0x20;
 150       DATA8_WRLVL_INIT_RATIO = 0x44;
 151
 152       DATA0_GTLVL_INIT_RATIO = 0xDD;
 153       DATA1_GTLVL_INIT_RATIO = 0xDD;
 154       DATA2_GTLVL_INIT_RATIO = 0xBE;
 155       DATA3_GTLVL_INIT_RATIO = 0xCA;
 156       DATA4_GTLVL_INIT_RATIO = 0xA9;
 157       DATA5_GTLVL_INIT_RATIO = 0xA7;
 158       DATA6_GTLVL_INIT_RATIO = 0x9E;
 159       DATA7_GTLVL_INIT_RATIO = 0xA1;
 160       DATA8_GTLVL_INIT_RATIO = 0xBA;
 161
 162       //Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0
 163       DDR_DDRPHYC &= ~(0x00008000);
 164       DDR_DDRPHYC |= (0x00008000);
 165       DDR_DDRPHYC &= ~(0x00008000);
 166
 167       /***************** 2.3 Basic Controller and DRAM configuration ************/
 168       DDR_SDRFC    = 0x00005162;    // enable configuration
 169
 170       /* DDR_SDTIM1   = 0x1113783C; */
 171        TEMP = 0;
 172        TEMP |= 0x8 << 25; // T_RP bit field 28:25
 173        TEMP |= 0x8 << 21; // T_RCD bit field 24:21
 174        TEMP |= 0x9 << 17; // T_WR bit field 20:17
 175        TEMP |= 0x17 << 12; // T_RAS bit field 16:12
 176        TEMP |= 0x20 << 6; // T_RC bit field 11:6
 177        TEMP |= 0x7 << 3; // T_RRD bit field 5:3
 178        TEMP |= 0x4; // T_WTR bit field 2:0
 179        DDR_SDTIM1 = TEMP;
 180
 181       /* DDR_SDTIM2   = 0x304F7FE3; */
 182        TEMP = 0;
 183        TEMP |= 0x3 << 28; // T_XP bit field 30:28
 184        TEMP |= 0x4f << 16; // T_XSNR bit field 24:16
 185        TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6
 186        TEMP |= 0x4 << 3; // T_RTP bit field 5:3
 187        TEMP |= 0x3; // T_CKE bit field 2:0
 188        DDR_SDTIM2 = TEMP;
 189
 190       /*  DDR_SDTIM3   = 0x559F849F; */
 191        TEMP = 0;
 192        TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)
 193        TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)
 194        TEMP |= 0x4 << 21; // T_CKESR bit field 23:21
 195        TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15
 196        TEMP |= 0x49 << 4; // T_RFC bit field 12:4
 197        TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value)
 198        DDR_SDTIM3 = TEMP;
 199
 200         DDR_DDRPHYC  = 0x0010010F;
 201
 202         DDR_ZQCFG    = 0x70073214;
 203
 204         DDR_PMCTL    = 0x0;
 205
 206         DDR_SDRFC = 0x00005162; // enable configuration
 207
 208         /* DDR_SDCFG    = 0x63062A32; */
 209         /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32;    // last config write DRAM init occurs */
 210          TEMP = 0;
 211          TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)
 212          TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27
 213          TEMP |= 0x3 << 24; // DDR_TERM bit field 26:24
 214          TEMP |= 0x0 << 21; // DYN_ODT bit field 22:21
 215          TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18
 216          TEMP |= 0x2 << 16; // CWL bit field 17:16
 217          TEMP |= 0x0 << 14; // NM bit field 15:14
 218          TEMP |= 0xA << 10; // CL bit field 13:10
 219          TEMP |= 0x4 << 7; // ROWSIZE bit field 9:7
 220          TEMP |= 0x3 << 4; // IBANK bit field 6:4
 221          TEMP |= 0x0 << 3; // EBANK bit field 3:3
 222          TEMP |= 0x2; // PAGESIZE bit field 2:0
 223          DDR_SDCFG = TEMP;
 224
 225         for (i = 0; i < 12000; i++) {
 226                 ddr3_wait(1000);             //Wait 600us for HW init to complete
 227         }
 228
 229         DDR_SDRFC = 0x00001450;       //Refresh rate = (7.8*666MHz]
 230
 231         DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
 232
 233         /*Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value
 234           Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.
 235           Actual time = ~10-15 ms */
 236         DDR_RDWR_LVL_CTRL = 0x80000000;
 237
 238         for (i = 0; i < 30000; i++) {
 239                 ddr3_wait(1000); //Wait 3ms for leveling to complete
 240         }
 241     }
 242     else
 243     {
 244         /* C64x configuration */
 245         /* If the config registers or refresh control registers are being written
 246          * disable the initialization sequence until they are all setup */
 247         if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0)  {
 248
 249             v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
 250             EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
 251             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
 252         }
 253
 254         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
 255             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
 256
 257         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
 258             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
 259
 260         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
 261             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
 262
 263         if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
 264             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
 265
 266         if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
 267             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
 268
 269         if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
 270             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
 271
 272         if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
 273             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
 274
 275         if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
 276             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
 277
 278         if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
 279             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
 280
 281         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
 282             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
 283
 284         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
 285             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
 286
 287         if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
 288             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
 289
 290         if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
 291             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
 292
 293         if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
 294             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
 295
 296         if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
 297             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
 298
 299         if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
 300             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
 301
 302         if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
 303             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
 304
 305         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
 306             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
 307
 308         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
 309             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
 310
 311         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
 312             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
 313
 314         if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
 315             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
 316
 317         /* Allow the configuration to occur */
 318         v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
 319         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
 320         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
 321
 322         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
 323             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
 324
 325         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
 326             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
 327
 328         v = cfg->sdRamRefreshCtl;
 329         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
 330         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
 331     }
 332
 333     return (0);
 334
 335 } /* hwEmif4p0Enable */
 336
 337