7b82f8c9709771c1131ad472909fd9ce532566ff
[keystone-rtos/ibl.git] / src / hw / ddrs / emif4 / emif4.c
1 /*************************************************************************************************
2  * FILE PURPOSE: EMIF4 driver
3  *************************************************************************************************
4  * FILE NAME: emif4.c
5  *
6  * DESCRIPTION: The boot emif4 driver
7  *
8  *************************************************************************************************/
9 #include "types.h"
10 #include "ibl.h"
11 #include "emif4_api.h"
12 #include "emif4_loc.h"
13 #include "device.h"
15 #define CHIP_LEVEL_REG  0x02620000
17 #define KICK0                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0038)
18 #define KICK1                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x003C)
19 #define KICK0_UNLOCK            0x83e70b13
20 #define KICK1_UNLOCK            0x95a4f1e0
22 #define DDR3PLLCTL0             *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330)
23 #define DDR3PLLCTL1             *(unsigned int*)(CHIP_LEVEL_REG + 0x0334)
25 // DDR3 definitions
26 #define DDR_BASE_ADDR 0x21000000
28 #define DDR_MIDR               (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000000))
29 #define DDR_SDCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000008))
30 #define DDR_SDRFC              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000010))
31 #define DDR_SDTIM1             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000018))
32 #define DDR_SDTIM2             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000020))
33 #define DDR_SDTIM3             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000028))
34 #define DDR_PMCTL              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000038))
35 #define DDR_RDWR_LVL_RMP_CTRL  (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
36 #define DDR_RDWR_LVL_CTRL      (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
37 #define DDR_DDRPHYC            (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000E4))
38 #define DDR_ZQCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000C8))
40 #define DATA0_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262043C))
41 #define DATA1_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620440))
42 #define DATA2_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620444))
43 #define DATA3_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620448))
44 #define DATA4_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262044C))
45 #define DATA5_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620450))
46 #define DATA6_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620454))
47 #define DATA7_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620458))
48 #define DATA8_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262045C))
50 #define DATA0_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262040C))
51 #define DATA1_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620410))
52 #define DATA2_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620414))
53 #define DATA3_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620418))
54 #define DATA4_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262041C))
55 #define DATA5_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620420))
56 #define DATA6_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620424))
57 #define DATA7_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620428))
58 #define DATA8_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262042C))
60 #define RDWR_INIT_RATIO_0       (*(volatile unsigned int*)(0x0262040C))
61 #define RDWR_INIT_RATIO_1       (*(volatile unsigned int*)(0x02620410))
62 #define RDWR_INIT_RATIO_2       (*(volatile unsigned int*)(0x02620414))
63 #define RDWR_INIT_RATIO_3       (*(volatile unsigned int*)(0x02620418))
64 #define RDWR_INIT_RATIO_4       (*(volatile unsigned int*)(0x0262041C))
65 #define RDWR_INIT_RATIO_5       (*(volatile unsigned int*)(0x02620420))
66 #define RDWR_INIT_RATIO_6       (*(volatile unsigned int*)(0x02620424))
67 #define RDWR_INIT_RATIO_7       (*(volatile unsigned int*)(0x02620428))
68 #define RDWR_INIT_RATIO_8       (*(volatile unsigned int*)(0x0262042C))
71 #define DDR3_CONFIG_REG_0   (*(volatile unsigned int*)(0x02620404))
72 #define DDR3_CONFIG_REG_12  (*(volatile unsigned int*)(0x02620434))
73 #define DDR3_CONFIG_REG_23  (*(volatile unsigned int*)(0x02620460))
74 #define DDR3_CONFIG_REG_24  (*(volatile unsigned int*)(0x02620464))
76 #define RD_DQS_SLAVE_RATIO 0x34
77 #define WR_DQS_SLAVE_RATIO 0xA9
78 #define WR_DATA_SLAVE_RATIO 0xE9
79 #define FIFO_WE_SLAVE_RATIO 0x106
82 static void ddr3_wait (uint32 del)
83 {
84     volatile unsigned int i;
86     for (i = 0; i < del; i++) asm (" nop ");
88 }
90 /*************************************************************************************************
91  * FUNCTION PUROPSE: Initial EMIF4 setup
92  *************************************************************************************************
93  * DESCRIPTION: Emif configuration
94  *************************************************************************************************/
95 SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
96 {
97     UINT32 v, i, TEMP;
98     
99     v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
100     v &= DEVICE_JTAG_ID_MASK;
101     
102     if ( (v == DEVICE_C6678_JTAG_ID_VAL) ||
103          (v == DEVICE_C6670_JTAG_ID_VAL) )
104     {
107         KICK0 = KICK0_UNLOCK;
108         KICK1 = KICK1_UNLOCK;
109         
110        /**************** 3.3 Leveling register configuration ********************/
111         DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
112         DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
113         DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
114         DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15
115         DDR3_CONFIG_REG_23 |= 0x00000200;    // See section 4.2.1, set for partial automatic levelling
116             
117       /**************** 3.3 Partial Automatic Leveling ********************/
118       DATA0_WRLVL_INIT_RATIO = 0x5E;
119       DATA1_WRLVL_INIT_RATIO = 0x5E;
120       DATA2_WRLVL_INIT_RATIO = 0x5E;
121       DATA3_WRLVL_INIT_RATIO = 0x51;
122       DATA4_WRLVL_INIT_RATIO = 0x38;
123       DATA5_WRLVL_INIT_RATIO = 0x3A;
124       DATA6_WRLVL_INIT_RATIO = 0x24;
125       DATA7_WRLVL_INIT_RATIO = 0x20;
126       DATA8_WRLVL_INIT_RATIO = 0x44;
128       DATA0_GTLVL_INIT_RATIO = 0xDD;
129       DATA1_GTLVL_INIT_RATIO = 0xDD;
130       DATA2_GTLVL_INIT_RATIO = 0xBE;
131       DATA3_GTLVL_INIT_RATIO = 0xCA;
132       DATA4_GTLVL_INIT_RATIO = 0xA9;
133       DATA5_GTLVL_INIT_RATIO = 0xA7;
134       DATA6_GTLVL_INIT_RATIO = 0x9E;
135       DATA7_GTLVL_INIT_RATIO = 0xA1;
136       DATA8_GTLVL_INIT_RATIO = 0xBA;
137   
138       //Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0
139       DDR_DDRPHYC &= ~(0x00008000);
140       DDR_DDRPHYC |= (0x00008000);
141       DDR_DDRPHYC &= ~(0x00008000);
143       /***************** 3.4 Basic Controller and DRAM configuration ************/
144       DDR_SDRFC    = 0x00005162;    // enable configuration 
146       /* DDR_SDTIM1   = 0x1113783C; */
147        TEMP = 0;
148        TEMP |= 0x8 << 25; // T_RP bit field 28:25
149        TEMP |= 0x8 << 21; // T_RCD bit field 24:21
150        TEMP |= 0x9 << 17; // T_WR bit field 20:17
151        TEMP |= 0x17 << 12; // T_RAS bit field 16:12
152        TEMP |= 0x20 << 6; // T_RC bit field 11:6
153        TEMP |= 0x7 << 3; // T_RRD bit field 5:3
154        TEMP |= 0x4; // T_WTR bit field 2:0
155        DDR_SDTIM1 = TEMP;
157       /* DDR_SDTIM2   = 0x304F7FE3; */
158        TEMP = 0;
159        TEMP |= 0x3 << 28; // T_XP bit field 30:28
160        TEMP |= 0x4f << 16; // T_XSNR bit field 24:16
161        TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6
162        TEMP |= 0x4 << 3; // T_RTP bit field 5:3
163        TEMP |= 0x3; // T_CKE bit field 2:0
164        DDR_SDTIM2 = TEMP;
166       /*  DDR_SDTIM3   = 0x559F849F; */
167        TEMP = 0;
168        TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)
169        TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)
170        TEMP |= 0x4 << 21; // T_CKESR bit field 23:21
171        TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15
172        TEMP |= 0x49 << 4; // T_RFC bit field 12:4
173        TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value)
174        DDR_SDTIM3 = TEMP; 
176         DDR_DDRPHYC  = 0x0010010F;
177      
178         DDR_ZQCFG    = 0x70073214; 
180         DDR_PMCTL    = 0x0;
181      
182         DDR_SDRFC = 0x00005162; // enable configuration
184         /* DDR_SDCFG    = 0x63062A32; */
185         /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32;    // last config write DRAM init occurs */
186          TEMP = 0;
187          TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)
188          TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27
189          TEMP |= 0x3 << 24; // DDR_TERM bit field 26:24
190          TEMP |= 0x0 << 21; // DYN_ODT bit field 22:21
191          TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18
192          TEMP |= 0x2 << 16; // CWL bit field 17:16
193          TEMP |= 0x0 << 14; // NM bit field 15:14
194          TEMP |= 0xA << 10; // CL bit field 13:10
195          TEMP |= 0x4 << 7; // ROWSIZE bit field 9:7
196          TEMP |= 0x3 << 4; // IBANK bit field 6:4
197          TEMP |= 0x0 << 3; // EBANK bit field 3:3
198          TEMP |= 0x2; // PAGESIZE bit field 2:0
199          DDR_SDCFG = TEMP;
201         /* assuming max device speed, 1.4GHz, 1 cycle = 0.714 ns *
202         * so, 100 us = 100000 ns = 140056 cycles
203           thereby, 600us=840336 */
204          ddr3_wait(840336);             //Wait 600us for HW init to complete
206         DDR_SDRFC = 0x00001450;       //Refresh rate = (7.8*666MHz]
208       /***************** 4.2.1 Partial automatic leveling ************/
209         DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable automatic leveling
210    
211         /*Trigger automatic leveling - This ignores read DQS leveling result and uses ratio forced value
212           Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.
213           Actual time = ~10-15 ms */
214         DDR_RDWR_LVL_CTRL = 0x80000000; 
216         /* assuming max device speed, 1.4GHz, 1 cycle = 0.714 ns *
217         * so, 100 us = 100000 ns = 140056 cycles
218           thereby, 3ms=3000us=4201680 */
219         ddr3_wait(4201680); //Wait 3ms for leveling to complete
220     }
221     else
222     {
223         /* C64x configuration */
224         /* If the config registers or refresh control registers are being written
225          * disable the initialization sequence until they are all setup */
226         if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0)  {
227             
228             v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
229             EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
230             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
231         }
232         
233         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
234             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
235         
236         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
237             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
238         
239         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
240             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
241         
242         if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
243             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
244         
245         if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
246             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
247         
248         if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
249             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
250         
251         if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
252             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
253         
254         if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
255             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
256         
257         if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
258             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
259         
260         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
261             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
262         
263         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
264             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
265         
266         if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
267             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
268         
269         if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
270             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
271         
272         if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
273             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
274         
275         if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
276             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
277         
278         if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
279             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
280         
281         if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
282             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
283         
284         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
285             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
286         
287         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
288             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
289         
290         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
291             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
292         
293         if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
294             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
295         
296         /* Allow the configuration to occur */
297         v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
298         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
299         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
300         
301         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
302             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
303         
304         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
305             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
306         
307         v = cfg->sdRamRefreshCtl;
308         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
309         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
310     }
311     
312     return (0);
314 } /* hwEmif4p0Enable */