8043e19f9b5d53153dcd7ffb858da1b2f6a91dec
1 /*************************************************************************************************
2 * FILE PURPOSE: EMIF4 driver
3 *************************************************************************************************
4 * FILE NAME: emif4.c
5 *
6 * DESCRIPTION: The boot emif4 driver
7 *
8 *************************************************************************************************/
9 #include "types.h"
10 #include "ibl.h"
11 #include "emif4_api.h"
12 #include "emif4_loc.h"
13 #include "device.h"
15 #define CHIP_LEVEL_REG 0x02620000
17 #define KICK0 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0038)
18 #define KICK1 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x003C)
20 #define DDR3PLLCTL0 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330)
21 #define DDR3PLLCTL1 *(unsigned int*)(CHIP_LEVEL_REG + 0x0334)
23 // DDR3 definitions
24 #define DDR_BASE_ADDR 0x21000000
26 #define DDR_MIDR (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000000))
27 #define DDR_SDCFG (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000008))
28 #define DDR_SDRFC (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000010))
29 #define DDR_SDTIM1 (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000018))
30 #define DDR_SDTIM2 (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000020))
31 #define DDR_SDTIM3 (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000028))
32 #define DDR_PMCTL (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000038))
33 #define DDR_RDWR_LVL_RMP_CTRL (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
34 #define DDR_RDWR_LVL_CTRL (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
35 #define DDR_DDRPHYC (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000E4))
36 #define DDR_ZQCFG (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000C8))
38 #define DATA0_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x0262043C))
39 #define DATA1_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620440))
40 #define DATA2_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620444))
41 #define DATA3_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620448))
42 #define DATA4_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x0262044C))
43 #define DATA5_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620450))
44 #define DATA6_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620454))
45 #define DATA7_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620458))
46 #define DATA8_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x0262045C))
48 #define DATA0_WRLVL_INIT_RATIO (*(unsigned int*)(0x0262040C))
49 #define DATA1_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620410))
50 #define DATA2_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620414))
51 #define DATA3_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620418))
52 #define DATA4_WRLVL_INIT_RATIO (*(unsigned int*)(0x0262041C))
53 #define DATA5_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620420))
54 #define DATA6_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620424))
55 #define DATA7_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620428))
56 #define DATA8_WRLVL_INIT_RATIO (*(unsigned int*)(0x0262042C))
58 #define RDWR_INIT_RATIO_0 (*(volatile unsigned int*)(0x0262040C))
59 #define RDWR_INIT_RATIO_1 (*(volatile unsigned int*)(0x02620410))
60 #define RDWR_INIT_RATIO_2 (*(volatile unsigned int*)(0x02620414))
61 #define RDWR_INIT_RATIO_3 (*(volatile unsigned int*)(0x02620418))
62 #define RDWR_INIT_RATIO_4 (*(volatile unsigned int*)(0x0262041C))
63 #define RDWR_INIT_RATIO_5 (*(volatile unsigned int*)(0x02620420))
64 #define RDWR_INIT_RATIO_6 (*(volatile unsigned int*)(0x02620424))
65 #define RDWR_INIT_RATIO_7 (*(volatile unsigned int*)(0x02620428))
66 #define RDWR_INIT_RATIO_8 (*(volatile unsigned int*)(0x0262042C))
69 #define DDR3_CONFIG_REG_0 (*(volatile unsigned int*)(0x02620404))
70 #define DDR3_CONFIG_REG_12 (*(volatile unsigned int*)(0x02620434))
71 #define DDR3_CONFIG_REG_13 (*(volatile unsigned int*)(0x02620460))
72 #define DDR3_CONFIG_REG_23 (*(volatile unsigned int*)(0x02620460))
73 #define DDR3_CONFIG_REG_24 (*(volatile unsigned int*)(0x02620464))
75 #define RD_DQS_SLAVE_RATIO 0x34
76 #define WR_DQS_SLAVE_RATIO 0xA9
77 #define WR_DATA_SLAVE_RATIO 0xE9
78 #define FIFO_WE_SLAVE_RATIO 0x106
81 static void ddr3_wait (uint32 del)
82 {
83 volatile unsigned int i;
85 for (i = 0; i < del; i++);
87 }
89 /*************************************************************************************************
90 * FUNCTION PUROPSE: Initial EMIF4 setup
91 *************************************************************************************************
92 * DESCRIPTION: Emif configuration
93 *************************************************************************************************/
94 SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
95 {
96 UINT32 v, i;
98 v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
99 v &= DEVICE_JTAG_ID_MASK;
101 if (v == DEVICE_C6678_JTAG_ID_VAL)
102 {
103 #if 0
104 /* C6678 Old 1066 configuration */
105 DDR3PLLCTL0 = 0x100807C1;
107 DDR_SDTIM1 = 0x0CCF369B;
108 DDR_SDTIM2 = 0x3A3F7FDA;
109 DDR_SDTIM3 = 0x057F83A8;
110 DDR_PMCTL |= (0x9 << 4); // Set up SR_TIM to Enter self-refresh after 4096 clocks
112 DDR_DDRPHYC = 0x0010010B;
114 DDR_SDRFC = 0x00004111; //500us
117 DDR_SDCFG = 0x63C51A32; //0x63C51A32; //row-col = 13-10
120 //Values with invertclkout = 0
121 DATA0_GTLVL_INIT_RATIO = 0x3C;
122 DATA1_GTLVL_INIT_RATIO = 0x3C;
123 DATA2_GTLVL_INIT_RATIO = 0x23;
124 DATA3_GTLVL_INIT_RATIO = 0x2D;
125 DATA4_GTLVL_INIT_RATIO = 0x13;
126 DATA5_GTLVL_INIT_RATIO = 0x11;
127 DATA6_GTLVL_INIT_RATIO = 0x9;
128 DATA7_GTLVL_INIT_RATIO = 0xC;
129 //DATA8_GTLVL_INIT_RATIO = 0x21; //ECC byte lane. Don't care as long as you don't enable ECC by software
131 //Values with invertclkout = 0
132 RDWR_INIT_RATIO_0 = 0x0;
133 RDWR_INIT_RATIO_1 = 0x0;
134 RDWR_INIT_RATIO_2 = 0x0;
135 RDWR_INIT_RATIO_3 = 0x0;
136 RDWR_INIT_RATIO_4 = 0x0;
137 RDWR_INIT_RATIO_5 = 0x0;
138 RDWR_INIT_RATIO_6 = 0x0;
139 RDWR_INIT_RATIO_7 = 0x0;
140 //RDWR_INIT_RATIO_8 = 0x0; //ECC byte lane. Don't care as long as you don't enable ECC by software
144 //GEL_TextOut("\nProgrammed initial ratios.\n");
146 DDR3_CONFIG_REG_0 = DDR3_CONFIG_REG_0 | 0xF;
148 //DDR3_CONFIG_REG_23 = RD_DQS_SLAVE_RATIO_1066 | (WR_DQS_SLAVE_RATIO_1066 << 10) | (WR_DATA_SLAVE_RATIO_1066 << 20);
150 DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS
151 //GEL_TextOut("\nSet bit 9 = 1 for forced ratio read eye leveling.\n");
153 DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
154 DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value //(0x34) instead
155 //GEL_TextOut("\n Triggered full leveling.\n");
157 DDR_SDTIM1; //Read MMR to ensure full leveling is complete
159 DDR_SDRFC = 0x00001040; //Refresh rate = Round[7.8*666.5MHz] = 0x1450
160 #endif
161 #if 1
162 /* C6678 1333 MHz data rate */
163 /***************** 2.2 DDR3 PLL Configuration ************/
164 DDR3PLLCTL1 |= 0x00000040; //Set ENSAT bit = 1
165 DDR3PLLCTL1 |= 0x00002000; //Set RESET bit = 1
166 DDR3PLLCTL0 = 0x090804C0; //Configure CLKR, CLKF, CLKOD, BWADJ
167 ddr3_wait(1000); //Wait for reset to complete
168 DDR3PLLCTL1 &= ~(0x00002000); //Clear RESET bit
169 ddr3_wait(1000); //Wait for PLL lock
171 /***************** 2.3 Basic Controller and DRAM configuration ************/
172 DDR_SDRFC = 0x80005162; // inhibit configuration
174 DDR_SDTIM1 = 0x1113783C;
175 DDR_SDTIM2 = 0x304F7FE3;
176 DDR_SDTIM3 = 0x559F849F;
178 DDR_DDRPHYC = 0x0010010F;
180 DDR_ZQCFG = 0x70073214;
182 DDR_PMCTL = 0x0;
184 DDR_SDRFC = 0x00005162; // enable configuration
185 DDR_SDCFG = 0x63222A32; // last config write \96 DRAM init occurs
187 ddr3_wait(1000); //Wait for HW init to complete
188 DDR_SDRFC = 0x00001450; //Refresh rate = (7.8*666MHz]
190 /**************** 3.0 Leveling Register Configuration ********************/
191 /* Using partial automatic leveling due to errata */
193 /**************** 3.2 Invert Clock Out ********************/
194 DDR3_CONFIG_REG_0 &= ~(0x007FE000); // clear ctrl_slave_ratio field
195 DDR3_CONFIG_REG_0 |= 0x00200000; // set ctrl_slave_ratio to 0x100
196 DDR3_CONFIG_REG_12 |= 0x08000000; // Set invert_clkout = 1
197 DDR3_CONFIG_REG_0 |= 0xF; // set dll_lock_diff to 15
200 /**************** 3.3+3.4 Partial Automatic Leveling ********************/
201 DATA0_WRLVL_INIT_RATIO = 0x20;
202 DATA1_WRLVL_INIT_RATIO = 0x24;
203 DATA2_WRLVL_INIT_RATIO = 0x3A;
204 DATA3_WRLVL_INIT_RATIO = 0x38;
205 DATA4_WRLVL_INIT_RATIO = 0x51;
206 DATA5_WRLVL_INIT_RATIO = 0x5E;
207 DATA6_WRLVL_INIT_RATIO = 0x5E;
208 DATA7_WRLVL_INIT_RATIO = 0x5E;
209 DATA8_WRLVL_INIT_RATIO = 0x44;
211 DATA0_GTLVL_INIT_RATIO = 0xA1;
212 DATA1_GTLVL_INIT_RATIO = 0x9E;
213 DATA2_GTLVL_INIT_RATIO = 0xA7;
214 DATA3_GTLVL_INIT_RATIO = 0xA9;
215 DATA4_GTLVL_INIT_RATIO = 0xCA;
216 DATA5_GTLVL_INIT_RATIO = 0xBE;
217 DATA6_GTLVL_INIT_RATIO = 0xDD;
218 DATA7_GTLVL_INIT_RATIO = 0xDD;
219 DATA8_GTLVL_INIT_RATIO = 0xBA;
221 DDR3_CONFIG_REG_23 |= 0x00000200;
222 DDR_RDWR_LVL_RMP_CTRL = 0x80000000;
223 DDR_RDWR_LVL_CTRL = 0x80000000;
224 #endif
226 #if 0
227 /* C6678 New 1066 rate */
228 /***************** 2.2 DDR3 PLL Configuration ************/
229 DDR3PLLCTL1 |= 0x00000040; //Set ENSAT bit = 1
230 DDR3PLLCTL1 |= 0x00002000; //Set RESET bit = 1
231 DDR3PLLCTL0 = 0x0F0807C1; //Configure CLKR, CLKF, CLKOD, BWADJ
232 ddr3_wait(1000); //Wait for reset to complete
233 DDR3PLLCTL1 &= ~(0x00002000); //Clear RESET bit
234 ddr3_wait(1000);
236 /***************** 2.3 Basic Controller and DRAM configuration ************/
237 DDR_SDRFC = 0x8000411B; // inhibit configuration
238 DDR_SDTIM1 = 0x0CCF36B3;
239 DDR_SDTIM2 = 0x303F7FDA;
240 DDR_SDTIM3 = 0x559F83AF;
242 DDR_DDRPHYC = 0x0010010A;
243 DDR_ZQCFG = 0x70073214;
245 //DDR_PMCTL = 0x0;
246 DDR_SDRFC = 0x0000411B; // enable configuration
247 DDR_SDCFG = 0x63211A32; // last config write \96 DRAM init occurs
249 ddr3_wait(1000); //Wait for HW init to complete
251 DDR_SDRFC = 0x00001040; //Refresh rate = (7.8*666MHz]
253 /**************** 3.0 Leveling Register Configuration ********************/
254 /* Using partial automatic leveling due to errata */
256 /**************** 3.2 Invert Clock Out ********************/
257 DDR3_CONFIG_REG_0 &= ~(0x007FE000); // clear ctrl_slave_ratio field
258 DDR3_CONFIG_REG_0 |= 0x00200000; // set ctrl_slave_ratio to 0x100
259 DDR3_CONFIG_REG_12 |= 0x08000000; // Set invert_clkout = 1
260 DDR3_CONFIG_REG_0 |= 0xF; // set dll_lock_diff to 15
262 /**************** 3.3+3.4 Partial Automatic Leveling ********************/
263 DATA0_WRLVL_INIT_RATIO = 0x19;//0x4C;
264 DATA1_WRLVL_INIT_RATIO = 0x1C;//0x4C;
265 DATA2_WRLVL_INIT_RATIO = 0x2F;//0x4C;
266 DATA3_WRLVL_INIT_RATIO = 0x2D;//0x42;
267 DATA4_WRLVL_INIT_RATIO = 0x42;//0x2D;
268 DATA5_WRLVL_INIT_RATIO = 0x4C;//0x2F;
269 DATA6_WRLVL_INIT_RATIO = 0x4C;//0x1C;
270 DATA7_WRLVL_INIT_RATIO = 0x4C;//0x19;
271 DATA8_WRLVL_INIT_RATIO = 0x37;
273 DATA0_GTLVL_INIT_RATIO = 0x8D;//0xBC;
274 DATA1_GTLVL_INIT_RATIO = 0x8A;//0xBC;
275 DATA2_GTLVL_INIT_RATIO = 0x91;//0xA4;
276 DATA3_GTLVL_INIT_RATIO = 0x93;//0xAE;
277 DATA4_GTLVL_INIT_RATIO = 0xAE;//0x93;
278 DATA5_GTLVL_INIT_RATIO = 0xA4;//0x91;
279 DATA6_GTLVL_INIT_RATIO = 0xBC;//0x8A;
280 DATA7_GTLVL_INIT_RATIO = 0xBC;//0x8D;
281 DATA8_GTLVL_INIT_RATIO = 0xA1;
283 DDR3_CONFIG_REG_23 |= 0x00000200;
284 DDR_RDWR_LVL_RMP_CTRL = 0x80000000;
285 DDR_RDWR_LVL_CTRL = 0x80000000;
286 #endif
287 }
288 else if (v == DEVICE_C6670_JTAG_ID_VAL)
289 {
290 /* C6670 800 M rate */
291 DDR3PLLCTL1 |= 0x00000040; //Set ENSAT = 1
292 DDR3PLLCTL1 |= 0x00002000; //Set RESET bit before programming DDR3PLLCTL0
293 DDR3PLLCTL0 = 0x02000140;
295 for(i=0;i<1000;i++); //Wait atleast 5us
296 DDR3PLLCTL1 &= 0xFFFFDFFF; //Clear RESET bit
298 DDR_SDRFC = 0x800030D4; // inhibit configuration
300 DDR_SDTIM1 = 0x0AAAE4E3;
301 DDR_SDTIM2 = 0x20437FDA;
302 DDR_SDTIM3 = 0x559F83FF;
304 DDR_DDRPHYC = 0x0010010F;
306 DDR_SDRFC = 0x000030D4; // enable configuration
308 DDR_SDCFG = 0x63222AB2; // DRAM Mode Register writes occur here - 31.25us long refresh periods
310 DDR3_CONFIG_REG_0 |= 0xF; // set dll_lock_diff to 15
311 DDR3_CONFIG_REG_0 &= 0xFF801FFF; // clear ctrl_slave_ratio field
312 DDR3_CONFIG_REG_0 |= 0x00200000; // set ctrl_slave_ratio field to 256 since INV_CLKOUT = 1
314 DDR3_CONFIG_REG_12 |= 0x08000000; // Set INV_CLKOUT = 1
316 DDR3_CONFIG_REG_23 = RD_DQS_SLAVE_RATIO | (WR_DQS_SLAVE_RATIO << 10) | (WR_DATA_SLAVE_RATIO << 20);
317 DDR3_CONFIG_REG_24 = FIFO_WE_SLAVE_RATIO;
320 DDR_SDRFC = 0x00000C30; //Refresh rate = Round[7.8*400MHz] = 0x0C30
321 }
322 else
323 {
324 /* C64x configuration */
325 /* If the config registers or refresh control registers are being written
326 * disable the initialization sequence until they are all setup */
327 if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0) {
329 v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
330 EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
331 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
332 }
334 if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
335 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
337 if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
338 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
340 if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
341 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
343 if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
344 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
346 if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
347 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
349 if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
350 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
352 if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
353 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
355 if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
356 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
358 if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
359 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
361 if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
362 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
364 if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
365 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
367 if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
368 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
370 if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
371 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
373 if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
374 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
376 if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
377 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
379 if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
380 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
382 if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
383 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
385 if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
386 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
388 if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
389 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
391 if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
392 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
394 if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
395 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
397 /* Allow the configuration to occur */
398 v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
399 EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
400 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
402 if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
403 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
405 if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
406 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
408 v = cfg->sdRamRefreshCtl;
409 EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
410 DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
411 }
413 return (0);
415 } /* hwEmif4p0Enable */