a170814e53e0cb1436160a19d618b3e8a1572fba
[keystone-rtos/ibl.git] / src / hw / ddrs / emif4 / emif4.c
1 /*************************************************************************************************
2  * FILE PURPOSE: EMIF4 driver
3  *************************************************************************************************
4  * FILE NAME: emif4.c
5  *
6  * DESCRIPTION: The boot emif4 driver
7  *
8  *************************************************************************************************/
9 #include "types.h"
10 #include "ibl.h"
11 #include "emif4_api.h"
12 #include "emif4_loc.h"
13 #include "device.h"
15 #define CHIP_LEVEL_REG  0x02620000
17 #define KICK0                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0038)
18 #define KICK1                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x003C)
20 #define DDR3PLLCTL0             *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330)
22 // DDR3 definitions
23 #define DDR_BASE_ADDR 0x21000000
25 #define DDR_MIDR               (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000000))
26 #define DDR_SDCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000008))
27 #define DDR_SDRFC              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000010))
28 #define DDR_SDTIM1             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000018))
29 #define DDR_SDTIM2             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000020))
30 #define DDR_SDTIM3             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000028))
31 #define DDR_PMCTL              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000038))
32 #define DDR_RDWR_LVL_RMP_CTRL  (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
33 #define DDR_RDWR_LVL_CTRL      (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
34 #define DDR_DDRPHYC            (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000E4))
36 #define DATA0_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262043C))
37 #define DATA1_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620440))
38 #define DATA2_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620444))
39 #define DATA3_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620448))
40 #define DATA4_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262044C))
41 #define DATA5_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620450))
42 #define DATA6_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620454))
43 #define DATA7_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620458))
44 #define DATA8_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262045C))
46 #define RDWR_INIT_RATIO_0       (*(volatile unsigned int*)(0x0262040C))
47 #define RDWR_INIT_RATIO_1       (*(volatile unsigned int*)(0x02620410))
48 #define RDWR_INIT_RATIO_2       (*(volatile unsigned int*)(0x02620414))
49 #define RDWR_INIT_RATIO_3       (*(volatile unsigned int*)(0x02620418))
50 #define RDWR_INIT_RATIO_4       (*(volatile unsigned int*)(0x0262041C))
51 #define RDWR_INIT_RATIO_5       (*(volatile unsigned int*)(0x02620420))
52 #define RDWR_INIT_RATIO_6       (*(volatile unsigned int*)(0x02620424))
53 #define RDWR_INIT_RATIO_7       (*(volatile unsigned int*)(0x02620428))
54 #define RDWR_INIT_RATIO_8       (*(volatile unsigned int*)(0x0262042C))
56 #define DDR3_CONFIG_REG_0   (*(volatile unsigned int*)(0x02620404))
57 #define DDR3_CONFIG_REG_12  (*(volatile unsigned int*)(0x02620434))
58 #define DDR3_CONFIG_REG_13  (*(volatile unsigned int*)(0x02620460))
59 #define DDR3_CONFIG_REG_23  (*(volatile unsigned int*)(0x02620460))
60 #define DDR3_CONFIG_REG_24  (*(volatile unsigned int*)(0x02620464))
62 /*************************************************************************************************
63  * FUNCTION PUROPSE: Initial EMIF4 setup
64  *************************************************************************************************
65  * DESCRIPTION: Emif configuration
66  *************************************************************************************************/
67 SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
68 {
69     UINT32 v;
71 #if 0
72     /* If the config registers or refresh control registers are being written
73      * disable the initialization sequence until they are all setup */
74     if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0)  {
76         v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
77         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
78         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
79     }
81     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
82         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
84     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
85         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
87     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
88         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
90     if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
91         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
93     if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
94         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
96     if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
97         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
99     if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
100         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
102     if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
103         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
105     if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
106         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
108     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
109         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
111     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
112         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
114     if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
115         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
117     if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
118         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
120     if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
121         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
123     if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
124         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
126     if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
127         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
129     if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
130         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
132     if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
133         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
135     if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
136         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
138     if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
139         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
141     if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
142         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
144     /* Allow the configuration to occur */
145     v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
146     EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
147     DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
149     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0) 
150         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
152     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0) 
153         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
155     v = cfg->sdRamRefreshCtl;
156     EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
157     DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
158 #endif
159     KICK0 = 0x83E70B13;
160     KICK1 = 0x95A4F1E0;
161     
162     DDR3PLLCTL0 = 0x100807C1;
164     DDR_SDTIM1   = 0x0CCF369B;
165     DDR_SDTIM2   = 0x3A3F7FDA;
166     DDR_SDTIM3   = 0x057F83A8;
167     DDR_PMCTL   |= (0x9 << 4); // Set up SR_TIM to Enter self-refresh after 4096 clocks
168    
169     DDR_DDRPHYC  = 0x0010010B;
170    
171     DDR_SDRFC = 0x00004111; //500us
173     
174     DDR_SDCFG    = 0x63C51A32; //0x63C51A32;    //row-col = 13-10
175    
176         
177         //Values with invertclkout = 0
178         DATA0_GTLVL_INIT_RATIO = 0x3C;
179         DATA1_GTLVL_INIT_RATIO = 0x3C;
180         DATA2_GTLVL_INIT_RATIO = 0x23;
181         DATA3_GTLVL_INIT_RATIO = 0x2D;
182         DATA4_GTLVL_INIT_RATIO = 0x13;
183         DATA5_GTLVL_INIT_RATIO = 0x11;
184         DATA6_GTLVL_INIT_RATIO = 0x9;
185         DATA7_GTLVL_INIT_RATIO = 0xC;
186         //DATA8_GTLVL_INIT_RATIO = 0x21; //ECC byte lane. Don't care as long as you don't enable ECC by software
187         
188         //Values with invertclkout = 0  
189         RDWR_INIT_RATIO_0 = 0x0;
190         RDWR_INIT_RATIO_1 = 0x0;
191         RDWR_INIT_RATIO_2 = 0x0;
192         RDWR_INIT_RATIO_3 = 0x0;
193         RDWR_INIT_RATIO_4 = 0x0;
194         RDWR_INIT_RATIO_5 = 0x0;
195         RDWR_INIT_RATIO_6 = 0x0;
196         RDWR_INIT_RATIO_7 = 0x0;
197         //RDWR_INIT_RATIO_8 = 0x0; //ECC byte lane. Don't care as long as you don't enable ECC by software
198         
199         
200         
201         //GEL_TextOut("\nProgrammed initial ratios.\n");
202         
203         DDR3_CONFIG_REG_0 = DDR3_CONFIG_REG_0 | 0xF;
204         
205         //DDR3_CONFIG_REG_23 = RD_DQS_SLAVE_RATIO_1066 | (WR_DQS_SLAVE_RATIO_1066 << 10) | (WR_DATA_SLAVE_RATIO_1066 << 20);
207         DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS
208         //GEL_TextOut("\nSet bit 9 = 1 for forced ratio read eye leveling.\n");
210         DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
211     DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value                                                         //(0x34) instead
212         //GEL_TextOut("\n Triggered full leveling.\n");
214         DDR_SDTIM1; //Read MMR to ensure full leveling is complete
215     
216         DDR_SDRFC    = 0x00001040; //Refresh rate = Round[7.8*666.5MHz] = 0x1450
217         
219     return (0);
221 } /* hwEmif4p0Enable */
223