d06a38e05b5eb48fba55c240e525d26c0f6380b1
[keystone-rtos/ibl.git] / src / hw / ddrs / emif4 / emif4.c
1 /*************************************************************************************************
2  * FILE PURPOSE: EMIF4 driver
3  *************************************************************************************************
4  * FILE NAME: emif4.c
5  *
6  * DESCRIPTION: The boot emif4 driver
7  *
8  *************************************************************************************************/
9 #include "types.h"
10 #include "ibl.h"
11 #include "emif4_api.h"
12 #include "emif4_loc.h"
13 #include "device.h"
15 #define CHIP_LEVEL_REG  0x02620000
17 #define KICK0                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0038)
18 #define KICK1                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x003C)
19 #define KICK0_UNLOCK            0x83e70b13
20 #define KICK1_UNLOCK            0x95a4f1e0
22 #define DDR3PLLCTL0             *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330)
23 #define DDR3PLLCTL1             *(unsigned int*)(CHIP_LEVEL_REG + 0x0334)
25 // DDR3 definitions
26 #define DDR_BASE_ADDR 0x21000000
28 #define DDR_MIDR               (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000000))
29 #define DDR_SDCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000008))
30 #define DDR_SDRFC              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000010))
31 #define DDR_SDTIM1             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000018))
32 #define DDR_SDTIM2             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000020))
33 #define DDR_SDTIM3             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000028))
34 #define DDR_PMCTL              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000038))
35 #define DDR_RDWR_LVL_RMP_CTRL  (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
36 #define DDR_RDWR_LVL_CTRL      (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
37 #define DDR_DDRPHYC            (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000E4))
38 #define DDR_ZQCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000C8))
40 #define DATA0_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262043C))
41 #define DATA1_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620440))
42 #define DATA2_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620444))
43 #define DATA3_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620448))
44 #define DATA4_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262044C))
45 #define DATA5_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620450))
46 #define DATA6_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620454))
47 #define DATA7_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620458))
48 #define DATA8_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262045C))
50 #define DATA0_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262040C))
51 #define DATA1_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620410))
52 #define DATA2_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620414))
53 #define DATA3_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620418))
54 #define DATA4_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262041C))
55 #define DATA5_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620420))
56 #define DATA6_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620424))
57 #define DATA7_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620428))
58 #define DATA8_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262042C))
60 #define RDWR_INIT_RATIO_0       (*(volatile unsigned int*)(0x0262040C))
61 #define RDWR_INIT_RATIO_1       (*(volatile unsigned int*)(0x02620410))
62 #define RDWR_INIT_RATIO_2       (*(volatile unsigned int*)(0x02620414))
63 #define RDWR_INIT_RATIO_3       (*(volatile unsigned int*)(0x02620418))
64 #define RDWR_INIT_RATIO_4       (*(volatile unsigned int*)(0x0262041C))
65 #define RDWR_INIT_RATIO_5       (*(volatile unsigned int*)(0x02620420))
66 #define RDWR_INIT_RATIO_6       (*(volatile unsigned int*)(0x02620424))
67 #define RDWR_INIT_RATIO_7       (*(volatile unsigned int*)(0x02620428))
68 #define RDWR_INIT_RATIO_8       (*(volatile unsigned int*)(0x0262042C))
71 #define DDR3_CONFIG_REG_0   (*(volatile unsigned int*)(0x02620404))
72 #define DDR3_CONFIG_REG_12  (*(volatile unsigned int*)(0x02620434))
73 #define DDR3_CONFIG_REG_13  (*(volatile unsigned int*)(0x02620460))
74 #define DDR3_CONFIG_REG_23  (*(volatile unsigned int*)(0x02620460))
75 #define DDR3_CONFIG_REG_24  (*(volatile unsigned int*)(0x02620464))
77 #define RD_DQS_SLAVE_RATIO 0x34
78 #define WR_DQS_SLAVE_RATIO 0xA9
79 #define WR_DATA_SLAVE_RATIO 0xE9
80 #define FIFO_WE_SLAVE_RATIO 0x106
83 static void ddr3_wait (uint32 del)
84 {
85     volatile unsigned int i;
87     for (i = 0; i < del; i++);
89 }
91 /*************************************************************************************************
92  * FUNCTION PUROPSE: Initial EMIF4 setup
93  *************************************************************************************************
94  * DESCRIPTION: Emif configuration
95  *************************************************************************************************/
96 SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
97 {
98     UINT32 v, i, TEMP;
99     
100     v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
101     v &= DEVICE_JTAG_ID_MASK;
102     
103     if ( (v == DEVICE_C6678_JTAG_ID_VAL) ||
104          (v == DEVICE_C6670_JTAG_ID_VAL) )
105     {
108         KICK0 = KICK0_UNLOCK;
109         KICK1 = KICK1_UNLOCK;
111         /* 1333 MHz data rate */
112         /***************** 2.2 DDR3 PLL Configuration ************/
113         DDR3PLLCTL1 |= 0x00000040;      //Set ENSAT bit = 1
114         DDR3PLLCTL1 |= 0x00002000;      //Set RESET bit = 1
115         DDR3PLLCTL0 = 0x090804C0;       //Configure CLKR, CLKF, CLKOD, BWADJ
117         for (i = 0;i < 20;i++)
118                 ddr3_wait(1000);                //Wait for reset to complete
120         DDR3PLLCTL1 &= ~(0x00002000);   //Clear RESET bit
122         for (i = 0;i < 500;i++)
123                 ddr3_wait(1000);                //Wait for PLL lock
126         /**************** 3.0 Leveling Register Configuration ********************/
127         /* Using partial automatic leveling due to errata */
128         
129        /**************** 3.2 Invert Clock Out ********************/
130         DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
131         DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
132         DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
133         DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15
134         DDR3_CONFIG_REG_23 |= 0x00000200;    //Set bit 9 = 1 to use forced ratio leveling for read DQS
135             
136        //Values with invertclkout = 1
137       /**************** 3.3+3.4 Partial Automatic Leveling ********************/
138       DATA0_WRLVL_INIT_RATIO = 0x5E;
139       DATA1_WRLVL_INIT_RATIO = 0x5E;
140       DATA2_WRLVL_INIT_RATIO = 0x5E;
141       DATA3_WRLVL_INIT_RATIO = 0x51;
142       DATA4_WRLVL_INIT_RATIO = 0x38;
143       DATA5_WRLVL_INIT_RATIO = 0x3A;
144       DATA6_WRLVL_INIT_RATIO = 0x24;
145       DATA7_WRLVL_INIT_RATIO = 0x20;
146       DATA8_WRLVL_INIT_RATIO = 0x44;
148       DATA0_GTLVL_INIT_RATIO = 0xDD;
149       DATA1_GTLVL_INIT_RATIO = 0xDD;
150       DATA2_GTLVL_INIT_RATIO = 0xBE;
151       DATA3_GTLVL_INIT_RATIO = 0xCA;
152       DATA4_GTLVL_INIT_RATIO = 0xA9;
153       DATA5_GTLVL_INIT_RATIO = 0xA7;
154       DATA6_GTLVL_INIT_RATIO = 0x9E;
155       DATA7_GTLVL_INIT_RATIO = 0xA1;
156       DATA8_GTLVL_INIT_RATIO = 0xBA;
157   
158       //Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0
159       DDR_DDRPHYC &= ~(0x00008000);
160       DDR_DDRPHYC |= (0x00008000);
161       DDR_DDRPHYC &= ~(0x00008000);
163       /***************** 2.3 Basic Controller and DRAM configuration ************/
164       DDR_SDRFC    = 0x00005162;    // enable configuration 
166       /* DDR_SDTIM1   = 0x1113783C; */
167        TEMP = 0;
168        TEMP |= 0x8 << 25; // T_RP bit field 28:25
169        TEMP |= 0x8 << 21; // T_RCD bit field 24:21
170        TEMP |= 0x9 << 17; // T_WR bit field 20:17
171        TEMP |= 0x17 << 12; // T_RAS bit field 16:12
172        TEMP |= 0x20 << 6; // T_RC bit field 11:6
173        TEMP |= 0x7 << 3; // T_RRD bit field 5:3
174        TEMP |= 0x4; // T_WTR bit field 2:0
175        DDR_SDTIM1 = TEMP;
177       /* DDR_SDTIM2   = 0x304F7FE3; */
178        TEMP = 0;
179        TEMP |= 0x3 << 28; // T_XP bit field 30:28
180        TEMP |= 0x4f << 16; // T_XSNR bit field 24:16
181        TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6
182        TEMP |= 0x4 << 3; // T_RTP bit field 5:3
183        TEMP |= 0x3; // T_CKE bit field 2:0
184        DDR_SDTIM2 = TEMP;
186       /*  DDR_SDTIM3   = 0x559F849F; */
187        TEMP = 0;
188        TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)
189        TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)
190        TEMP |= 0x4 << 21; // T_CKESR bit field 23:21
191        TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15
192        TEMP |= 0x49 << 4; // T_RFC bit field 12:4
193        TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value)
194        DDR_SDTIM3 = TEMP; 
196         DDR_DDRPHYC  = 0x0010010F;
197      
198         DDR_ZQCFG    = 0x70073214; 
200         DDR_PMCTL    = 0x0;
201      
202         DDR_SDRFC = 0x00005162; // enable configuration
204         /* DDR_SDCFG    = 0x63062A32; */
205         /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32;    // last config write DRAM init occurs */
206          TEMP = 0;
207          TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)
208          TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27
209          TEMP |= 0x3 << 24; // DDR_TERM bit field 26:24
210          TEMP |= 0x0 << 21; // DYN_ODT bit field 22:21
211          TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18
212          TEMP |= 0x2 << 16; // CWL bit field 17:16
213          TEMP |= 0x0 << 14; // NM bit field 15:14
214          TEMP |= 0xA << 10; // CL bit field 13:10
215          TEMP |= 0x4 << 7; // ROWSIZE bit field 9:7
216          TEMP |= 0x3 << 4; // IBANK bit field 6:4
217          TEMP |= 0x0 << 3; // EBANK bit field 3:3
218          TEMP |= 0x2; // PAGESIZE bit field 2:0
219          DDR_SDCFG = TEMP;
221         for (i = 0; i < 12000; i++) {
222                 ddr3_wait(1000);             //Wait 600us for HW init to complete
223         }
225         DDR_SDRFC = 0x00001450;       //Refresh rate = (7.8*666MHz]
227         DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
228    
229         /*Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value
230           Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.
231           Actual time = ~10-15 ms */
232         DDR_RDWR_LVL_CTRL = 0x80000000; 
234         for (i = 0; i < 30000; i++) {
235                 ddr3_wait(1000); //Wait 3ms for leveling to complete
236         }
237     }
238     else
239     {
240         /* C64x configuration */
241         /* If the config registers or refresh control registers are being written
242          * disable the initialization sequence until they are all setup */
243         if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0)  {
244             
245             v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
246             EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
247             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
248         }
249         
250         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
251             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
252         
253         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
254             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
255         
256         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
257             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
258         
259         if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
260             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
261         
262         if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
263             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
264         
265         if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
266             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
267         
268         if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
269             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
270         
271         if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
272             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
273         
274         if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
275             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
276         
277         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
278             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
279         
280         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
281             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
282         
283         if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
284             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
285         
286         if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
287             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
288         
289         if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
290             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
291         
292         if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
293             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
294         
295         if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
296             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
297         
298         if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
299             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
300         
301         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
302             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
303         
304         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
305             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
306         
307         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
308             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
309         
310         if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
311             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
312         
313         /* Allow the configuration to occur */
314         v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
315         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
316         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
317         
318         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
319             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
320         
321         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
322             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
323         
324         v = cfg->sdRamRefreshCtl;
325         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
326         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
327     }
328     
329     return (0);
331 } /* hwEmif4p0Enable */