Merge branch 'nysh_multi_boot'
[keystone-rtos/ibl.git] / src / hw / ddrs / emif4 / emif4.c
1 /*************************************************************************************************
2  * FILE PURPOSE: EMIF4 driver
3  *************************************************************************************************
4  * FILE NAME: emif4.c
5  *
6  * DESCRIPTION: The boot emif4 driver
7  *
8  *************************************************************************************************/
9 #include "types.h"
10 #include "ibl.h"
11 #include "emif4_api.h"
12 #include "emif4_loc.h"
13 #include "device.h"
15 #define CHIP_LEVEL_REG  0x02620000
17 #define KICK0                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0038)
18 #define KICK1                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x003C)
20 #define DDR3PLLCTL0             *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330)
21 #define DDR3PLLCTL1             *(unsigned int*)(CHIP_LEVEL_REG + 0x0334)
23 // DDR3 definitions
24 #define DDR_BASE_ADDR 0x21000000
26 #define DDR_MIDR               (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000000))
27 #define DDR_SDCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000008))
28 #define DDR_SDRFC              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000010))
29 #define DDR_SDTIM1             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000018))
30 #define DDR_SDTIM2             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000020))
31 #define DDR_SDTIM3             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000028))
32 #define DDR_PMCTL              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000038))
33 #define DDR_RDWR_LVL_RMP_CTRL  (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
34 #define DDR_RDWR_LVL_CTRL      (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
35 #define DDR_DDRPHYC            (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000E4))
36 #define DDR_ZQCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000C8))
38 #define DATA0_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262043C))
39 #define DATA1_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620440))
40 #define DATA2_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620444))
41 #define DATA3_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620448))
42 #define DATA4_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262044C))
43 #define DATA5_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620450))
44 #define DATA6_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620454))
45 #define DATA7_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620458))
46 #define DATA8_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262045C))
48 #define DATA0_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262040C))
49 #define DATA1_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620410))
50 #define DATA2_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620414))
51 #define DATA3_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620418))
52 #define DATA4_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262041C))
53 #define DATA5_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620420))
54 #define DATA6_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620424))
55 #define DATA7_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620428))
56 #define DATA8_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262042C))
58 #define RDWR_INIT_RATIO_0       (*(volatile unsigned int*)(0x0262040C))
59 #define RDWR_INIT_RATIO_1       (*(volatile unsigned int*)(0x02620410))
60 #define RDWR_INIT_RATIO_2       (*(volatile unsigned int*)(0x02620414))
61 #define RDWR_INIT_RATIO_3       (*(volatile unsigned int*)(0x02620418))
62 #define RDWR_INIT_RATIO_4       (*(volatile unsigned int*)(0x0262041C))
63 #define RDWR_INIT_RATIO_5       (*(volatile unsigned int*)(0x02620420))
64 #define RDWR_INIT_RATIO_6       (*(volatile unsigned int*)(0x02620424))
65 #define RDWR_INIT_RATIO_7       (*(volatile unsigned int*)(0x02620428))
66 #define RDWR_INIT_RATIO_8       (*(volatile unsigned int*)(0x0262042C))
69 #define DDR3_CONFIG_REG_0   (*(volatile unsigned int*)(0x02620404))
70 #define DDR3_CONFIG_REG_12  (*(volatile unsigned int*)(0x02620434))
71 #define DDR3_CONFIG_REG_13  (*(volatile unsigned int*)(0x02620460))
72 #define DDR3_CONFIG_REG_23  (*(volatile unsigned int*)(0x02620460))
73 #define DDR3_CONFIG_REG_24  (*(volatile unsigned int*)(0x02620464))
75 #define RD_DQS_SLAVE_RATIO 0x34
76 #define WR_DQS_SLAVE_RATIO 0xA9
77 #define WR_DATA_SLAVE_RATIO 0xE9
78 #define FIFO_WE_SLAVE_RATIO 0x106
81 static void ddr3_wait (uint32 del)
82 {
83     volatile unsigned int i;
85     for (i = 0; i < del; i++);
87 }
89 /*************************************************************************************************
90  * FUNCTION PUROPSE: Initial EMIF4 setup
91  *************************************************************************************************
92  * DESCRIPTION: Emif configuration
93  *************************************************************************************************/
94 SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
95 {
96     UINT32 v, i;
97     
98     v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
99     
100     if (v == DEVICE_C6618_JTAG_ID_VAL)
101     {
102 #if 0
103         /* C6678 Old 1066 configuration */
104         DDR3PLLCTL0 = 0x100807C1;
105         
106         DDR_SDTIM1   = 0x0CCF369B;
107         DDR_SDTIM2   = 0x3A3F7FDA;
108         DDR_SDTIM3   = 0x057F83A8;
109         DDR_PMCTL   |= (0x9 << 4); // Set up SR_TIM to Enter self-refresh after 4096 clocks
110         
111         DDR_DDRPHYC  = 0x0010010B;
112         
113         DDR_SDRFC = 0x00004111; //500us
114         
115         
116         DDR_SDCFG    = 0x63C51A32; //0x63C51A32;    //row-col = 13-10
117         
118         
119         //Values with invertclkout = 0
120         DATA0_GTLVL_INIT_RATIO = 0x3C;
121         DATA1_GTLVL_INIT_RATIO = 0x3C;
122         DATA2_GTLVL_INIT_RATIO = 0x23;
123         DATA3_GTLVL_INIT_RATIO = 0x2D;
124         DATA4_GTLVL_INIT_RATIO = 0x13;
125         DATA5_GTLVL_INIT_RATIO = 0x11;
126         DATA6_GTLVL_INIT_RATIO = 0x9;
127         DATA7_GTLVL_INIT_RATIO = 0xC;
128         //DATA8_GTLVL_INIT_RATIO = 0x21; //ECC byte lane. Don't care as long as you don't enable ECC by software
129         
130         //Values with invertclkout = 0
131         RDWR_INIT_RATIO_0 = 0x0;
132         RDWR_INIT_RATIO_1 = 0x0;
133         RDWR_INIT_RATIO_2 = 0x0;
134         RDWR_INIT_RATIO_3 = 0x0;
135         RDWR_INIT_RATIO_4 = 0x0;
136         RDWR_INIT_RATIO_5 = 0x0;
137         RDWR_INIT_RATIO_6 = 0x0;
138         RDWR_INIT_RATIO_7 = 0x0;
139         //RDWR_INIT_RATIO_8 = 0x0; //ECC byte lane. Don't care as long as you don't enable ECC by software
140         
141         
142         
143         //GEL_TextOut("\nProgrammed initial ratios.\n");
144         
145         DDR3_CONFIG_REG_0 = DDR3_CONFIG_REG_0 | 0xF;
146         
147         //DDR3_CONFIG_REG_23 = RD_DQS_SLAVE_RATIO_1066 | (WR_DQS_SLAVE_RATIO_1066 << 10) | (WR_DATA_SLAVE_RATIO_1066 << 20);
148         
149         DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS
150         //GEL_TextOut("\nSet bit 9 = 1 for forced ratio read eye leveling.\n");
151         
152         DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
153         DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value                                                     //(0x34) instead
154         //GEL_TextOut("\n Triggered full leveling.\n");
155         
156         DDR_SDTIM1; //Read MMR to ensure full leveling is complete
157         
158         DDR_SDRFC    = 0x00001040; //Refresh rate = Round[7.8*666.5MHz] = 0x1450
159 #endif
160 #if 1
161         /* C6678 1333 MHz data rate */
162         /***************** 2.2 DDR3 PLL Configuration ************/
163         DDR3PLLCTL1 |= 0x00000040;      //Set ENSAT bit = 1
164         DDR3PLLCTL1 |= 0x00002000;      //Set RESET bit = 1
165         DDR3PLLCTL0 = 0x090804C0;       //Configure CLKR, CLKF, CLKOD, BWADJ
166         ddr3_wait(1000);               //Wait for reset to complete
167         DDR3PLLCTL1 &= ~(0x00002000);   //Clear RESET bit
168         ddr3_wait(1000);              //Wait for PLL lock
169         
170         /***************** 2.3 Basic Controller and DRAM configuration ************/
171         DDR_SDRFC    = 0x80005162;    // inhibit configuration 
172         
173         DDR_SDTIM1   = 0x1113783C;
174         DDR_SDTIM2   = 0x304F7FE3;
175         DDR_SDTIM3   = 0x559F849F;
176         
177         DDR_DDRPHYC  = 0x0010010F;
178         
179         DDR_ZQCFG    = 0x70073214;
180         
181         DDR_PMCTL    = 0x0;
182         
183         DDR_SDRFC    = 0x00005162;    // enable configuration
184         DDR_SDCFG    = 0x63222A32;    // last config write \96 DRAM init occurs
185         
186         ddr3_wait(1000);            //Wait for HW init to complete
187         DDR_SDRFC = 0x00001450;       //Refresh rate = (7.8*666MHz]
188         
189         /**************** 3.0 Leveling Register Configuration ********************/
190         /* Using partial automatic leveling due to errata */
191         
192         /**************** 3.2 Invert Clock Out ********************/
193         DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
194         DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
195         DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
196         DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15
197         
198         
199         /**************** 3.3+3.4 Partial Automatic Leveling ********************/
200         DATA0_WRLVL_INIT_RATIO = 0x20;
201         DATA1_WRLVL_INIT_RATIO = 0x24;
202         DATA2_WRLVL_INIT_RATIO = 0x3A;
203         DATA3_WRLVL_INIT_RATIO = 0x38;
204         DATA4_WRLVL_INIT_RATIO = 0x51;
205         DATA5_WRLVL_INIT_RATIO = 0x5E;
206         DATA6_WRLVL_INIT_RATIO = 0x5E;
207         DATA7_WRLVL_INIT_RATIO = 0x5E;
208         DATA8_WRLVL_INIT_RATIO = 0x44;
209         
210         DATA0_GTLVL_INIT_RATIO = 0xA1;
211         DATA1_GTLVL_INIT_RATIO = 0x9E;
212         DATA2_GTLVL_INIT_RATIO = 0xA7;
213         DATA3_GTLVL_INIT_RATIO = 0xA9;
214         DATA4_GTLVL_INIT_RATIO = 0xCA;
215         DATA5_GTLVL_INIT_RATIO = 0xBE;
216         DATA6_GTLVL_INIT_RATIO = 0xDD;
217         DATA7_GTLVL_INIT_RATIO = 0xDD;
218         DATA8_GTLVL_INIT_RATIO = 0xBA;
219         
220         DDR3_CONFIG_REG_23 |= 0x00000200;
221         DDR_RDWR_LVL_RMP_CTRL = 0x80000000;
222         DDR_RDWR_LVL_CTRL = 0x80000000;
223 #endif
224         
225 #if 0
226         /* C6678 New 1066 rate */
227         /***************** 2.2 DDR3 PLL Configuration ************/
228         DDR3PLLCTL1 |= 0x00000040;      //Set ENSAT bit = 1
229         DDR3PLLCTL1 |= 0x00002000;      //Set RESET bit = 1
230         DDR3PLLCTL0 = 0x0F0807C1;       //Configure CLKR, CLKF, CLKOD, BWADJ
231         ddr3_wait(1000);              //Wait for reset to complete
232         DDR3PLLCTL1 &= ~(0x00002000);   //Clear RESET bit
233         ddr3_wait(1000);
234         
235         /***************** 2.3 Basic Controller and DRAM configuration ************/
236         DDR_SDRFC    = 0x8000411B;    // inhibit configuration 
237         DDR_SDTIM1   = 0x0CCF36B3;
238         DDR_SDTIM2   = 0x303F7FDA;
239         DDR_SDTIM3   = 0x559F83AF;
240         
241         DDR_DDRPHYC  = 0x0010010A;
242         DDR_ZQCFG    = 0x70073214;
243         
244         //DDR_PMCTL    = 0x0;
245         DDR_SDRFC    = 0x0000411B;    // enable configuration
246         DDR_SDCFG    = 0x63211A32;    // last config write \96 DRAM init occurs
247         
248         ddr3_wait(1000);             //Wait for HW init to complete
249         
250         DDR_SDRFC = 0x00001040;       //Refresh rate = (7.8*666MHz]
251         
252         /**************** 3.0 Leveling Register Configuration ********************/
253         /* Using partial automatic leveling due to errata */
254         
255         /**************** 3.2 Invert Clock Out ********************/
256         DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
257         DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
258         DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
259         DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15
260         
261         /**************** 3.3+3.4 Partial Automatic Leveling ********************/
262         DATA0_WRLVL_INIT_RATIO = 0x19;//0x4C;
263         DATA1_WRLVL_INIT_RATIO = 0x1C;//0x4C;
264         DATA2_WRLVL_INIT_RATIO = 0x2F;//0x4C;
265         DATA3_WRLVL_INIT_RATIO = 0x2D;//0x42;
266         DATA4_WRLVL_INIT_RATIO = 0x42;//0x2D;
267         DATA5_WRLVL_INIT_RATIO = 0x4C;//0x2F;
268         DATA6_WRLVL_INIT_RATIO = 0x4C;//0x1C;
269         DATA7_WRLVL_INIT_RATIO = 0x4C;//0x19;
270         DATA8_WRLVL_INIT_RATIO = 0x37;
271         
272         DATA0_GTLVL_INIT_RATIO = 0x8D;//0xBC;
273         DATA1_GTLVL_INIT_RATIO = 0x8A;//0xBC;
274         DATA2_GTLVL_INIT_RATIO = 0x91;//0xA4;
275         DATA3_GTLVL_INIT_RATIO = 0x93;//0xAE;
276         DATA4_GTLVL_INIT_RATIO = 0xAE;//0x93;
277         DATA5_GTLVL_INIT_RATIO = 0xA4;//0x91;
278         DATA6_GTLVL_INIT_RATIO = 0xBC;//0x8A;
279         DATA7_GTLVL_INIT_RATIO = 0xBC;//0x8D;
280         DATA8_GTLVL_INIT_RATIO = 0xA1;
281         
282         DDR3_CONFIG_REG_23 |= 0x00000200;
283         DDR_RDWR_LVL_RMP_CTRL = 0x80000000;
284         DDR_RDWR_LVL_CTRL = 0x80000000;
285 #endif
286     }
287     else if (v == DEVICE_C6616_JTAG_ID_VAL)
288     {
289         /* C6670 800 M rate */
290         DDR3PLLCTL1 |= 0x00000040;    //Set ENSAT = 1
291         DDR3PLLCTL1 |= 0x00002000;    //Set RESET bit before programming DDR3PLLCTL0
292         DDR3PLLCTL0 = 0x02000140;
293         
294         for(i=0;i<1000;i++); //Wait atleast 5us
295         DDR3PLLCTL1 &= 0xFFFFDFFF;    //Clear RESET bit
296         
297         DDR_SDRFC    = 0x800030D4;    // inhibit configuration
298         
299         DDR_SDTIM1   = 0x0AAAE4E3;
300         DDR_SDTIM2   = 0x20437FDA;
301         DDR_SDTIM3   = 0x559F83FF;
302         
303         DDR_DDRPHYC  = 0x0010010F;
304         
305         DDR_SDRFC    = 0x000030D4;    // enable configuration
306         
307         DDR_SDCFG    = 0x63222AB2;    // DRAM Mode Register writes occur here - 31.25us long refresh periods
308         
309         DDR3_CONFIG_REG_0 |= 0xF;         // set dll_lock_diff to 15
310         DDR3_CONFIG_REG_0 &= 0xFF801FFF;  // clear ctrl_slave_ratio field
311         DDR3_CONFIG_REG_0 |= 0x00200000;  // set ctrl_slave_ratio field to 256 since INV_CLKOUT = 1
312         
313         DDR3_CONFIG_REG_12 |= 0x08000000; // Set INV_CLKOUT = 1
314         
315         DDR3_CONFIG_REG_23 = RD_DQS_SLAVE_RATIO | (WR_DQS_SLAVE_RATIO << 10) | (WR_DATA_SLAVE_RATIO << 20);
316         DDR3_CONFIG_REG_24 = FIFO_WE_SLAVE_RATIO;
317         
318         
319         DDR_SDRFC    = 0x00000C30; //Refresh rate = Round[7.8*400MHz] = 0x0C30
320     }
321     else
322     {
323         /* C64x configuration */
324         /* If the config registers or refresh control registers are being written
325          * disable the initialization sequence until they are all setup */
326         if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0)  {
327             
328             v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
329             EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
330             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
331         }
332         
333         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
334             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
335         
336         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
337             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
338         
339         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
340             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
341         
342         if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
343             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
344         
345         if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
346             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
347         
348         if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
349             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
350         
351         if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
352             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
353         
354         if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
355             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
356         
357         if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
358             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
359         
360         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
361             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
362         
363         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
364             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
365         
366         if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
367             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
368         
369         if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
370             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
371         
372         if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
373             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
374         
375         if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
376             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
377         
378         if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
379             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
380         
381         if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
382             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
383         
384         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
385             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
386         
387         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
388             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
389         
390         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
391             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
392         
393         if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
394             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
395         
396         /* Allow the configuration to occur */
397         v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
398         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
399         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
400         
401         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
402             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
403         
404         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
405             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
406         
407         v = cfg->sdRamRefreshCtl;
408         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
409         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
410     }
411     
412     return (0);
414 } /* hwEmif4p0Enable */