Initial c661x version
[keystone-rtos/ibl.git] / src / hw / ddrs / emif4 / emif4.c
1 /*************************************************************************************************
2  * FILE PURPOSE: EMIF4 driver
3  *************************************************************************************************
4  * FILE NAME: emif4.c
5  *
6  * DESCRIPTION: The boot emif4 driver
7  *
8  *************************************************************************************************/
9 #include "types.h"
10 #include "ibl.h"
11 #include "emif4_api.h"
12 #include "emif4_loc.h"
13 #include "device.h"
15 /*************************************************************************************************
16  * FUNCTION PUROPSE: Initial EMIF4 setup
17  *************************************************************************************************
18  * DESCRIPTION: Emif configuration
19  *************************************************************************************************/
20 SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
21 {
22     UINT32 v;
24     /* If the config registers or refresh control registers are being written
25      * disable the initialization sequence until they are all setup */
26     if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0)  {
28         v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
29         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
30         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
31     }
33     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
34         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
36     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
37         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
39     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
40         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
42     if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
43         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
45     if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
46         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
48     if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
49         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
51     if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
52         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
54     if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
55         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
57     if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
58         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
60     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
61         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
63     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
64         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
66     if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
67         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
69     if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
70         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
72     if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
73         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
75     if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
76         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
78     if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
79         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
81     if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
82         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
84     if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
85         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
87     if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
88         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
90     if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
91         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
93     if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
94         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
96     /* Allow the configuration to occur */
97     v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
98     EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
99     DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
101     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0) 
102         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
104     if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0) 
105         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
107     v = cfg->sdRamRefreshCtl;
108     EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
109     DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
111     return (0);
113 } /* hwEmif4p0Enable */
115