src/hw/ddrs/emif4/emif4.c

   1 /*************************************************************************************************
   2  * FILE PURPOSE: EMIF4 driver
   3  *************************************************************************************************
   4  * FILE NAME: emif4.c
   5  *
   6  * DESCRIPTION: The boot emif4 driver
   7  *
   8  *************************************************************************************************/
   9 #include "types.h"
  10 #include "ibl.h"
  11 #include "emif4_api.h"
  12 #include "emif4_loc.h"
  13 #include "device.h"
  14
  15 #define CHIP_LEVEL_REG  0x02620000
  16
  17 #define KICK0                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0038)
  18 #define KICK1                   *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x003C)
  19 #define KICK0_UNLOCK            0x83e70b13
  20 #define KICK1_UNLOCK            0x95a4f1e0
  21
  22 #define DDR3PLLCTL0             *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330)
  23 #define DDR3PLLCTL1             *(unsigned int*)(CHIP_LEVEL_REG + 0x0334)
  24
  25 // DDR3 definitions
  26 #define DDR_BASE_ADDR 0x21000000
  27
  28 #define DDR_MIDR               (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000000))
  29 #define DDR_SDCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000008))
  30 #define DDR_SDRFC              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000010))
  31 #define DDR_SDTIM1             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000018))
  32 #define DDR_SDTIM2             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000020))
  33 #define DDR_SDTIM3             (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000028))
  34 #define DDR_PMCTL              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000038))
  35 #define DDR_RDWR_LVL_RMP_CTRL  (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
  36 #define DDR_RDWR_LVL_CTRL      (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
  37 #define DDR_DDRPHYC            (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000E4))
  38 #define DDR_ZQCFG              (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000C8))
  39
  40 #define DATA0_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262043C))
  41 #define DATA1_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620440))
  42 #define DATA2_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620444))
  43 #define DATA3_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620448))
  44 #define DATA4_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262044C))
  45 #define DATA5_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620450))
  46 #define DATA6_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620454))
  47 #define DATA7_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x02620458))
  48 #define DATA8_GTLVL_INIT_RATIO  (*(volatile unsigned int*)(0x0262045C))
  49
  50 #define DATA0_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262040C))
  51 #define DATA1_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620410))
  52 #define DATA2_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620414))
  53 #define DATA3_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620418))
  54 #define DATA4_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262041C))
  55 #define DATA5_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620420))
  56 #define DATA6_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620424))
  57 #define DATA7_WRLVL_INIT_RATIO  (*(unsigned int*)(0x02620428))
  58 #define DATA8_WRLVL_INIT_RATIO  (*(unsigned int*)(0x0262042C))
  59
  60 #define RDWR_INIT_RATIO_0       (*(volatile unsigned int*)(0x0262040C))
  61 #define RDWR_INIT_RATIO_1       (*(volatile unsigned int*)(0x02620410))
  62 #define RDWR_INIT_RATIO_2       (*(volatile unsigned int*)(0x02620414))
  63 #define RDWR_INIT_RATIO_3       (*(volatile unsigned int*)(0x02620418))
  64 #define RDWR_INIT_RATIO_4       (*(volatile unsigned int*)(0x0262041C))
  65 #define RDWR_INIT_RATIO_5       (*(volatile unsigned int*)(0x02620420))
  66 #define RDWR_INIT_RATIO_6       (*(volatile unsigned int*)(0x02620424))
  67 #define RDWR_INIT_RATIO_7       (*(volatile unsigned int*)(0x02620428))
  68 #define RDWR_INIT_RATIO_8       (*(volatile unsigned int*)(0x0262042C))
  69
  70
  71 #define DDR3_CONFIG_REG_0   (*(volatile unsigned int*)(0x02620404))
  72 #define DDR3_CONFIG_REG_12  (*(volatile unsigned int*)(0x02620434))
  73 #define DDR3_CONFIG_REG_23  (*(volatile unsigned int*)(0x02620460))
  74 #define DDR3_CONFIG_REG_24  (*(volatile unsigned int*)(0x02620464))
  75
  76 #define RD_DQS_SLAVE_RATIO 0x34
  77 #define WR_DQS_SLAVE_RATIO 0xA9
  78 #define WR_DATA_SLAVE_RATIO 0xE9
  79 #define FIFO_WE_SLAVE_RATIO 0x106
  80
  81
  82 static void ddr3_wait (uint32 del)
  83 {
  84     volatile unsigned int i;
  85
  86     for (i = 0; i < del; i++) asm (" nop ");
  87
  88 }
  89
  90 /*************************************************************************************************
  91  * FUNCTION PUROPSE: Initial EMIF4 setup
  92  *************************************************************************************************
  93  * DESCRIPTION: Emif configuration
  94  *************************************************************************************************/
  95 SINT16 hwEmif4p0Enable (iblEmif4p0_t *cfg)
  96 {
  97     UINT32 v, i, TEMP;
  98
  99     v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
 100     v &= DEVICE_JTAG_ID_MASK;
 101
 102     if ( (v == DEVICE_C6678_JTAG_ID_VAL) ||
 103          (v == DEVICE_C6670_JTAG_ID_VAL) )
 104     {
 105
 106
 107         KICK0 = KICK0_UNLOCK;
 108         KICK1 = KICK1_UNLOCK;
 109         /* Adding DDR PLL code here */
 110         DDR3PLLCTL1 |= 0x00000040;      //Set ENSAT bit = 1
 111         DDR3PLLCTL0 |= 0x00800000;      //Set BYPASS bit = 1
 112         DDR3PLLCTL1 |= 0x00002000;      //Set RESET bit = 1
 113         DDR3PLLCTL0 = 0x098804C0;       //Configure PLLM, PLLD, BWADJ
 114         DDR3PLLCTL1 &= ~(0x0000000F);   //Clear upper BWADJ
 115         ddr3_wait(7000);                //Wait at least 5us for reset to complete
 116         DDR3PLLCTL1 &= ~(0x00002000);   //Clear RESET bit
 117         ddr3_wait(70000);               //Wait >50us for PLL lock - min 500*(PLL+1) DDRCLK periods
 118         DDR3PLLCTL0 &= ~(0x00800000);   //Clear BYPASS bit
 119         /*End DDR PLL code */
 120
 121        /**************** 3.3 Leveling register configuration ********************/
 122         DDR3_CONFIG_REG_0 &= ~(0x007FE000);  // clear ctrl_slave_ratio field
 123         DDR3_CONFIG_REG_0 |= 0x00200000;     // set ctrl_slave_ratio to 0x100
 124         DDR3_CONFIG_REG_12 |= 0x08000000;    // Set invert_clkout = 1
 125         DDR3_CONFIG_REG_0 |= 0xF;            // set dll_lock_diff to 15
 126         DDR3_CONFIG_REG_23 |= 0x00000200;    // See section 4.2.1, set for partial automatic levelling
 127
 128       /**************** 3.3 Partial Automatic Leveling ********************/
 129       DATA0_WRLVL_INIT_RATIO = 0x5E;
 130       DATA1_WRLVL_INIT_RATIO = 0x5E;
 131       DATA2_WRLVL_INIT_RATIO = 0x5E;
 132       DATA3_WRLVL_INIT_RATIO = 0x51;
 133       DATA4_WRLVL_INIT_RATIO = 0x38;
 134       DATA5_WRLVL_INIT_RATIO = 0x3A;
 135       DATA6_WRLVL_INIT_RATIO = 0x24;
 136       DATA7_WRLVL_INIT_RATIO = 0x20;
 137       DATA8_WRLVL_INIT_RATIO = 0x44;
 138
 139       DATA0_GTLVL_INIT_RATIO = 0xDD;
 140       DATA1_GTLVL_INIT_RATIO = 0xDD;
 141       DATA2_GTLVL_INIT_RATIO = 0xBE;
 142       DATA3_GTLVL_INIT_RATIO = 0xCA;
 143       DATA4_GTLVL_INIT_RATIO = 0xA9;
 144       DATA5_GTLVL_INIT_RATIO = 0xA7;
 145       DATA6_GTLVL_INIT_RATIO = 0x9E;
 146       DATA7_GTLVL_INIT_RATIO = 0xA1;
 147       DATA8_GTLVL_INIT_RATIO = 0xBA;
 148
 149       //Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0
 150       DDR_DDRPHYC &= ~(0x00008000);
 151       DDR_DDRPHYC |= (0x00008000);
 152       DDR_DDRPHYC &= ~(0x00008000);
 153
 154       /***************** 3.4 Basic Controller and DRAM configuration ************/
 155       DDR_SDRFC    = 0x00005162;    // enable configuration
 156
 157       /* DDR_SDTIM1   = 0x1113783C; */
 158        TEMP = 0;
 159        TEMP |= 0x8 << 25; // T_RP bit field 28:25
 160        TEMP |= 0x8 << 21; // T_RCD bit field 24:21
 161        TEMP |= 0x9 << 17; // T_WR bit field 20:17
 162        TEMP |= 0x17 << 12; // T_RAS bit field 16:12
 163        TEMP |= 0x20 << 6; // T_RC bit field 11:6
 164        TEMP |= 0x7 << 3; // T_RRD bit field 5:3
 165        TEMP |= 0x4; // T_WTR bit field 2:0
 166        DDR_SDTIM1 = TEMP;
 167
 168       /* DDR_SDTIM2   = 0x304F7FE3; */
 169        TEMP = 0;
 170        TEMP |= 0x3 << 28; // T_XP bit field 30:28
 171        TEMP |= 0x4f << 16; // T_XSNR bit field 24:16
 172        TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6
 173        TEMP |= 0x4 << 3; // T_RTP bit field 5:3
 174        TEMP |= 0x3; // T_CKE bit field 2:0
 175        DDR_SDTIM2 = TEMP;
 176
 177       /*  DDR_SDTIM3   = 0x559F849F; */
 178        TEMP = 0;
 179        TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)
 180        TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)
 181        TEMP |= 0x4 << 21; // T_CKESR bit field 23:21
 182        TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15
 183        TEMP |= 0x49 << 4; // T_RFC bit field 12:4
 184        TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value)
 185        DDR_SDTIM3 = TEMP;
 186
 187         DDR_DDRPHYC  = 0x0010010F;
 188
 189         DDR_ZQCFG    = 0x70073214;
 190
 191         DDR_PMCTL    = 0x0;
 192
 193         DDR_SDRFC = 0x00005162; // enable configuration
 194
 195         /* DDR_SDCFG    = 0x63062A32; */
 196         /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32;    // last config write DRAM init occurs */
 197          TEMP = 0;
 198          TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)
 199          TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27
 200          TEMP |= 0x3 << 24; // DDR_TERM bit field 26:24
 201          TEMP |= 0x0 << 21; // DYN_ODT bit field 22:21
 202          TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18
 203          TEMP |= 0x2 << 16; // CWL bit field 17:16
 204          TEMP |= 0x0 << 14; // NM bit field 15:14
 205          TEMP |= 0xA << 10; // CL bit field 13:10
 206          TEMP |= 0x4 << 7; // ROWSIZE bit field 9:7
 207          TEMP |= 0x3 << 4; // IBANK bit field 6:4
 208          TEMP |= 0x0 << 3; // EBANK bit field 3:3
 209          TEMP |= 0x2; // PAGESIZE bit field 2:0
 210          DDR_SDCFG = TEMP;
 211
 212         /* assuming max device speed, 1.4GHz, 1 cycle = 0.714 ns *
 213         * so, 100 us = 100000 ns = 140056 cycles
 214           thereby, 600us=840336 */
 215          ddr3_wait(840336);             //Wait 600us for HW init to complete
 216
 217         DDR_SDRFC = 0x00001450;       //Refresh rate = (7.8*666MHz]
 218
 219       /***************** 4.2.1 Partial automatic leveling ************/
 220         DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable automatic leveling
 221
 222         /*Trigger automatic leveling - This ignores read DQS leveling result and uses ratio forced value
 223           Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.
 224           Actual time = ~10-15 ms */
 225         DDR_RDWR_LVL_CTRL = 0x80000000;
 226
 227         /* assuming max device speed, 1.4GHz, 1 cycle = 0.714 ns *
 228         * so, 100 us = 100000 ns = 140056 cycles
 229           thereby, 3ms=3000us=4201680 */
 230         ddr3_wait(4201680); //Wait 3ms for leveling to complete
 231     }
 232     else
 233     {
 234         /* C64x configuration */
 235         /* If the config registers or refresh control registers are being written
 236          * disable the initialization sequence until they are all setup */
 237         if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0)  {
 238
 239             v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
 240             EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,1);
 241             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
 242         }
 243
 244         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming1) != 0)
 245             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING1, cfg->sdRamTiming1);
 246
 247         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming2) != 0)
 248             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING2, cfg->sdRamTiming2);
 249
 250         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamTiming3) != 0)
 251             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TIMING3, cfg->sdRamTiming3);
 252
 253         if ((cfg->registerMask & ibl_EMIF4_ENABLE_lpDdrNvmTiming) != 0)
 254             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_NVM_TIMING, cfg->lpDdrNvmTiming);
 255
 256         if ((cfg->registerMask & ibl_EMIF4_ENABLE_powerManageCtl) != 0)
 257             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PWR_MNG_CTL, cfg->powerManageCtl);
 258
 259         if ((cfg->registerMask & ibl_EMIF4_ENABLE_iODFTTestLogic) != 0)
 260             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IODFT_TST_LOGIC, cfg->iODFTTestLogic);
 261
 262         if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountCfg) != 0)
 263             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_CFG, cfg->performCountCfg);
 264
 265         if ((cfg->registerMask & ibl_EMIF4_ENABLE_performCountMstRegSel) != 0)
 266             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PERFORM_CNT_MST_REG_SEL, cfg->performCountMstRegSel);
 267
 268         if ((cfg->registerMask & ibl_EMIF4_ENABLE_readIdleCtl) != 0)
 269             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_IDLE_CTL, cfg->readIdleCtl);
 270
 271         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sysVbusmIntEnSet) != 0)
 272             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_INT_EN_SET, cfg->sysVbusmIntEnSet);
 273
 274         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg) != 0)
 275             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_OUT_IMP_CAL_CFG, cfg->sdRamOutImpdedCalCfg);
 276
 277         if ((cfg->registerMask & ibl_EMIF4_ENABLE_tempAlterCfg) != 0)
 278             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_TEMP_ALTER_CFG, cfg->tempAlterCfg);
 279
 280         if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl1) != 0)
 281             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CTL1, cfg->ddrPhyCtl1);
 282
 283         if ((cfg->registerMask & ibl_EMIF4_ENABLE_ddrPhyCtl2) != 0)
 284             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PHY_CLT2, cfg->ddrPhyCtl2);
 285
 286         if ((cfg->registerMask & ibl_EMIF4_ENABLE_priClassSvceMap) != 0)
 287             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_PRI_CLASS_SVC_MAP, cfg->priClassSvceMap);
 288
 289         if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce1Map) != 0)
 290             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_1MAP, cfg->mstId2ClsSvce1Map);
 291
 292         if ((cfg->registerMask & ibl_EMIF4_ENABLE_mstId2ClsSvce2Map) != 0)
 293             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ID2CLS_SVC_2MAP, cfg->mstId2ClsSvce2Map);
 294
 295         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccCtl) != 0)
 296             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_CTL, cfg->eccCtl);
 297
 298         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange1) != 0)
 299             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE1, cfg->eccRange1);
 300
 301         if ((cfg->registerMask & ibl_EMIF4_ENABLE_eccRange2) != 0)
 302             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_ECC_RANGE2, cfg->eccRange2);
 303
 304         if ((cfg->registerMask & ibl_EMIF4_ENABLE_rdWrtExcThresh) != 0)
 305             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_RD_WRT_EXC_THRESH, cfg->rdWrtExcThresh);
 306
 307         /* Allow the configuration to occur */
 308         v = DEVICE_REG32_R (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL);
 309         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
 310         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
 311
 312         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig) != 0)
 313             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG, cfg->sdRamConfig);
 314
 315         if ((cfg->registerMask & ibl_EMIF4_ENABLE_sdRamConfig2) != 0)
 316             DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SD_RAM_CFG2, cfg->sdRamConfig2);
 317
 318         v = cfg->sdRamRefreshCtl;
 319         EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
 320         DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
 321     }
 322
 323     return (0);
 324
 325 } /* hwEmif4p0Enable */
 326
 327