1 /*
2 *
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
38 /********************************************************************************************************
39 * FILE PURPOSE: IBL configuration and control definitions
40 ********************************************************************************************************
41 * FILE NAME: ibl.h
42 *
43 * DESCRIPTION: Defines the data structure used to handle initial configuration and control
44 * of the ibl. This data structure resides at a fixed location in the device memory
45 * map. It is initially populated either during the rom boot. The table can be
46 * over-written during the ibl process to redirect the boot. For example the ibl
47 * can initially load from an i2c which repopulates this table with parameters
48 * for an ethernet boot.
49 *
50 * @file ibl.h
51 *
52 * @brief
53 * This file defines the configuration and control of the IBL
54 *
55 *
56 ********************************************************************************************************/
57 #ifndef IBL_H
58 #define IBL_H
60 #include "types.h"
63 #define ibl_MAKE_VERSION(a,b,c,d) ((a << 24) | (b << 16) | (c << 8) | (d << 0))
66 /**
67 * @brief
68 * The version number, 1.0.0.17
69 */
70 #define ibl_VERSION ibl_MAKE_VERSION(1,0,0,17)
71 /* Version string for UART write */
72 #define ibl_VERSION_STR "1.0.0.17"
74 /**
75 * @defgroup iblBootModes Defines the boot modes supported by the IBL
76 *
77 * @ingroup iblBootModes
78 * @{
79 *
80 * @def ibl_BOOT_MODE_TFTP */
81 #define ibl_BOOT_MODE_TFTP 10 /* Boot through a tftp interface */
83 /* @def ibl_BOOT_MODE_NAND */
84 #define ibl_BOOT_MODE_NAND 11 /* Boot through a nand interface */
86 /* @def ibl_BOOT_MODE_NOR */
87 #define ibl_BOOT_MODE_NOR 12 /* Boot through a nor (or flash) interface */
89 /* @def ibl_BOOT_MODE_NONE */
90 #define ibl_BOOT_MODE_NONE 13 /* Boot mode selection is inactive */
92 /* @} */
94 /**
95 * @brief
96 * Define the number of different boot modes which can be configured for
97 * a single execution of the IBL.
98 */
99 #define ibl_N_BOOT_MODES 3
101 /* Information used to make generate a bootp request */
102 /**
103 * @brief
104 * Defines parameters used for making a bootp request
105 *
106 * @details
107 * The bootp request parameters are created from these fields
108 */
109 typedef struct iblBootp_s
110 {
111 uint8 hwAddress[6]; /**< The hardware (mac) address of this device. If set to 0
112 the ibl will values from e-fuse */
114 uint8 ipDest[4]; /**< The IP address of this device. This is typically set
115 to IP broadcast */
117 } iblBootp_t;
120 /**
121 * @brief
122 * This structure contains information used for tftp boot.
123 *
124 * @details These fields are typically filled in by the bootp packet, but
125 * can be provided if bootp will not be used.
126 */
127 typedef struct iblEthBootInfo_s
128 {
129 uint8 ipAddr[4]; /**< The IP address of this device */
130 uint8 serverIp[4]; /**< The IP address of the tftp server */
131 uint8 gatewayIp[4]; /**< The IP address of the gateway */
132 uint8 netmask[4]; /**< The IP netmask */
133 uint8 hwAddress[6]; /**< The hardware (mac) address of this device */
134 char8 fileName[64]; /**< The file name to load */
136 } iblEthBootInfo_t;
139 /**
140 * @def ibl_ETH_PORT_FROM_RBL
141 */
142 #define ibl_ETH_PORT_FROM_RBL -1 /**< The ethernet port used is the same one used
143 during the ROM boot load process. */
145 /**
146 * @def ibl_PORT_SWITCH_ALL
147 */
148 #define ibl_PORT_SWITCH_ALL -2 /**< The ethernet subsystem is connected to a switch, and
149 all ports on the subsystem should be configured */
152 /**
153 * @defgroup iblBootFormats
154 *
155 * @ingroup iblBootFormats
156 * @{
157 */
158 #define ibl_BOOT_FORMAT_AUTO 0 /**< Auto determine the boot format from the data */
159 #define ibl_BOOT_FORMAT_NAME 1 /**< Determines the boot format based on file name (bootp/tftp only) */
160 #define ibl_BOOT_FORMAT_BIS 2 /**< Boot TI AIS format */
161 #define ibl_BOOT_FORMAT_COFF 3 /**< Boot a COFF file */
162 #define ibl_BOOT_FORMAT_ELF 4 /**< Boot an ELF file */
163 #define ibl_BOOT_FORMAT_BBLOB 5 /**< Boot a binary blob */
164 #define ibl_BOOT_FORMAT_BTBL 6 /**< Boot a TI boot table file */
166 /* @} */
168 /**
169 * @defgroup iblPeriphPriority Defines the boot sequence
170 *
171 * @ingroup iblPeriphPriority
172 * @{
173 * @def ibl_LOWEST_PRIORITY
174 */
175 #define ibl_LOWEST_PRIORITY 10 /**< The lowest priority assignable to a peripheral for boot */
177 /**
178 * @def ibl_HIGHEST_PRIORITY
179 */
180 #define ibl_HIGHEST_PRIORITY 1 /**< The highest priority assignable to a peripheral for boot */
182 /**
183 * @def ibl_DEVICE_NOBOOT
184 */
185 #define ibl_DEVICE_NOBOOT 20 /**< Indicates that the device is not to be used for boot */
187 /* @} */
190 /**
191 * @brief
192 * Emif controller 3.1 configuration
193 *
194 * @details
195 * The paramters are directly placed into the emif controller
196 */
197 typedef struct iblEmif3p1_s
198 {
199 uint32 sdcfg; /**< SD configuration register */
200 uint32 sdrfc; /**< Refresh timing register */
201 uint32 sdtim1; /**< DDR timing register 1 */
202 uint32 sdtim2; /**< DDR timing register 2 */
203 uint32 dmcctl; /**< CAS match timing */
205 } iblEmif3p1_t;
208 /**
209 * @brief
210 * Emif controller 4.0 configuration
211 *
212 * @details
213 * The parameters are placed directly into the emif controller
214 */
215 typedef struct iblEmif4p0_s
216 {
217 uint32 registerMask; /**< Identifies which registers will be configured */
218 uint32 sdRamConfig; /**< SDRAM Config Register */
219 uint32 sdRamConfig2; /**< SDRAM Config2 Register */
220 uint32 sdRamRefreshCtl; /**< SDRAM Refresh Control Register */
221 uint32 sdRamTiming1; /**< SDRAM Timing 1 Register */
222 uint32 sdRamTiming2; /**< SDRAM Timing 2 Register */
223 uint32 sdRamTiming3; /**< SDRAM Timing 3 Register */
224 uint32 lpDdrNvmTiming; /**< LPDDR2-NVM Timing Register */
225 uint32 powerManageCtl; /**< Power Management Control Register */
226 uint32 iODFTTestLogic; /**< IODFT Test Logic Global Control Register */
227 uint32 performCountCfg; /**< Performance Counter Config Register */
228 uint32 performCountMstRegSel; /**< Performance Counter Master Region Select Register */
229 uint32 readIdleCtl; /**< Read Idle Control Register */
230 uint32 sysVbusmIntEnSet; /**< VBUSM Interrupt Enable Set Register */
231 uint32 sdRamOutImpdedCalCfg; /**< SDRAM Output Impedance Calibratin Config Register */
232 uint32 tempAlterCfg; /**< Temperature Alert Config Register */
233 uint32 ddrPhyCtl1; /**< DDR PHY Control 1 Register */
234 uint32 ddrPhyCtl2; /**< DDR PHY Control 2 Register */
235 uint32 priClassSvceMap; /**< DDR Priority to Class of Service Mapping Register */
236 uint32 mstId2ClsSvce1Map; /**< Master ID to Class of Service 1 Mapping Register */
237 uint32 mstId2ClsSvce2Map; /**< Master ID to Class of Service 2 Mapping Register */
238 uint32 eccCtl; /**< ECC Control Register */
239 uint32 eccRange1; /**< ECC Address Range 1 Register */
240 uint32 eccRange2; /**< ECC Address Range 2 Register */
241 uint32 rdWrtExcThresh; /**< Read Write Execution Threshold Register */
243 } iblEmif4p0_t;
246 /**
247 * @defgroup iblEmif4Select Defines the EMIF4 registers configured by IBL
248 *
249 * @ingroup iblEmif4Select
250 * @{
251 * @def ibl_EMIF4_ENABLE_sdRamConfig
252 */
253 #define ibl_EMIF4_ENABLE_sdRamConfig (1 << 0)
255 /** @def ibl_EMIF4_ENABLE_sdRamConfig2 */
256 #define ibl_EMIF4_ENABLE_sdRamConfig2 (1 << 1)
258 /** @def ibl_EMIF4_ENABLE_sdRamRefreshCtl */
259 #define ibl_EMIF4_ENABLE_sdRamRefreshCtl (1 << 2)
261 /** @def ibl_EMIF4_ENABLE_sdRamTiming1 */
262 #define ibl_EMIF4_ENABLE_sdRamTiming1 (1 << 3)
264 /** @def ibl_EMIF4_ENABLE_sdRamTiming2 */
265 #define ibl_EMIF4_ENABLE_sdRamTiming2 (1 << 4)
267 /** @def ibl_EMIF4_ENABLE_sdRamTiming3 */
268 #define ibl_EMIF4_ENABLE_sdRamTiming3 (1 << 5)
270 /** @def ibl_EMIF4_ENABLE_lpDdrNvmTiming */
271 #define ibl_EMIF4_ENABLE_lpDdrNvmTiming (1 << 6)
273 /** @def ibl_EMIF4_ENABLE_powerManageCtl */
274 #define ibl_EMIF4_ENABLE_powerManageCtl (1 << 7)
276 /** @def ibl_EMIF4_ENABLE_iODFTTestLogic */
277 #define ibl_EMIF4_ENABLE_iODFTTestLogic (1 << 8)
279 /** @def ibl_EMIF4_ENABLE_performCountCfg */
280 #define ibl_EMIF4_ENABLE_performCountCfg (1 << 9)
282 /** @def ibl_EMIF4_ENABLE_performCountMstRegSel */
283 #define ibl_EMIF4_ENABLE_performCountMstRegSel (1 << 10)
285 /** @def ibl_EMIF4_ENABLE_readIdleCtl */
286 #define ibl_EMIF4_ENABLE_readIdleCtl (1 << 11)
288 /** @def ibl_EMIF4_ENABLE_sysVbusmIntEnSet */
289 #define ibl_EMIF4_ENABLE_sysVbusmIntEnSet (1 << 12)
291 /** @def ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg */
292 #define ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg (1 << 13)
294 /** @def ibl_EMIF4_ENABLE_tempAlterCfg */
295 #define ibl_EMIF4_ENABLE_tempAlterCfg (1 << 14)
297 /** @def ibl_EMIF4_ENABLE_ddrPhyCtl1 */
298 #define ibl_EMIF4_ENABLE_ddrPhyCtl1 (1 << 15)
300 /** @def ibl_EMIF4_ENABLE_ddrPhyCtl2 */
301 #define ibl_EMIF4_ENABLE_ddrPhyCtl2 (1 << 16)
303 /** @def ibl_EMIF4_ENABLE_priClassSvceMap */
304 #define ibl_EMIF4_ENABLE_priClassSvceMap (1 << 17)
306 /** @def ibl_EMIF4_ENABLE_mstId2ClsSvce1Map */
307 #define ibl_EMIF4_ENABLE_mstId2ClsSvce1Map (1 << 18)
309 /** @def ibl_EMIF4_ENABLE_mstId2ClsSvce2Map */
310 #define ibl_EMIF4_ENABLE_mstId2ClsSvce2Map (1 << 11)
312 /** @def ibl_EMIF4_ENABLE_eccCtl */
313 #define ibl_EMIF4_ENABLE_eccCtl (1 << 19)
315 /** @def ibl_EMIF4_ENABLE_eccRange1 */
316 #define ibl_EMIF4_ENABLE_eccRange1 (1 << 20)
318 /** @def ibl_EMIF4_ENABLE_eccRange2 */
319 #define ibl_EMIF4_ENABLE_eccRange2 (1 << 21)
321 /** @def ibl_EMIF4_ENABLE_rdWrtExcThresh */
322 #define ibl_EMIF4_ENABLE_rdWrtExcThresh (1 << 22)
324 /** @def ibl_BOOT_EMIF4_ENABLE_ALL */
325 #define ibl_BOOT_EMIF4_ENABLE_ALL 0x007fffff
327 /* @} */
330 /**
331 * @defgroup iblEmifType Defines the EMIF4 type on a device
332 *
333 * @ingroup iblEmifType
334 * @{
335 */
336 /** @def ibl_EMIF_TYPE_31 */
337 #define ibl_EMIF_TYPE_31 31
339 /** @def ibl_EMIF_TYPE_40 */
340 #define ibl_EMIF_TYPE_40 40
342 /* @} */
344 /**
345 * @brief
346 * This structure is used to configure the DDR interface
347 *
348 * @details
349 * The DDR configuration parameters are setup
350 *
351 */
352 typedef struct idblDdr_s
353 {
354 bool configDdr; /**< Set to non-zero to enable EMIF configuration */
356 union {
358 iblEmif3p1_t emif3p1; /**< Configuration of devices with emif controller version 3.1 */
359 iblEmif4p0_t emif4p0; /**< Configuration of devices with emif controller version 4.0 */
360 } uEmif;
362 } iblDdr_t;
364 /**
365 * @brief
366 * This structure is used to identify binary blob load parameters.
367 *
368 * @details
369 * Since binary blob is formatless the start address, size and branch to address
370 * can be specified. In the case of network boot, boot will terminate when no
371 * more data is received (or timed out), even if the size is not reached.
372 */
373 typedef struct iblBinBlob_s
374 {
375 uint32 startAddress; /**< Where the loaded data is placed */
376 uint32 sizeBytes; /**< How much data to load */
377 uint32 branchAddress; /**< Where to branch to when the load is complete */
379 } iblBinBlob_t;
381 /**
382 * @brief
383 * This structure is used to control the operation of the ibl ethernet boot.
384 *
385 * @details
386 * The ethernet port and bootp request are controlled through this structure.
387 */
388 typedef struct iblEth_s
389 {
390 bool doBootp; /**< If true a bootp request is generated. If false the @ref iblEthBootInfo_t
391 table must be populated before the ibl begins execution */
392 bool useBootpServerIp; /**< If TRUE then the server IP received from the bootp server
393 is used, if FALSE the one in the ethInfo field is used */
394 bool useBootpFileName; /**< If TRUE then the file name received from the bootp server
395 is used, if FALSE the one in the ethInfo field is used */
396 int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
398 iblBinBlob_t blob; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
400 iblEthBootInfo_t ethInfo; /**< Low level ethernet information */
402 } iblEth_t;
405 /**
406 * @brief
407 * This structure is used to control the operation of the ibl sgmii ports
408 *
409 * @details
410 * The physical register configuration is provided
411 */
412 typedef struct iblSgmii_s
413 {
414 bool configure; /**< Set to false to disable configuration */
415 uint32 adviseAbility; /**< The advise ability register */
416 uint32 control; /**< The control register */
417 uint32 txConfig; /**< Serdes Tx config */
418 uint32 rxConfig; /**< Serdes Rx config */
419 uint32 auxConfig; /**< Serdes Aux config */
421 } iblSgmii_t;
424 /**
425 * @def ibl_N_ETH_PORTS
426 */
427 #define ibl_N_ETH_PORTS 2 /**< The number of ethernet port configurations available */
429 /**
430 * @def ibl_N_MDIO_CFGS
431 */
432 #define ibl_N_MDIO_CFGS 16 /**< The maximum number of mdio configurations */
435 /**
436 * @brief
437 * This structure is used to configure phys through the mdio interface
438 *
439 * @details
440 * Defines optional configuration through MDIO.
441 *
442 * The mdio transaction values are mapped as follows:
443 *
444 * /-------------------------------------------------------------\
445 * | 31 | 30 | 29 26 | 25 21 | 20 16 | 15 0|
446 * | rsvd | write | rsvd | register | phy addr | data |
447 * \-------------------------------------------------------------/
448 */
449 typedef struct iblMdio_s
450 {
451 int16 nMdioOps; /**< The number of mdio writes to perform */
452 uint16 mdioClkDiv; /**< The divide down of the mac clock which drives the mdio */
454 uint32 interDelay; /**< The number of cpu cycles to wait between mdio writes */
456 uint32 mdio[ibl_N_MDIO_CFGS]; /* The MDIO transactions */
458 } iblMdio_t;
460 /**
461 * @def ibl_N_ECC_BYTES
462 */
463 #define ibl_N_ECC_BYTES 10 /**< The number of ECC bytes to be computed for each page */
465 /**
466 * @def ibl_N_BAD_BLOCK_MARKER
467 */
468 #define ibl_N_BAD_BLOCK_PAGE 2 /**< The number of pages in each block that has the bad block marker */
470 /**
471 * @brief
472 * This structure defines the physical parameters of the NAND device
473 */
474 typedef struct nandDevInfo_s
475 {
476 uint32 busWidthBits; /**< 8 or 16 bit bus width */
477 uint32 pageSizeBytes; /**< The size of each page */
478 uint32 pageEccBytes; /**< Number of ecc bytes in each page */
479 uint32 pagesPerBlock; /**< The number of pages in each block */
480 uint32 totalBlocks; /**< The total number of blocks in a device */
482 uint32 addressBytes; /**< Number of bytes in the address */
483 bool lsbFirst; /**< Set to true if the LSB is output first, otherwise msb is first */
484 uint32 blockOffset; /**< Address bits which specify the block number */
485 uint32 pageOffset; /**< Address bits which specify the page number */
486 uint32 columnOffset; /**< Address bits which specify the column number */
488 uint8 eccBytesIdx[ibl_N_ECC_BYTES];
489 /**< Index of each ECC byte in each page data */
490 uint8 badBlkMarkIdx[ibl_N_BAD_BLOCK_PAGE];
491 /**< Index of bad block marker in each page data */
493 uint8 resetCommand; /**< The command to reset the flash */
494 uint8 readCommandPre; /**< The read command sent before the address */
495 uint8 readCommandPost; /**< The read command sent after the address */
496 bool postCommand; /**< If TRUE the post command is sent */
498 } nandDevInfo_t;
501 /**
502 * @def ibl_N_ENDIANS
503 */
504 #define ibl_N_ENDIANS 2 /**< The number of endians supported */
506 #define ibl_ENDIAN_BIG 0 /**< Big endian */
507 #define ibl_ENDIAN_LITTLE 1 /**< Little endian */
509 /**
510 * @def ibl_N_IMAGES
511 */
512 #define ibl_N_IMAGES 2 /**< The number of boot images supported on the same device */
514 /**
515 * @brief
516 * This structure is used to control the operation of the NAND boot
517 *
518 */
519 typedef struct iblNand_s
520 {
522 int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
523 uint32 bootAddress[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< The start address of each image for booting */
524 int32 interface; /**< The nand interface @ref iblPmemf */
525 iblBinBlob_t blob[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
528 nandDevInfo_t nandInfo; /** Low level device info */
530 } iblNand_t;
532 /**
533 * @brief
534 * Nor boot configuration.
535 */
536 typedef struct iblNor_s
537 {
538 int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
539 uint32 bootAddress[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< The start address for booting */
540 int32 interface; /**< The nor interface. @ref iblPmemIf */
541 iblBinBlob_t blob[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
543 } iblNor_t;
545 extern uint32 iblEndianIdx;
546 extern uint32 iblImageIdx;
548 /**
549 * @defgroup iblPmemIf defines the interfaces used for NOR memory. Not all values are
550 * valid for all devices
551 *
552 * @ingroup iblPmemIf
553 * @{
554 */
556 /** @def ibl_PMEM_IF_GPIO - GPIO interface */
557 #define ibl_PMEM_IF_GPIO 0
559 /** @def ibl_PMEM_IF_CHIPSEL_2 */
560 #define ibl_PMEM_IF_CHIPSEL_2 2 /* EMIF interface using chip select 2, no wait enabled */
562 /** @def ibl_PMEM_IF_CHIPSEL_3 */
563 #define ibl_PMEM_IF_CHIPSEL_3 3 /* EMIF interface using chip select 3, no wait enabled */
565 /** @def ibl_PMEM_IF_CHIPSEL_4 */
566 #define ibl_PMEM_IF_CHIPSEL_4 4 /* EMIF interface using chip select 4 */
568 /** @def ibl_PMEM_IF_CHIPSEL_5 */
569 #define ibl_PMEM_IF_CHIPSEL_5 5 /* EMIF interface using chip select 5 */
571 /** @def ibl_PMEM_IF_SPI */
572 #define ibl_PMEM_IF_SPI 100 /* Interface through SPI */
574 /* @} */
577 /**
578 * @brief
579 * EMIF (nand/nor) configuration
580 */
581 typedef struct iblEmif_s {
583 int16 csSpace; /**< Chip select space, @ref iblPmemIf */
584 int16 busWidth; /**< Bus width, bits */
585 bool waitEnable; /**< Valid only for NOR devices */
587 } iblEmif_t;
589 /**
590 * @brief
591 * The maximum number of chip select spaces for emif boot (not ddr) configuration
592 */
593 #define ibl_MAX_EMIF_PMEM 2
596 /**
597 * @brief
598 * SPI configuration used for either NOR or NAND
599 */
600 typedef struct iblSpi_s
601 {
602 int16 addrWidth; /**< 16 or 24 are the only valid values */
603 int16 nPins; /**< 4 or 5 are the only valid values */
604 int16 mode; /**< Clock / data polarities (valid values 0-3) */
605 int16 csel; /**< Chip select value (5 pin). Only 0b10 and 0b01 are valid */
606 uint16 c2tdelay; /**< Setup time between chip select and the transaction */
607 uint16 busFreqMHz; /**< Bus speed */
609 } iblSpi_t;
613 /**
614 * @brief
615 * This structure is used to control the programming of the device PLL
616 *
617 * @details
618 * The system PLLs are optionally configured
619 */
620 typedef struct iblPll_s {
622 bool doEnable; /**< If true the PLL is configured */
624 Uint32 prediv; /**< The pll pre-divisor */
625 Uint32 mult; /**< The pll multiplier */
626 Uint32 postdiv; /**< The pll post divider */
628 Uint32 pllOutFreqMhz; /**< The resulting output frequency, required for timer setup */
630 } iblPll_t;
633 /**
634 * @defgroup iblPllNum
635 *
636 * @ingroup iblPllNum
637 * @{
638 *
639 * @def ibl_MAIN_PLL
640 */
641 #define ibl_MAIN_PLL 0 /**< The main cpu pll */
643 /**
644 * @def ibl_DDR_PLL
645 */
646 #define ibl_DDR_PLL 1 /**< The ddr pll */
648 /**
649 * @def ibl_NET_PLL
650 */
651 #define ibl_NET_PLL 2 /**< The network pll */
653 /**
654 * @def the number of PLL configuration entries in the table
655 */
656 #define ibl_N_PLL_CFGS (ibl_NET_PLL + 1)
658 /* @} */
661 /**
662 * @def iblBoot_t
663 * Configures an ibl boot attempt
664 *
665 * @details
666 * The ibl allows for the configuration for multiple boot attempts. This structure is
667 * used to configure the ibl boot attempt.
668 */
669 typedef struct iblBoot_s
670 {
672 int32 bootMode; /**< Identifies the boot mode @ref iblBootModes */
674 uint32 priority; /**< The boot priority. @ref iblPeriphPriority */
675 int32 port; /**< The port to use, or @ref ibl_PORT_FROM_RBL */
677 union {
679 iblEth_t ethBoot; /**< Ethernet boot configuration. @ref iblEth_t */
681 iblNand_t nandBoot; /**< NAND boot configuration @ref iblNand_t */
683 iblNor_t norBoot; /**< NOR boot configuration @ref iblNor_t */
685 } u;
687 } iblBoot_t;
690 /**
691 * @def ibl_MAGIC_VALUE
692 */
693 #define ibl_MAGIC_VALUE 0xCEC11EBC /**< Indicates that the configuration table is valid */
695 /**
696 * @def ibl_EVM_TYPE
697 */
698 #define ibl_EVM_C6455L 0x10 /**< C6455 Low Cost EVM */
699 #define ibl_EVM_C6457L 0x20 /**< C6457 Low Cost EVM */
700 #define ibl_EVM_C6472L 0x30 /**< C6472 Low Cost EVM */
701 #define ibl_EVM_C6474L 0x40 /**< C6474 Low Cost EVM */
702 #define ibl_EVM_C6474M 0x41 /**< C6474 Mez EVM */
703 #define ibl_EVM_C6670L 0x50 /**< C6670 Low Cost EVM */
704 #define ibl_EVM_C6678L 0x60 /**< C6678 Low Cost EVM */
705 #define ibl_EVM_C6657L 0x70 /**< C6657 Low Cost EVM */
706 #define ibl_EVM_TCI6634K2K 0x80 /**< TCI6634K2K Low Cost EVM */
708 /**
709 * @brief
710 * The main configuration/control structure for the ibl
711 *
712 * @details
713 * The operation of the ibl is configured/controlled based on the values in this structure.
714 * This structure resides at a fixed location in the memory map. It can be changed during
715 * the boot operation itself by loading new values into it, but these changes must occur
716 * as part of the boot process itself (not through an asynchronous write through a master
717 * peripheral).
718 *
719 * Each boot mode is assigned a priority, with lower values indicating a higher
720 * priority. The lowest valid priority is @ref ibl_LOWEST_BOOT_PRIORITY, and the value
721 * @ref ibl_DEVICE_NOBOOT indicates no boot will be attempted on that peripheral.
722 */
723 typedef struct ibl_s
724 {
725 uint32 iblMagic; /**< @ref ibl_MAGIC_VALUE */
727 iblPll_t pllConfig[ibl_N_PLL_CFGS]; /**< PLL Configuration. @ref iblPll_t */
729 iblDdr_t ddrConfig; /**< DDR configuration @ref iblDdr_t */
731 iblSgmii_t sgmiiConfig[ibl_N_ETH_PORTS]; /**< SGMII boot configuration. @ref iblSgmii_t */
733 iblMdio_t mdioConfig; /**< MDIO configuration. @ref iblMdio_t */
735 iblSpi_t spiConfig; /**< SPI configuration @ref iblSpi_s */
737 iblEmif_t emifConfig[ibl_MAX_EMIF_PMEM]; /**< EMIF (nand/nor, not ddr) configuration. @ref iblEmif_t */
739 iblBoot_t bootModes[ibl_N_BOOT_MODES]; /**< Boot configuration */
741 uint16 iblEvmType; /**< @ref ibl_EVM_TYPE */
743 uint16 chkSum; /**< Ones complement checksum over the whole config structure */
745 } ibl_t;
748 extern ibl_t ibl;
751 /**
752 * @defgroup iblActiveDevice
753 *
754 * @ingroup iblActiveDevice
755 * @{
756 * @def ibl_ACTIVE_DEVICE_ETH
757 */
758 #define ibl_ACTIVE_DEVICE_ETH 100 /**< Data received through an ethernet interface */
760 /**
761 * @def ibl_ACTIVE_DEVICE_EMIF
762 */
763 #define ibl_ACTIVE_DEVICE_EMIF 101 /**< Data read through an EMIF interface */
765 /**
766 * @def ibl_ACTIVE_DEVICE_I2C
767 */
768 #define ibl_ACTIVE_DEVICE_I2C 102 /**< Data read through an I2C interface */
770 /**
771 * @def ibl_ACTIVE_DEVICE_SPI
772 */
773 #define ibl_ACTIVE_DEVICE_SPI 103 /**< Data read through an SPI interface */
775 /* @} */
778 /**
779 * @defgroup iblFailCode
780 *
781 * @ingroup iblFailCode
782 * @{
783 * @def ibl_FAIL_CODE_INVALID_I2C_ADDRESS
784 */
785 #define ibl_FAIL_CODE_INVALID_I2C_ADDRESS 700 /**< Invalid i2c eeprom address encountered */
787 /**
788 * @def ibl_FAIL_CODE_BTBL_FAIL
789 */
790 #define ibl_FAIL_CODE_BTBL_FAIL 701 /**< Boot table processing function error */
792 /**
793 * @def ibl_FAIL_CODE_PA
794 */
795 #define ibl_FAIL_CODE_PA 702 /**< Packet Accelerator setup failed */
798 /**
799 * @def ibl_FAIL_CODE_SPI_PARAMS
800 */
801 #define ibl_FAIL_CODE_SPI_PARAMS 703 /**< Invalid SPI configuration found */
803 /**
804 * @def ibl_FAIL_CODE_INVALID_INIT_DEVICE
805 */
806 #define ibl_FAIL_CODE_INVALID_INIT_DEVICE 704 /**< Second stage boot device specified is invalid */
808 /**
809 * @def ibl_FAIL_CODE_INVALID_SPI_ADDRESS
810 */
811 #define ibl_FAIL_CODE_INVALID_SPI_ADDRESS 705 /**< Invalid data address specified on SPI */
813 /**
814 * @def ibl_FAIL_CODE_PERIPH_POWER_UP
815 */
816 #define ibl_FAIL_CODE_PERIPH_POWER_UP 706 /**< Boot peripheral failed to power up */
818 /**
819 * @def ibl_FAIL_CODE_INVALID_NAND_PERIPH
820 */
821 #define ibl_FAIL_CODE_INVALID_NAND_PERIPH 707 /**< Invalid nand boot peripheral specified */
823 /**
824 * @def ibl_FAIL_CODE_NO_EMIF_CFG
825 */
826 #define ibl_FAIL_CODE_NO_EMIF_CFG 708 /**< No emif configuration found to match specified cs space */
828 /**
829 * @def ibl_FAIL_CODE_EMIF_CFG_FAIL
830 */
831 #define ibl_FAIL_CODE_EMIF_CFG_FAIL 709 /**< Hardware setup of emif failed */
833 /* @} */
836 /**
837 * @brief
838 * Provide status on the boot operation
839 *
840 * @details
841 * Run time status of the IBL is provided to aid in debugging
842 *
843 */
844 typedef struct iblStatus_s
845 {
846 uint32 iblMagic; /**< The @ref ibl_MAGIC_VALUE is placed here to indicate the boot has begun */
848 uint32 iblVersion; /**< The version number. MSB = major, SMSB = minor, SLSB = minor minor LSB= tiny */
850 uint32 iblFail; /**< If non-zero the IBL has encountered a fatal error */
852 uint32 i2cRetries; /**< Count of I2C read retries */
853 uint32 i2cDataRetries; /**< Number of retries while reading block data from the i2c */
855 uint32 spiRetries; /**< Count of SPI read retries */
856 uint32 spiDataRetries; /**< Number of retries while reading block data from the spi */
858 uint32 magicRetries; /**< Count of I2C/SPI re-reads because the magic number was incorrect */
859 uint32 mapSizeFail; /**< Number of times an invalid map table size was read from the i2c/spi */
860 uint32 mapRetries; /**< Number of times the checksum failed on the read of the i2c/spi map */
862 int32 heartBeat; /**< An increasing value as long as the boot code is running */
864 int32 activeBoot; /**< Describes the active boot mode @ref iblBootModes */
865 int32 activeDevice; /**< Describes the active boot peripheral device @ref iblActiveDevice */
866 int32 activeFileFormat; /**< Describes the format being decoded */
868 uint32 autoDetectFailCnt; /**< Counts the number of times an auto detect of the data format failed */
869 uint32 nameDetectFailCnt; /**< Counts the number of times an name detect of the data format failed */
871 uint32 invalidDataFormatSpec; /**< Counts the number of times the main boot found an invalid boot format request */
873 uint32 exitAddress; /**< If non-zero the IBL exited and branched to this address */
875 iblEthBootInfo_t ethParams; /**< Last ethernet boot attemp parameters */
877 } iblStatus_t;
879 extern iblStatus_t iblStatus;
882 /**
883 * @brief
884 * The ibl boot map structure
885 *
886 * @details
887 * The ibl boot device contains a structure which identifies the location of the big and little
888 * endian ibl images on the external device.
889 */
890 typedef struct iblBootMap_s
891 {
892 uint16 length; /**< Size of the structure in bytes */
893 uint16 chkSum; /**< Value which makes the ones complement checksum over the block equal to 0 or -0 */
895 uint32 addrLe; /**< Base address of the boot tables for the little endian image */
896 uint32 configLe; /**< Base address of the ibl structure for use with the little endian image */
898 uint32 addrBe; /**< Base address of the boot tables for the big endian image */
899 uint32 configBe; /**< Base address of the ibl structure for use with the big endian image */
901 } iblBootMap_t;
909 #endif /* IBL_H */