1 /*
2 *
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
38 /********************************************************************************************************
39 * FILE PURPOSE: IBL configuration and control definitions
40 ********************************************************************************************************
41 * FILE NAME: ibl.h
42 *
43 * DESCRIPTION: Defines the data structure used to handle initial configuration and control
44 * of the ibl. This data structure resides at a fixed location in the device memory
45 * map. It is initially populated either during the rom boot. The table can be
46 * over-written during the ibl process to redirect the boot. For example the ibl
47 * can initially load from an i2c which repopulates this table with parameters
48 * for an ethernet boot.
49 *
50 * @file ibl.h
51 *
52 * @brief
53 * This file defines the configuration and control of the IBL
54 *
55 *
56 ********************************************************************************************************/
57 #ifndef IBL_H
58 #define IBL_H
60 #include "types.h"
63 #define ibl_MAKE_VERSION(a,b,c,d) ((a << 24) | (b << 16) | (c << 8) | (d << 0))
66 /**
67 * @brief
68 * The version number, 1.0.0.12
69 */
70 #define ibl_VERSION ibl_MAKE_VERSION(1,0,0,12)
73 /**
74 * @defgroup iblBootModes Defines the boot modes supported by the IBL
75 *
76 * @ingroup iblBootModes
77 * @{
78 *
79 * @def ibl_BOOT_MODE_TFTP */
80 #define ibl_BOOT_MODE_TFTP 10 /* Boot through a tftp interface */
82 /* @def ibl_BOOT_MODE_NAND */
83 #define ibl_BOOT_MODE_NAND 11 /* Boot through a nand interface */
85 /* @def ibl_BOOT_MODE_NOR */
86 #define ibl_BOOT_MODE_NOR 12 /* Boot through a nor (or flash) interface */
88 /* @def ibl_BOOT_MODE_NONE */
89 #define ibl_BOOT_MODE_NONE 13 /* Boot mode selection is inactive */
91 /* @} */
93 /**
94 * @brief
95 * Define the number of different boot modes which can be configured for
96 * a single execution of the IBL.
97 */
98 #define ibl_N_BOOT_MODES 3
100 /* Information used to make generate a bootp request */
101 /**
102 * @brief
103 * Defines parameters used for making a bootp request
104 *
105 * @details
106 * The bootp request parameters are created from these fields
107 */
108 typedef struct iblBootp_s
109 {
110 uint8 hwAddress[6]; /**< The hardware (mac) address of this device. If set to 0
111 the ibl will values from e-fuse */
113 uint8 ipDest[4]; /**< The IP address of this device. This is typically set
114 to IP broadcast */
116 } iblBootp_t;
119 /**
120 * @brief
121 * This structure contains information used for tftp boot.
122 *
123 * @details These fields are typically filled in by the bootp packet, but
124 * can be provided if bootp will not be used.
125 */
126 typedef struct iblEthBootInfo_s
127 {
128 uint8 ipAddr[4]; /**< The IP address of this device */
129 uint8 serverIp[4]; /**< The IP address of the tftp server */
130 uint8 gatewayIp[4]; /**< The IP address of the gateway */
131 uint8 netmask[4]; /**< The IP netmask */
132 uint8 hwAddress[6]; /**< The hardware (mac) address of this device */
133 char8 fileName[64]; /**< The file name to load */
135 } iblEthBootInfo_t;
138 /**
139 * @def ibl_ETH_PORT_FROM_RBL
140 */
141 #define ibl_ETH_PORT_FROM_RBL -1 /**< The ethernet port used is the same one used
142 during the ROM boot load process. */
144 /**
145 * @def ibl_PORT_SWITCH_ALL
146 */
147 #define ibl_PORT_SWITCH_ALL -2 /**< The ethernet subsystem is connected to a switch, and
148 all ports on the subsystem should be configured */
151 /**
152 * @defgroup iblBootFormats
153 *
154 * @ingroup iblBootFormats
155 * @{
156 */
157 #define ibl_BOOT_FORMAT_AUTO 0 /**< Auto determine the boot format from the data */
158 #define ibl_BOOT_FORMAT_NAME 1 /**< Determines the boot format based on file name (bootp/tftp only) */
159 #define ibl_BOOT_FORMAT_BIS 2 /**< Boot TI AIS format */
160 #define ibl_BOOT_FORMAT_COFF 3 /**< Boot a COFF file */
161 #define ibl_BOOT_FORMAT_ELF 4 /**< Boot an ELF file */
162 #define ibl_BOOT_FORMAT_BBLOB 5 /**< Boot a binary blob */
163 #define ibl_BOOT_FORMAT_BTBL 6 /**< Boot a TI boot table file */
165 /* @} */
167 /**
168 * @defgroup iblPeriphPriority Defines the boot sequence
169 *
170 * @ingroup iblPeriphPriority
171 * @{
172 * @def ibl_LOWEST_PRIORITY
173 */
174 #define ibl_LOWEST_PRIORITY 10 /**< The lowest priority assignable to a peripheral for boot */
176 /**
177 * @def ibl_HIGHEST_PRIORITY
178 */
179 #define ibl_HIGHEST_PRIORITY 1 /**< The highest priority assignable to a peripheral for boot */
181 /**
182 * @def ibl_DEVICE_NOBOOT
183 */
184 #define ibl_DEVICE_NOBOOT 20 /**< Indicates that the device is not to be used for boot */
186 /* @} */
189 /**
190 * @brief
191 * Emif controller 3.1 configuration
192 *
193 * @details
194 * The paramters are directly placed into the emif controller
195 */
196 typedef struct iblEmif3p1_s
197 {
198 uint32 sdcfg; /**< SD configuration register */
199 uint32 sdrfc; /**< Refresh timing register */
200 uint32 sdtim1; /**< DDR timing register 1 */
201 uint32 sdtim2; /**< DDR timing register 2 */
202 uint32 dmcctl; /**< CAS match timing */
204 } iblEmif3p1_t;
207 /**
208 * @brief
209 * Emif controller 4.0 configuration
210 *
211 * @details
212 * The parameters are placed directly into the emif controller
213 */
214 typedef struct iblEmif4p0_s
215 {
216 uint32 registerMask; /**< Identifies which registers will be configured */
217 uint32 sdRamConfig; /**< SDRAM Config Register */
218 uint32 sdRamConfig2; /**< SDRAM Config2 Register */
219 uint32 sdRamRefreshCtl; /**< SDRAM Refresh Control Register */
220 uint32 sdRamTiming1; /**< SDRAM Timing 1 Register */
221 uint32 sdRamTiming2; /**< SDRAM Timing 2 Register */
222 uint32 sdRamTiming3; /**< SDRAM Timing 3 Register */
223 uint32 lpDdrNvmTiming; /**< LPDDR2-NVM Timing Register */
224 uint32 powerManageCtl; /**< Power Management Control Register */
225 uint32 iODFTTestLogic; /**< IODFT Test Logic Global Control Register */
226 uint32 performCountCfg; /**< Performance Counter Config Register */
227 uint32 performCountMstRegSel; /**< Performance Counter Master Region Select Register */
228 uint32 readIdleCtl; /**< Read Idle Control Register */
229 uint32 sysVbusmIntEnSet; /**< VBUSM Interrupt Enable Set Register */
230 uint32 sdRamOutImpdedCalCfg; /**< SDRAM Output Impedance Calibratin Config Register */
231 uint32 tempAlterCfg; /**< Temperature Alert Config Register */
232 uint32 ddrPhyCtl1; /**< DDR PHY Control 1 Register */
233 uint32 ddrPhyCtl2; /**< DDR PHY Control 2 Register */
234 uint32 priClassSvceMap; /**< DDR Priority to Class of Service Mapping Register */
235 uint32 mstId2ClsSvce1Map; /**< Master ID to Class of Service 1 Mapping Register */
236 uint32 mstId2ClsSvce2Map; /**< Master ID to Class of Service 2 Mapping Register */
237 uint32 eccCtl; /**< ECC Control Register */
238 uint32 eccRange1; /**< ECC Address Range 1 Register */
239 uint32 eccRange2; /**< ECC Address Range 2 Register */
240 uint32 rdWrtExcThresh; /**< Read Write Execution Threshold Register */
242 } iblEmif4p0_t;
245 /**
246 * @defgroup iblEmif4Select Defines the EMIF4 registers configured by IBL
247 *
248 * @ingroup iblEmif4Select
249 * @{
250 * @def ibl_EMIF4_ENABLE_sdRamConfig
251 */
252 #define ibl_EMIF4_ENABLE_sdRamConfig (1 << 0)
254 /** @def ibl_EMIF4_ENABLE_sdRamConfig2 */
255 #define ibl_EMIF4_ENABLE_sdRamConfig2 (1 << 1)
257 /** @def ibl_EMIF4_ENABLE_sdRamRefreshCtl */
258 #define ibl_EMIF4_ENABLE_sdRamRefreshCtl (1 << 2)
260 /** @def ibl_EMIF4_ENABLE_sdRamTiming1 */
261 #define ibl_EMIF4_ENABLE_sdRamTiming1 (1 << 3)
263 /** @def ibl_EMIF4_ENABLE_sdRamTiming2 */
264 #define ibl_EMIF4_ENABLE_sdRamTiming2 (1 << 4)
266 /** @def ibl_EMIF4_ENABLE_sdRamTiming3 */
267 #define ibl_EMIF4_ENABLE_sdRamTiming3 (1 << 5)
269 /** @def ibl_EMIF4_ENABLE_lpDdrNvmTiming */
270 #define ibl_EMIF4_ENABLE_lpDdrNvmTiming (1 << 6)
272 /** @def ibl_EMIF4_ENABLE_powerManageCtl */
273 #define ibl_EMIF4_ENABLE_powerManageCtl (1 << 7)
275 /** @def ibl_EMIF4_ENABLE_iODFTTestLogic */
276 #define ibl_EMIF4_ENABLE_iODFTTestLogic (1 << 8)
278 /** @def ibl_EMIF4_ENABLE_performCountCfg */
279 #define ibl_EMIF4_ENABLE_performCountCfg (1 << 9)
281 /** @def ibl_EMIF4_ENABLE_performCountMstRegSel */
282 #define ibl_EMIF4_ENABLE_performCountMstRegSel (1 << 10)
284 /** @def ibl_EMIF4_ENABLE_readIdleCtl */
285 #define ibl_EMIF4_ENABLE_readIdleCtl (1 << 11)
287 /** @def ibl_EMIF4_ENABLE_sysVbusmIntEnSet */
288 #define ibl_EMIF4_ENABLE_sysVbusmIntEnSet (1 << 12)
290 /** @def ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg */
291 #define ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg (1 << 13)
293 /** @def ibl_EMIF4_ENABLE_tempAlterCfg */
294 #define ibl_EMIF4_ENABLE_tempAlterCfg (1 << 14)
296 /** @def ibl_EMIF4_ENABLE_ddrPhyCtl1 */
297 #define ibl_EMIF4_ENABLE_ddrPhyCtl1 (1 << 15)
299 /** @def ibl_EMIF4_ENABLE_ddrPhyCtl2 */
300 #define ibl_EMIF4_ENABLE_ddrPhyCtl2 (1 << 16)
302 /** @def ibl_EMIF4_ENABLE_priClassSvceMap */
303 #define ibl_EMIF4_ENABLE_priClassSvceMap (1 << 17)
305 /** @def ibl_EMIF4_ENABLE_mstId2ClsSvce1Map */
306 #define ibl_EMIF4_ENABLE_mstId2ClsSvce1Map (1 << 18)
308 /** @def ibl_EMIF4_ENABLE_mstId2ClsSvce2Map */
309 #define ibl_EMIF4_ENABLE_mstId2ClsSvce2Map (1 << 11)
311 /** @def ibl_EMIF4_ENABLE_eccCtl */
312 #define ibl_EMIF4_ENABLE_eccCtl (1 << 19)
314 /** @def ibl_EMIF4_ENABLE_eccRange1 */
315 #define ibl_EMIF4_ENABLE_eccRange1 (1 << 20)
317 /** @def ibl_EMIF4_ENABLE_eccRange2 */
318 #define ibl_EMIF4_ENABLE_eccRange2 (1 << 21)
320 /** @def ibl_EMIF4_ENABLE_rdWrtExcThresh */
321 #define ibl_EMIF4_ENABLE_rdWrtExcThresh (1 << 22)
323 /** @def ibl_BOOT_EMIF4_ENABLE_ALL */
324 #define ibl_BOOT_EMIF4_ENABLE_ALL 0x007fffff
326 /* @} */
329 /**
330 * @defgroup iblEmifType Defines the EMIF4 type on a device
331 *
332 * @ingroup iblEmifType
333 * @{
334 */
335 /** @def ibl_EMIF_TYPE_31 */
336 #define ibl_EMIF_TYPE_31 31
338 /** @def ibl_EMIF_TYPE_40 */
339 #define ibl_EMIF_TYPE_40 40
341 /* @} */
343 /**
344 * @brief
345 * This structure is used to configure the DDR interface
346 *
347 * @details
348 * The DDR configuration parameters are setup
349 *
350 */
351 typedef struct idblDdr_s
352 {
353 bool configDdr; /**< Set to non-zero to enable EMIF configuration */
355 union {
357 iblEmif3p1_t emif3p1; /**< Configuration of devices with emif controller version 3.1 */
358 iblEmif4p0_t emif4p0; /**< Configuration of devices with emif controller version 4.0 */
359 } uEmif;
361 } iblDdr_t;
363 /**
364 * @brief
365 * This structure is used to identify binary blob load parameters.
366 *
367 * @details
368 * Since binary blob is formatless the start address, size and branch to address
369 * can be specified. In the case of network boot, boot will terminate when no
370 * more data is received (or timed out), even if the size is not reached.
371 */
372 typedef struct iblBinBlob_s
373 {
374 uint32 startAddress; /**< Where the loaded data is placed */
375 uint32 sizeBytes; /**< How much data to load */
376 uint32 branchAddress; /**< Where to branch to when the load is complete */
378 } iblBinBlob_t;
380 /**
381 * @brief
382 * This structure is used to control the operation of the ibl ethernet boot.
383 *
384 * @details
385 * The ethernet port and bootp request are controlled through this structure.
386 */
387 typedef struct iblEth_s
388 {
389 bool doBootp; /**< If true a bootp request is generated. If false the @ref iblEthBootInfo_t
390 table must be populated before the ibl begins execution */
391 bool useBootpServerIp; /**< If TRUE then the server IP received from the bootp server
392 is used, if FALSE the one in the ethInfo field is used */
393 bool useBootpFileName; /**< If TRUE then the file name received from the bootp server
394 is used, if FALSE the one in the ethInfo field is used */
395 int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
397 iblBinBlob_t blob; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
399 iblEthBootInfo_t ethInfo; /**< Low level ethernet information */
401 } iblEth_t;
404 /**
405 * @brief
406 * This structure is used to control the operation of the ibl sgmii ports
407 *
408 * @details
409 * The physical register configuration is provided
410 */
411 typedef struct iblSgmii_s
412 {
413 bool configure; /**< Set to false to disable configuration */
414 uint32 adviseAbility; /**< The advise ability register */
415 uint32 control; /**< The control register */
416 uint32 txConfig; /**< Serdes Tx config */
417 uint32 rxConfig; /**< Serdes Rx config */
418 uint32 auxConfig; /**< Serdes Aux config */
420 } iblSgmii_t;
423 /**
424 * @def ibl_N_ETH_PORTS
425 */
426 #define ibl_N_ETH_PORTS 2 /**< The number of ethernet port configurations available */
428 /**
429 * @def ibl_N_MDIO_CFGS
430 */
431 #define ibl_N_MDIO_CFGS 16 /**< The maximum number of mdio configurations */
434 /**
435 * @brief
436 * This structure is used to configure phys through the mdio interface
437 *
438 * @details
439 * Defines optional configuration through MDIO.
440 *
441 * The mdio transaction values are mapped as follows:
442 *
443 * /-------------------------------------------------------------\
444 * | 31 | 30 | 29 26 | 25 21 | 20 16 | 15 0|
445 * | rsvd | write | rsvd | register | phy addr | data |
446 * \-------------------------------------------------------------/
447 */
448 typedef struct iblMdio_s
449 {
450 int16 nMdioOps; /**< The number of mdio writes to perform */
451 uint16 mdioClkDiv; /**< The divide down of the mac clock which drives the mdio */
453 uint32 interDelay; /**< The number of cpu cycles to wait between mdio writes */
455 uint32 mdio[ibl_N_MDIO_CFGS]; /* The MDIO transactions */
457 } iblMdio_t;
459 /**
460 * @def ibl_N_ECC_BYTES
461 */
462 #define ibl_N_ECC_BYTES 10 /**< The number of ECC bytes to be computed for each page */
464 /**
465 * @def ibl_N_BAD_BLOCK_MARKER
466 */
467 #define ibl_N_BAD_BLOCK_PAGE 2 /**< The number of pages in each block that has the bad block marker */
469 /**
470 * @brief
471 * This structure defines the physical parameters of the NAND device
472 */
473 typedef struct nandDevInfo_s
474 {
475 uint32 busWidthBits; /**< 8 or 16 bit bus width */
476 uint32 pageSizeBytes; /**< The size of each page */
477 uint32 pageEccBytes; /**< Number of ecc bytes in each page */
478 uint32 pagesPerBlock; /**< The number of pages in each block */
479 uint32 totalBlocks; /**< The total number of blocks in a device */
481 uint32 addressBytes; /**< Number of bytes in the address */
482 bool lsbFirst; /**< Set to true if the LSB is output first, otherwise msb is first */
483 uint32 blockOffset; /**< Address bits which specify the block number */
484 uint32 pageOffset; /**< Address bits which specify the page number */
485 uint32 columnOffset; /**< Address bits which specify the column number */
487 uint8 eccBytesIdx[ibl_N_ECC_BYTES];
488 /**< Index of each ECC byte in each page data */
489 uint8 badBlkMarkIdx[ibl_N_BAD_BLOCK_PAGE];
490 /**< Index of bad block marker in each page data */
492 uint8 resetCommand; /**< The command to reset the flash */
493 uint8 readCommandPre; /**< The read command sent before the address */
494 uint8 readCommandPost; /**< The read command sent after the address */
495 bool postCommand; /**< If TRUE the post command is sent */
497 } nandDevInfo_t;
500 /**
501 * @def ibl_N_ENDIANS
502 */
503 #define ibl_N_ENDIANS 2 /**< The number of endians supported */
505 #define ibl_ENDIAN_BIG 0 /**< Big endian */
506 #define ibl_ENDIAN_LITTLE 1 /**< Little endian */
508 /**
509 * @def ibl_N_IMAGES
510 */
511 #define ibl_N_IMAGES 2 /**< The number of boot images supported on the same device */
513 /**
514 * @brief
515 * This structure is used to control the operation of the NAND boot
516 *
517 */
518 typedef struct iblNand_s
519 {
521 int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
522 uint32 bootAddress[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< The start address of each image for booting */
523 int32 interface; /**< The nand interface @ref iblPmemf */
524 iblBinBlob_t blob[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
527 nandDevInfo_t nandInfo; /** Low level device info */
529 } iblNand_t;
531 /**
532 * @brief
533 * Nor boot configuration.
534 */
535 typedef struct iblNor_s
536 {
537 int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
538 uint32 bootAddress[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< The start address for booting */
539 int32 interface; /**< The nor interface. @ref iblPmemIf */
540 iblBinBlob_t blob[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
542 } iblNor_t;
544 extern uint32 iblEndianIdx;
545 extern uint32 iblImageIdx;
547 /**
548 * @defgroup iblPmemIf defines the interfaces used for NOR memory. Not all values are
549 * valid for all devices
550 *
551 * @ingroup iblPmemIf
552 * @{
553 */
555 /** @def ibl_PMEM_IF_GPIO - GPIO interface */
556 #define ibl_PMEM_IF_GPIO 0
558 /** @def ibl_PMEM_IF_CHIPSEL_2 */
559 #define ibl_PMEM_IF_CHIPSEL_2 2 /* EMIF interface using chip select 2, no wait enabled */
561 /** @def ibl_PMEM_IF_CHIPSEL_3 */
562 #define ibl_PMEM_IF_CHIPSEL_3 3 /* EMIF interface using chip select 3, no wait enabled */
564 /** @def ibl_PMEM_IF_CHIPSEL_4 */
565 #define ibl_PMEM_IF_CHIPSEL_4 4 /* EMIF interface using chip select 4 */
567 /** @def ibl_PMEM_IF_CHIPSEL_5 */
568 #define ibl_PMEM_IF_CHIPSEL_5 5 /* EMIF interface using chip select 5 */
570 /** @def ibl_PMEM_IF_SPI */
571 #define ibl_PMEM_IF_SPI 100 /* Interface through SPI */
573 /* @} */
576 /**
577 * @brief
578 * EMIF (nand/nor) configuration
579 */
580 typedef struct iblEmif_s {
582 int16 csSpace; /**< Chip select space, @ref iblPmemIf */
583 int16 busWidth; /**< Bus width, bits */
584 bool waitEnable; /**< Valid only for NOR devices */
586 } iblEmif_t;
588 /**
589 * @brief
590 * The maximum number of chip select spaces for emif boot (not ddr) configuration
591 */
592 #define ibl_MAX_EMIF_PMEM 2
595 /**
596 * @brief
597 * SPI configuration used for either NOR or NAND
598 */
599 typedef struct iblSpi_s
600 {
601 int16 addrWidth; /**< 16 or 24 are the only valid values */
602 int16 nPins; /**< 4 or 5 are the only valid values */
603 int16 mode; /**< Clock / data polarities (valid values 0-3) */
604 int16 csel; /**< Chip select value (5 pin). Only 0b10 and 0b01 are valid */
605 uint16 c2tdelay; /**< Setup time between chip select and the transaction */
606 uint16 busFreqMHz; /**< Bus speed */
608 } iblSpi_t;
612 /**
613 * @brief
614 * This structure is used to control the programming of the device PLL
615 *
616 * @details
617 * The system PLLs are optionally configured
618 */
619 typedef struct iblPll_s {
621 bool doEnable; /**< If true the PLL is configured */
623 Uint32 prediv; /**< The pll pre-divisor */
624 Uint32 mult; /**< The pll multiplier */
625 Uint32 postdiv; /**< The pll post divider */
627 Uint32 pllOutFreqMhz; /**< The resulting output frequency, required for timer setup */
629 } iblPll_t;
632 /**
633 * @defgroup iblPllNum
634 *
635 * @ingroup iblPllNum
636 * @{
637 *
638 * @def ibl_MAIN_PLL
639 */
640 #define ibl_MAIN_PLL 0 /**< The main cpu pll */
642 /**
643 * @def ibl_DDR_PLL
644 */
645 #define ibl_DDR_PLL 1 /**< The ddr pll */
647 /**
648 * @def ibl_NET_PLL
649 */
650 #define ibl_NET_PLL 2 /**< The network pll */
652 /**
653 * @def the number of PLL configuration entries in the table
654 */
655 #define ibl_N_PLL_CFGS (ibl_NET_PLL + 1)
657 /* @} */
660 /**
661 * @def iblBoot_t
662 * Configures an ibl boot attempt
663 *
664 * @details
665 * The ibl allows for the configuration for multiple boot attempts. This structure is
666 * used to configure the ibl boot attempt.
667 */
668 typedef struct iblBoot_s
669 {
671 int32 bootMode; /**< Identifies the boot mode @ref iblBootModes */
673 uint32 priority; /**< The boot priority. @ref iblPeriphPriority */
674 int32 port; /**< The port to use, or @ref ibl_PORT_FROM_RBL */
676 union {
678 iblEth_t ethBoot; /**< Ethernet boot configuration. @ref iblEth_t */
680 iblNand_t nandBoot; /**< NAND boot configuration @ref iblNand_t */
682 iblNor_t norBoot; /**< NOR boot configuration @ref iblNor_t */
684 } u;
686 } iblBoot_t;
689 /**
690 * @def ibl_MAGIC_VALUE
691 */
692 #define ibl_MAGIC_VALUE 0xCEC11EBC /**< Indicates that the configuration table is valid */
694 /**
695 * @def ibl_EVM_TYPE
696 */
697 #define ibl_EVM_C6455L 0x10 /**< C6455 Low Cost EVM */
698 #define ibl_EVM_C6457L 0x20 /**< C6457 Low Cost EVM */
699 #define ibl_EVM_C6472L 0x30 /**< C6472 Low Cost EVM */
700 #define ibl_EVM_C6474L 0x40 /**< C6474 Low Cost EVM */
701 #define ibl_EVM_C6474M 0x41 /**< C6474 Mez EVM */
702 #define ibl_EVM_C6670L 0x50 /**< C6670 Low Cost EVM */
703 #define ibl_EVM_C6678L 0x60 /**< C6678 Low Cost EVM */
706 /**
707 * @brief
708 * The main configuration/control structure for the ibl
709 *
710 * @details
711 * The operation of the ibl is configured/controlled based on the values in this structure.
712 * This structure resides at a fixed location in the memory map. It can be changed during
713 * the boot operation itself by loading new values into it, but these changes must occur
714 * as part of the boot process itself (not through an asynchronous write through a master
715 * peripheral).
716 *
717 * Each boot mode is assigned a priority, with lower values indicating a higher
718 * priority. The lowest valid priority is @ref ibl_LOWEST_BOOT_PRIORITY, and the value
719 * @ref ibl_DEVICE_NOBOOT indicates no boot will be attempted on that peripheral.
720 */
721 typedef struct ibl_s
722 {
723 uint32 iblMagic; /**< @ref ibl_MAGIC_VALUE */
725 iblPll_t pllConfig[ibl_N_PLL_CFGS]; /**< PLL Configuration. @ref iblPll_t */
727 iblDdr_t ddrConfig; /**< DDR configuration @ref iblDdr_t */
729 iblSgmii_t sgmiiConfig[ibl_N_ETH_PORTS]; /**< SGMII boot configuration. @ref iblSgmii_t */
731 iblMdio_t mdioConfig; /**< MDIO configuration. @ref iblMdio_t */
733 iblSpi_t spiConfig; /**< SPI configuration @ref iblSpi_s */
735 iblEmif_t emifConfig[ibl_MAX_EMIF_PMEM]; /**< EMIF (nand/nor, not ddr) configuration. @ref iblEmif_t */
737 iblBoot_t bootModes[ibl_N_BOOT_MODES]; /**< Boot configuration */
739 uint16 iblEvmType; /**< @ref ibl_EVM_TYPE */
741 uint16 chkSum; /**< Ones complement checksum over the whole config structure */
743 } ibl_t;
746 extern ibl_t ibl;
749 /**
750 * @defgroup iblActiveDevice
751 *
752 * @ingroup iblActiveDevice
753 * @{
754 * @def ibl_ACTIVE_DEVICE_ETH
755 */
756 #define ibl_ACTIVE_DEVICE_ETH 100 /**< Data received through an ethernet interface */
758 /**
759 * @def ibl_ACTIVE_DEVICE_EMIF
760 */
761 #define ibl_ACTIVE_DEVICE_EMIF 101 /**< Data read through an EMIF interface */
763 /**
764 * @def ibl_ACTIVE_DEVICE_I2C
765 */
766 #define ibl_ACTIVE_DEVICE_I2C 102 /**< Data read through an I2C interface */
768 /**
769 * @def ibl_ACTIVE_DEVICE_SPI
770 */
771 #define ibl_ACTIVE_DEVICE_SPI 103 /**< Data read through an SPI interface */
773 /* @} */
776 /**
777 * @defgroup iblFailCode
778 *
779 * @ingroup iblFailCode
780 * @{
781 * @def ibl_FAIL_CODE_INVALID_I2C_ADDRESS
782 */
783 #define ibl_FAIL_CODE_INVALID_I2C_ADDRESS 700 /**< Invalid i2c eeprom address encountered */
785 /**
786 * @def ibl_FAIL_CODE_BTBL_FAIL
787 */
788 #define ibl_FAIL_CODE_BTBL_FAIL 701 /**< Boot table processing function error */
790 /**
791 * @def ibl_FAIL_CODE_PA
792 */
793 #define ibl_FAIL_CODE_PA 702 /**< Packet Accelerator setup failed */
796 /**
797 * @def ibl_FAIL_CODE_SPI_PARAMS
798 */
799 #define ibl_FAIL_CODE_SPI_PARAMS 703 /**< Invalid SPI configuration found */
801 /**
802 * @def ibl_FAIL_CODE_INVALID_INIT_DEVICE
803 */
804 #define ibl_FAIL_CODE_INVALID_INIT_DEVICE 704 /**< Second stage boot device specified is invalid */
806 /**
807 * @def ibl_FAIL_CODE_INVALID_SPI_ADDRESS
808 */
809 #define ibl_FAIL_CODE_INVALID_SPI_ADDRESS 705 /**< Invalid data address specified on SPI */
811 /**
812 * @def ibl_FAIL_CODE_PERIPH_POWER_UP
813 */
814 #define ibl_FAIL_CODE_PERIPH_POWER_UP 706 /**< Boot peripheral failed to power up */
816 /**
817 * @def ibl_FAIL_CODE_INVALID_NAND_PERIPH
818 */
819 #define ibl_FAIL_CODE_INVALID_NAND_PERIPH 707 /**< Invalid nand boot peripheral specified */
821 /**
822 * @def ibl_FAIL_CODE_NO_EMIF_CFG
823 */
824 #define ibl_FAIL_CODE_NO_EMIF_CFG 708 /**< No emif configuration found to match specified cs space */
826 /**
827 * @def ibl_FAIL_CODE_EMIF_CFG_FAIL
828 */
829 #define ibl_FAIL_CODE_EMIF_CFG_FAIL 709 /**< Hardware setup of emif failed */
831 /* @} */
834 /**
835 * @brief
836 * Provide status on the boot operation
837 *
838 * @details
839 * Run time status of the IBL is provided to aid in debugging
840 *
841 */
842 typedef struct iblStatus_s
843 {
844 uint32 iblMagic; /**< The @ref ibl_MAGIC_VALUE is placed here to indicate the boot has begun */
846 uint32 iblVersion; /**< The version number. MSB = major, SMSB = minor, SLSB = minor minor LSB= tiny */
848 uint32 iblFail; /**< If non-zero the IBL has encountered a fatal error */
850 uint32 i2cRetries; /**< Count of I2C read retries */
851 uint32 i2cDataRetries; /**< Number of retries while reading block data from the i2c */
853 uint32 spiRetries; /**< Count of SPI read retries */
854 uint32 spiDataRetries; /**< Number of retries while reading block data from the spi */
856 uint32 magicRetries; /**< Count of I2C/SPI re-reads because the magic number was incorrect */
857 uint32 mapSizeFail; /**< Number of times an invalid map table size was read from the i2c/spi */
858 uint32 mapRetries; /**< Number of times the checksum failed on the read of the i2c/spi map */
860 int32 heartBeat; /**< An increasing value as long as the boot code is running */
862 int32 activeBoot; /**< Describes the active boot mode @ref iblBootModes */
863 int32 activeDevice; /**< Describes the active boot peripheral device @ref iblActiveDevice */
864 int32 activeFileFormat; /**< Describes the format being decoded */
866 uint32 autoDetectFailCnt; /**< Counts the number of times an auto detect of the data format failed */
867 uint32 nameDetectFailCnt; /**< Counts the number of times an name detect of the data format failed */
869 uint32 invalidDataFormatSpec; /**< Counts the number of times the main boot found an invalid boot format request */
871 uint32 exitAddress; /**< If non-zero the IBL exited and branched to this address */
873 iblEthBootInfo_t ethParams; /**< Last ethernet boot attemp parameters */
875 } iblStatus_t;
877 extern iblStatus_t iblStatus;
880 /**
881 * @brief
882 * The ibl boot map structure
883 *
884 * @details
885 * The ibl boot device contains a structure which identifies the location of the big and little
886 * endian ibl images on the external device.
887 */
888 typedef struct iblBootMap_s
889 {
890 uint16 length; /**< Size of the structure in bytes */
891 uint16 chkSum; /**< Value which makes the ones complement checksum over the block equal to 0 or -0 */
893 uint32 addrLe; /**< Base address of the boot tables for the little endian image */
894 uint32 configLe; /**< Base address of the ibl structure for use with the little endian image */
896 uint32 addrBe; /**< Base address of the boot tables for the big endian image */
897 uint32 configBe; /**< Base address of the ibl structure for use with the big endian image */
899 } iblBootMap_t;
907 #endif /* IBL_H */