1 /**
2 * @file iblinit.c
3 *
4 * @brief
5 * This file contains code which runs prior to loading the full IBL
6 *
7 * @details
8 * The IBL loads itself in a two stage process. The ROM boot loader
9 * loads this first stage IBL first. This entire program must be
10 * endian independent in execution.
11 *
12 * This first loader reads the IBL parameters, and will endian
13 * switch them if required. The PLL is configured if indicated
14 * by the parameters.
15 *
16 * The I2C block which contains the I2C EEPROM address for both
17 * the big and little endian images is then read. Based on the
18 * endianness of the device the rest of the IBL is read from
19 * the I2C EEPROM, and execution is transferred to the full
20 * IBL.
21 *
22 * The subsequent reads are allowed to cross 16 bit i2c EEPROM
23 * addresses. When the boundary is crossed the i2c address
24 * field is incremented.
25 *
26 */
28 #include "ibl.h"
29 #include "iblloc.h"
30 #include "iblcfg.h"
31 #include "device.h"
32 #include "iblbtbl.h"
33 #include "i2c.h"
34 #include <string.h>
37 /**
38 * @brief
39 * Data structures shared between the 1st and 2nd stage IBL load
40 * are declared in a single header file, included in both stages
41 */
42 #include "iblStage.h"
44 /**
45 * @brief
46 * byte swapping of i2c data must be done when in little endian mode
47 */
48 bool littleEndian;
50 /**
51 * @brief
52 * The boot table processing status is declared in the boot table wrapper,
53 * and used here in the main status fields.
54 */
55 extern Int32 btblWrapEcode;
57 /**
58 * @brief
59 * The malloc function used for both boot stages of the ibl
60 */
61 void *iblMalloc (Uint32 size)
62 {
63 return (malloc (size));
64 }
66 /**
67 * @brief
68 * The free function used for both stages of the ibl
69 */
70 void iblFree (void *mem)
71 {
72 free (mem);
73 }
75 /**
76 * @brief
77 * The memset function used for both stages of the ibl
78 */
79 void *iblMemset (void *mem, Int32 ch, Uint32 n)
80 {
81 return (memset (mem, ch, n));
82 }
84 /**
85 * @brief
86 * The memcpy function used for both stages of the ibl
87 */
88 void *iblMemcpy (void *s1, const void *s2, Uint32 n)
89 {
90 return (memcpy (s1, s2, n));
92 }
94 /**
95 * @brief
96 * Ones complement addition
97 */
98 inline uint16 onesComplementAdd (uint16 value1, uint16 value2)
99 {
100 uint32 result;
102 result = (uint32)value1 + (uint32)value2;
104 result = (result >> 16) + (result & 0xFFFF); /* add in carry */
105 result += (result >> 16); /* maybe one more */
106 return ((uint16)result);
107 }
110 /**
111 * @brief
112 * Ones complement checksum computation
113 */
114 uint16 onesComplementChksum (uint16 * restrict p_data, uint16 len)
115 {
116 uint16 chksum = 0;
118 while (len > 0)
119 {
120 chksum = onesComplementAdd(chksum, *p_data);
121 p_data++;
122 len--;
123 }
124 return (chksum);
125 }
129 /**
130 * @brief
131 * Do a 4 byte endian swap
132 */
133 uint32 swap32val (uint32 v)
134 {
135 v = (((v >> 24) & 0xff) << 0) |
136 (((v >> 16) & 0xff) << 8) |
137 (((v >> 8) & 0xff) << 16) |
138 (((v >> 0) & 0xff) << 24);
140 return (v);
142 }
144 /**
145 * @brief
146 * Do a 2 byte endian swap
147 */
148 uint16 swap16val (uint16 v)
149 {
150 v = (((v >> 8) & 0xff) << 0) |
151 (((v >> 0) & 0xff) << 8);
153 return (v);
155 }
157 /**
158 * @brief
159 * Do an endian swap on the ibl structure
160 */
161 void iblSwap (void)
162 {
163 int i;
165 ibl.iblMagic = swap32val (ibl.iblMagic);
167 for (i = 0; i < ibl_N_PLL_CFGS; i++) {
168 ibl.pllConfig[i].doEnable = swap16val (ibl.pllConfig[i].doEnable);
169 ibl.pllConfig[i].prediv = swap32val (ibl.pllConfig[i].prediv);
170 ibl.pllConfig[i].mult = swap32val (ibl.pllConfig[i].mult);
171 ibl.pllConfig[i].postdiv = swap32val (ibl.pllConfig[i].postdiv);
172 ibl.pllConfig[i].pllOutFreqMhz = swap32val (ibl.pllConfig[i].pllOutFreqMhz);
173 }
175 ibl.ddrConfig.configDdr = swap16val (ibl.ddrConfig.configDdr);
177 ibl.ddrConfig.uEmif.emif3p1.sdcfg = swap32val(ibl.ddrConfig.uEmif.emif3p1.sdcfg);
178 ibl.ddrConfig.uEmif.emif3p1.sdrfc = swap32val(ibl.ddrConfig.uEmif.emif3p1.sdrfc);
179 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = swap32val(ibl.ddrConfig.uEmif.emif3p1.sdtim1);
180 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = swap32val(ibl.ddrConfig.uEmif.emif3p1.sdtim2);
181 ibl.ddrConfig.uEmif.emif3p1.dmcctl = swap32val(ibl.ddrConfig.uEmif.emif3p1.dmcctl);
183 for (i = 0; i < ibl_N_ETH_PORTS; i++) {
184 ibl.ethConfig[i].ethPriority = swap32val (ibl.ethConfig[i].ethPriority);
185 ibl.ethConfig[i].port = swap32val (ibl.ethConfig[i].port);
186 ibl.ethConfig[i].doBootp = swap16val (ibl.ethConfig[i].doBootp);
187 ibl.ethConfig[i].useBootpServerIp = swap16val (ibl.ethConfig[i].useBootpServerIp);
188 ibl.ethConfig[i].useBootpFileName = swap16val (ibl.ethConfig[i].useBootpFileName);
189 ibl.ethConfig[i].bootFormat = swap32val (ibl.ethConfig[i].bootFormat);
190 ibl.ethConfig[i].blob.startAddress = swap32val (ibl.ethConfig[i].blob.startAddress);
191 ibl.ethConfig[i].blob.sizeBytes = swap32val (ibl.ethConfig[i].blob.sizeBytes);
192 ibl.ethConfig[i].blob.branchAddress = swap32val (ibl.ethConfig[i].blob.branchAddress);
194 ibl.sgmiiConfig[i].adviseAbility = swap32val (ibl.sgmiiConfig[i].adviseAbility);
195 ibl.sgmiiConfig[i].control = swap32val (ibl.sgmiiConfig[i].control);
196 ibl.sgmiiConfig[i].txConfig = swap32val (ibl.sgmiiConfig[i].txConfig);
197 ibl.sgmiiConfig[i].rxConfig = swap32val (ibl.sgmiiConfig[i].rxConfig);
198 ibl.sgmiiConfig[i].auxConfig = swap32val (ibl.sgmiiConfig[i].auxConfig);
199 }
201 ibl.mdioConfig.nMdioOps = swap16val (ibl.mdioConfig.nMdioOps);
202 ibl.mdioConfig.mdioClkDiv = swap16val (ibl.mdioConfig.mdioClkDiv);
203 ibl.mdioConfig.interDelay = swap32val (ibl.mdioConfig.interDelay);
205 for (i = 0; i < ibl_N_MDIO_CFGS; i++)
206 ibl.mdioConfig.mdio[i] = swap32val (ibl.mdioConfig.mdio[i]);
208 ibl.nandConfig.nandPriority = swap32val (ibl.nandConfig.nandPriority);
209 ibl.nandConfig.bootFormat = swap32val (ibl.nandConfig.bootFormat);
210 ibl.nandConfig.blob.startAddress = swap32val (ibl.nandConfig.blob.startAddress);
211 ibl.nandConfig.blob.sizeBytes = swap32val (ibl.nandConfig.blob.sizeBytes);
212 ibl.nandConfig.blob.branchAddress = swap32val (ibl.nandConfig.blob.branchAddress);
214 ibl.nandConfig.nandInfo.busWidthBits = swap32val (ibl.nandConfig.nandInfo.busWidthBits);
215 ibl.nandConfig.nandInfo.pageSizeBytes = swap32val (ibl.nandConfig.nandInfo.pageSizeBytes);
216 ibl.nandConfig.nandInfo.pageEccBytes = swap32val (ibl.nandConfig.nandInfo.pageEccBytes);
217 ibl.nandConfig.nandInfo.pagesPerBlock = swap32val (ibl.nandConfig.nandInfo.pagesPerBlock);
218 ibl.nandConfig.nandInfo.totalBlocks = swap32val (ibl.nandConfig.nandInfo.totalBlocks);
219 ibl.nandConfig.nandInfo.addressBytes = swap32val (ibl.nandConfig.nandInfo.addressBytes);
220 ibl.nandConfig.nandInfo.lsbFirst = swap16val (ibl.nandConfig.nandInfo.lsbFirst);
221 ibl.nandConfig.nandInfo.blockOffset = swap32val (ibl.nandConfig.nandInfo.blockOffset);
222 ibl.nandConfig.nandInfo.pageOffset = swap32val (ibl.nandConfig.nandInfo.pageOffset);
223 ibl.nandConfig.nandInfo.columnOffset = swap32val (ibl.nandConfig.nandInfo.columnOffset);
224 ibl.nandConfig.nandInfo.postCommand = swap16val (ibl.nandConfig.nandInfo.postCommand);
226 ibl.chkSum = swap16val (ibl.chkSum);
227 }
231 /**
232 * @brief
233 * The i2c load context consists of the address of the next block
234 * to read, and a simple fifo holding any existing data.
235 */
236 #define I2C_MAX_BLOCK_SIZE 0x80
237 uint32 i2cReadAddress;
239 uint32 i2cFifoIn = 0;
240 uint32 i2cFifoOut = 0;
241 uint8 i2cData[I2C_MAX_BLOCK_SIZE];
242 uint16 i2cSum[I2C_MAX_BLOCK_SIZE >> 1];
245 /**
246 * @brief
247 * Return the number of elements in the fifo
248 */
249 Uint32 i2cFifoCount (void)
250 {
251 Int32 count;
253 if (i2cFifoIn >= i2cFifoOut)
254 count = i2cFifoIn - i2cFifoOut;
255 else
256 count = i2cFifoIn + I2C_MAX_BLOCK_SIZE - i2cFifoOut;
258 return (count);
260 }
263 /**
264 * @brief
265 * Read a byte from the fifo
266 */
267 Uint8 i2cFifoRead(void)
268 {
269 Uint8 v;
271 v = i2cData[i2cFifoOut];
273 i2cFifoOut += 1;
275 if (i2cFifoOut == i2cFifoIn)
276 i2cFifoOut = i2cFifoIn = 0;
278 if (i2cFifoOut >= I2C_MAX_BLOCK_SIZE)
279 i2cFifoOut = 0;
281 return (v);
283 }
285 /**
286 * @brief
287 * Read a block of data from the I2C eeprom and put it in the fifo
288 */
289 void i2cReadBlock (void)
290 {
291 uint16 len;
292 int32 i, j;
293 uint32 v;
295 for (;;) {
296 while (hwI2cMasterRead (i2cReadAddress & 0xffff, /* The address on the eeprom of the table */
297 4, /* The number of bytes to read */
298 i2cData, /* Where to store the bytes */
299 i2cReadAddress >> 16, /* The bus address of the eeprom */
300 IBL_CFG_I2C_ADDR_DELAY) /* The delay between sending the address and reading data */
302 != I2C_RET_OK) {
304 iblStatus.i2cDataRetries += 1;
305 }
307 /* Form the length. The received bytes are always in big endian format */
308 len = (i2cData[0] << 8) | i2cData[1];
311 if (len > I2C_MAX_BLOCK_SIZE)
312 continue;
315 while (hwI2cMasterRead (i2cReadAddress & 0xffff, /* The address on the eeprom of the table */
316 len, /* The number of bytes to read */
317 i2cData, /* Where to store the bytes */
318 i2cReadAddress >> 16, /* The bus address of the eeprom */
319 IBL_CFG_I2C_ADDR_DELAY) /* The delay between sending the address and reading data */
321 != I2C_RET_OK) {
323 iblStatus.i2cDataRetries += 1;
324 }
327 /* Must do endian conversion to verify the checksum */
328 for (i = j = 0; i < len; i += 2, j += 1)
329 i2cSum[j] = (i2cData[i+0] << 8) | i2cData[i+1];
331 v = onesComplementChksum (i2cSum, j);
332 if ((v == 0) || (v == 0xffff))
333 break;
336 iblStatus.i2cDataRetries += 1;
338 }
341 i2cReadAddress += len;
343 i2cFifoIn = len;
344 i2cFifoOut = 4; /* The i2c header is effectively removed */
346 }
351 /**
352 * @brief
353 * Read data from the I2C to pass to the interpreter
354 */
355 Int32 iblI2cRead (Uint8 *buf, Uint32 num_bytes)
356 {
357 int i;
359 for (i = 0; i < num_bytes; i++) {
361 if (i2cFifoCount() == 0)
362 i2cReadBlock ();
364 buf[i] = i2cFifoRead();
365 }
367 return (0);
369 }
371 #define iblBITMASK(x,y) ( ( ( ((UINT32)1 << (((UINT32)x)-((UINT32)y)+(UINT32)1) ) - (UINT32)1 ) ) << ((UINT32)y) )
372 #define iblREAD_BITFIELD(z,x,y) (((UINT32)z) & iblBITMASK(x,y)) >> (y)
373 /**
374 * @brief
375 * Return the lower 16 bits of a 32 bit value. A function is used (with cross-function optomization off)
376 * which results in an endian independent version
377 */
378 uint16 readLower16 (uint32 v)
379 {
380 return (iblREAD_BITFIELD(v,15,0));
382 }
384 /**
385 * @brief
386 * Return the upper 16 bits of a 32 bit value. A function is used to force an endian independent version
387 */
388 uint16 readUpper16 (uint32 v)
389 {
390 return (iblREAD_BITFIELD(v,31,16));
391 }
394 /**
395 * @brief
396 * The module function table used for boot from i2c
397 */
398 BOOT_MODULE_FXN_TABLE i2cinit_boot_module =
399 {
400 NULL, /* Open API */
401 NULL, /* Close API */
402 iblI2cRead, /* Read API */
403 NULL, /* Write API */
404 NULL, /* Peek API */
405 NULL, /* Seek API */
406 NULL /* Query API */
407 };
411 /**
412 * @brief
413 * The main function
414 *
415 * @details
416 * The ibl configuration parameters are read from the i2c,
417 * followed by the i2c mapping information. The second stage
418 * of the IBL is then loaded, and execution transferred
419 * to the second stage.
420 */
421 void main (void)
422 {
424 uint16 v;
425 uint16 configAddrLsw;
426 uint16 configAddrMsw;
427 uint32 entry;
428 void (*exit)();
429 iblI2cMap_t map;
431 memset (&iblStatus, 0, sizeof(iblStatus_t));
432 iblStatus.iblMagic = ibl_MAGIC_VALUE;
433 iblStatus.iblVersion = ibl_VERSION;
434 iblStatus.activePeriph = ibl_ACTIVE_PERIPH_I2C;
436 /* Read the endianness setting of the device */
437 littleEndian = deviceIsLittleEndian();
439 /* Load the default configuration table from the i2c. The actual speed of the device
440 * isn't really known here, since it is part of the table, so a compile time
441 * value is used (the pll may have been configured during the initial load) */
442 hwI2Cinit (IBL_CFG_I2C_DEV_FREQ_MHZ, /* The CPU frequency during I2C data load */
443 DEVICE_I2C_MODULE_DIVISOR, /* The divide down of CPU that drives the i2c */
444 IBL_CFG_I2C_CLK_FREQ_KHZ, /* The I2C data rate used during table load */
445 IBL_CFG_I2C_OWN_ADDR); /* The address used by this device on the i2c bus */
448 /* Read the I2C mapping information from the eeprom */
449 for (;;) {
450 if (hwI2cMasterRead (IBL_CFG_I2C_MAP_TABLE_DATA_ADDR, /* The address on the eeprom of the data mapping */
451 sizeof(iblI2cMap_t), /* The number of bytes to read */
452 (UINT8 *)&map, /* Where to store the bytes */
453 IBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR, /* The bus address of the eeprom */
454 IBL_CFG_I2C_ADDR_DELAY) /* The delay between sending the address and reading data */
456 == I2C_RET_OK) {
458 /* On the I2C EEPROM the table is always formatted with the most significant
459 * byte first. So if the device is running little endain the endian must be
460 * swapped */
461 if (littleEndian == TRUE) {
462 map.length = swap16val (map.length);
463 map.chkSum = swap16val (map.chkSum);
464 map.addrLe = swap32val (map.addrLe);
465 map.configLe = swap32val (map.configLe);
466 map.addrBe = swap32val (map.addrBe);
467 map.configBe = swap32val (map.configBe);
469 configAddrLsw = readLower16 (map.configLe);
470 configAddrMsw = readUpper16 (map.configLe);
472 } else {
473 configAddrLsw = readLower16 (map.configBe);
474 configAddrMsw = readUpper16 (map.configLe);
476 }
479 if (map.length != sizeof(iblI2cMap_t)) {
480 iblStatus.mapSizeFail += 1;
481 continue;
482 }
484 if (map.chkSum != 0) {
486 v = onesComplementChksum ((UINT16 *)&map, sizeof(iblI2cMap_t));
487 if ((v != 0) && (v != 0xffff)) {
488 iblStatus.mapRetries += 1;
489 continue;
490 }
491 }
493 break;
494 }
496 iblStatus.mapRetries += 1;
498 }
501 /* Read the i2c configuration tables until the checksum passes and the magic number
502 * matches. The checksum must be verified before the endian re-ordering is done */
503 for (;;) {
505 if (hwI2cMasterRead (configAddrLsw, /* The address on the eeprom of the table */
506 sizeof(ibl_t), /* The number of bytes to read */
507 (UINT8 *)&ibl, /* Where to store the bytes */
508 configAddrMsw, /* The bus address of the eeprom */
509 IBL_CFG_I2C_ADDR_DELAY) /* The delay between sending the address and reading data */
511 == I2C_RET_OK) {
513 if (ibl.chkSum != 0) {
515 v = onesComplementChksum ((UINT16 *)&ibl, sizeof(ibl_t) / sizeof(UINT16));
516 if ((v != 0) && (v != 0xffff)) {
517 iblStatus.i2cRetries += 1;
518 continue;
519 }
521 }
524 if (ibl.iblMagic == ibl_MAGIC_VALUE)
525 break;
527 if (swap32val (ibl.iblMagic) == ibl_MAGIC_VALUE) {
528 iblSwap ();
529 break;
530 }
532 iblStatus.magicRetries += 1;
534 }
536 iblStatus.i2cRetries += 1;
537 }
539 /* Pll configuration is device specific */
540 devicePllConfig ();
543 /* The rest of the IBL is in boot table format. Read and process the data */
544 if (littleEndian == TRUE)
545 i2cReadAddress = map.addrLe;
546 else
547 i2cReadAddress = map.addrBe;
549 if (i2cReadAddress == 0xffffffff) {
550 iblStatus.iblFail = ibl_FAIL_CODE_INVALID_I2C_ADDRESS;
551 for (;;);
552 }
555 /* Pass control to the boot table processor */
556 iblBootBtbl (&i2cinit_boot_module, &entry);
558 if (btblWrapEcode != 0) {
559 iblStatus.iblFail = ibl_FAIL_CODE_BTBL_FAIL;
560 for (;;);
561 }
563 /* jump to the exit point, which will be the entry point for the full IBL */
564 exit = (void (*)())entry;
565 (*exit)();
568 }