1 #define TRUE 1\r
2 #define FALSE 0\r
3 \r
4 #define ibl_MAGIC_VALUE 0xCEC11EBB\r
5 \r
6 #define ibl_HIGHEST_PRIORITY 1 \r
7 #define ibl_LOWEST_PRIORITY 10\r
8 #define ibl_DEVICE_NOBOOT 20\r
9 \r
10 #define SETIP(array,i0,i1,i2,i3) array[0]=(i0); \\r
11 array[1]=(i1); \\r
12 array[2]=(i2); \\r
13 array[3]=(i3)\r
14 \r
15 #define ibl_BOOT_FORMAT_AUTO 0\r
16 #define ibl_BOOT_FORMAT_NAME 1\r
17 #define ibl_BOOT_FORMAT_BIS 2\r
18 #define ibl_BOOT_FORMAT_COFF 3\r
19 #define ibl_BOOT_FORMAT_ELF 4\r
20 #define ibl_BOOT_FORMAT_BBLOB 5\r
21 #define ibl_BOOT_FORMAT_BTBL 6\r
22 \r
23 #define ibl_MAIN_PLL 0\r
24 #define ibl_DDR_PLL 1\r
25 #define ibl_NET_PLL 2\r
26 \r
27 \r
28 menuitem "EVM c6472 IBL";\r
29 \r
30 hotmenu setConfig_c6472()\r
31 {\r
32 ibl.iblMagic = ibl_MAGIC_VALUE;\r
33 \r
34 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;\r
35 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;\r
36 ibl.pllConfig[ibl_MAIN_PLL].mult = 28;\r
37 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;\r
38 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 700;\r
39 \r
40 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
41 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
42 \r
43 /* The network PLL. The multipliers/dividers are fixed */\r
44 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
45 \r
46 /* EMIF configuration. The values are for DDR at 533 MHz */\r
47 ibl.ddrConfig.configDdr = TRUE;\r
48 \r
49 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538832; /* timing, 32bit wide */\r
50 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x0000073B; /* Refresh 533Mhz */ \r
51 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x47245BD2; /* Timing 1 */\r
52 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */\r
53 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */\r
54 \r
55 /* Ethernet configuration for port 0 */\r
56 ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;\r
57 ibl.ethConfig[0].port = 0;\r
58 \r
59 /* Bootp is disabled. The server and file name are provided here */\r
60 ibl.ethConfig[0].doBootp = FALSE;\r
61 ibl.ethConfig[0].useBootpServerIp = FALSE;\r
62 ibl.ethConfig[0].useBootpFileName = FALSE;\r
63 ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_AUTO;\r
64 \r
65 \r
66 SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 10,218,109,21);\r
67 SETIP(ibl.ethConfig[0].ethInfo.serverIp, 10,218,109,196);\r
68 SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,2);\r
69 SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);\r
70 \r
71 /* Leave the hardware address as 0 so the e-fuse value will be used */\r
72 \r
73 \r
74 \r
75 \r
76 ibl.ethConfig[0].ethInfo.fileName[0] = 't';\r
77 ibl.ethConfig[0].ethInfo.fileName[1] = 'e';\r
78 ibl.ethConfig[0].ethInfo.fileName[2] = 's';\r
79 ibl.ethConfig[0].ethInfo.fileName[3] = 't';\r
80 ibl.ethConfig[0].ethInfo.fileName[4] = '.';\r
81 ibl.ethConfig[0].ethInfo.fileName[5] = 'o';\r
82 ibl.ethConfig[0].ethInfo.fileName[6] = 'u';\r
83 ibl.ethConfig[0].ethInfo.fileName[7] = 't';\r
84 ibl.ethConfig[0].ethInfo.fileName[8] = '\0';\r
85 ibl.ethConfig[0].ethInfo.fileName[9] = '\0';\r
86 ibl.ethConfig[0].ethInfo.fileName[10] = '\0';\r
87 ibl.ethConfig[0].ethInfo.fileName[11] = '\0';\r
88 ibl.ethConfig[0].ethInfo.fileName[12] = '\0';\r
89 ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
90 ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
91 \r
92 /* Even though the entire range of DDR2 is chosen, the load will\r
93 * stop when the ftp reaches the end of the file */\r
94 ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */\r
95 ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */\r
96 ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */\r
97 \r
98 /* For port 1 use bootp */\r
99 /* Ethernet configuration for port 0 */\r
100 ibl.ethConfig[1].ethPriority = ibl_HIGHEST_PRIORITY + 1;\r
101 ibl.ethConfig[1].port = 1;\r
102 \r
103 /* Bootp is disabled. The server and file name are provided here */\r
104 ibl.ethConfig[1].doBootp = TRUE;\r
105 ibl.ethConfig[1].useBootpServerIp = TRUE;\r
106 ibl.ethConfig[1].useBootpFileName = TRUE;\r
107 ibl.ethConfig[1].bootFormat = ibl_BOOT_FORMAT_AUTO;\r
108 \r
109 \r
110 /* SGMII not present */\r
111 ibl.sgmiiConfig[0].adviseAbility = 0;\r
112 ibl.sgmiiConfig[0].control = 0;\r
113 ibl.sgmiiConfig[0].txConfig = 0;\r
114 ibl.sgmiiConfig[0].rxConfig = 0;\r
115 ibl.sgmiiConfig[0].auxConfig = 0;\r
116 \r
117 ibl.sgmiiConfig[1].adviseAbility = 0;\r
118 ibl.sgmiiConfig[1].control = 0;\r
119 ibl.sgmiiConfig[1].txConfig = 0;\r
120 ibl.sgmiiConfig[1].rxConfig = 0;\r
121 ibl.sgmiiConfig[1].auxConfig = 0;\r
122 \r
123 \r
124 /* Leave the hardware address as 0 so the e-fuse value will be used */\r
125 ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;\r
126 ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;\r
127 ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;\r
128 ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;\r
129 ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;\r
130 ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;\r
131 \r
132 \r
133 /* Leave all remaining fields as 0 since bootp will fill them in */\r
134 \r
135 \r
136 /* Even though the entire range of DDR2 is chosen, the load will */\r
137 /* stop when the ftp reaches the end of the file */\r
138 \r
139 ibl.ethConfig[1].blob.startAddress = 0xe0000000; /* Base address of DDR2 */\r
140 ibl.ethConfig[1].blob.sizeBytes = 0x20000000; /* All of DDR2 */\r
141 ibl.ethConfig[1].blob.branchAddress = 0xe0000000; /* Base of DDR2 */\r
142 \r
143 \r
144 \r
145 /* MDIO configuration */\r
146 ibl.mdioConfig.nMdioOps = 8;\r
147 ibl.mdioConfig.mdioClkDiv = 0x20;\r
148 ibl.mdioConfig.interDelay = 1400; /* ~2ms at 700 MHz */\r
149 \r
150 ibl.mdioConfig.mdio[0] = (1 << 30) | (27 << 21) | (24 << 16) | 0x848b;\r
151 ibl.mdioConfig.mdio[1] = (1 << 30) | (20 << 21) | (24 << 16) | 0x0ce0;\r
152 ibl.mdioConfig.mdio[2] = (1 << 30) | (24 << 21) | (24 << 16) | 0x4101;\r
153 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (24 << 16) | 0x9140;\r
154 \r
155 ibl.mdioConfig.mdio[4] = (1 << 30) | (27 << 21) | (25 << 16) | 0x848b;\r
156 ibl.mdioConfig.mdio[5] = (1 << 30) | (20 << 21) | (25 << 16) | 0x0ce0;\r
157 ibl.mdioConfig.mdio[6] = (1 << 30) | (24 << 21) | (25 << 16) | 0x4101;\r
158 ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | (25 << 16) | 0x9140;\r
159 \r
160 \r
161 /* Nand boot is disabled */\r
162 ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
163 \r
164 ibl.nandConfig.bootFormat = ibl_BOOT_FORMAT_AUTO;\r
165 \r
166 ibl.nandConfig.nandInfo.busWidthBits = 8;\r
167 ibl.nandConfig.nandInfo.pageSizeBytes = 2048;\r
168 ibl.nandConfig.nandInfo.pageEccBytes = 64;\r
169 ibl.nandConfig.nandInfo.pagesPerBlock = 64;\r
170 ibl.nandConfig.nandInfo.totalBlocks = 1024;\r
171 \r
172 ibl.nandConfig.nandInfo.addressBytes = 4;\r
173 ibl.nandConfig.nandInfo.lsbFirst = TRUE;\r
174 ibl.nandConfig.nandInfo.blockOffset = 22;\r
175 ibl.nandConfig.nandInfo.pageOffset = 16;\r
176 ibl.nandConfig.nandInfo.columnOffset = 0;\r
177 \r
178 ibl.nandConfig.nandInfo.resetCommand = 0xff;\r
179 ibl.nandConfig.nandInfo.readCommandPre = 0;\r
180 ibl.nandConfig.nandInfo.readCommandPost = 0x30;\r
181 ibl.nandConfig.nandInfo.postCommand = TRUE;\r
182 \r
183 }\r
184 \r
185 \r
186 menuitem "EVM c6474 Mez IBL";\r
187 \r
188 hotmenu setConfig_c6474()\r
189 {\r
190 ibl.iblMagic = ibl_MAGIC_VALUE;\r
191 \r
192 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;\r
193 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;\r
194 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;\r
195 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;\r
196 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;\r
197 \r
198 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
199 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
200 \r
201 /* The network PLL. The multipliers/dividers are fixed */\r
202 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
203 \r
204 /* EMIF configuration. The values are for DDR at 533 MHz */\r
205 ibl.ddrConfig.configDdr = TRUE;\r
206 \r
207 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */\r
208 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */ \r
209 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */\r
210 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */\r
211 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */\r
212 \r
213 \r
214 /* Ethernet configuration for port 0 */\r
215 ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;\r
216 ibl.ethConfig[0].port = 0;\r
217 \r
218 /* Bootp is disabled. The server and file name are provided here */\r
219 ibl.ethConfig[0].doBootp = FALSE;\r
220 ibl.ethConfig[0].useBootpServerIp = FALSE;\r
221 ibl.ethConfig[0].useBootpFileName = FALSE;\r
222 ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;\r
223 \r
224 SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 10,218,109,35);\r
225 SETIP(ibl.ethConfig[0].ethInfo.serverIp, 10,218,109,196);\r
226 SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,1);\r
227 SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);\r
228 \r
229 /* Set the hardware address as 0 so the e-fuse value will be used */\r
230 ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;\r
231 ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;\r
232 ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;\r
233 ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;\r
234 ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;\r
235 ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;\r
236 \r
237 \r
238 ibl.ethConfig[0].ethInfo.fileName[0] = 't';\r
239 ibl.ethConfig[0].ethInfo.fileName[1] = 'e';\r
240 ibl.ethConfig[0].ethInfo.fileName[2] = 's';\r
241 ibl.ethConfig[0].ethInfo.fileName[3] = 't';\r
242 ibl.ethConfig[0].ethInfo.fileName[4] = '.';\r
243 ibl.ethConfig[0].ethInfo.fileName[5] = 'b';\r
244 ibl.ethConfig[0].ethInfo.fileName[6] = 'l';\r
245 ibl.ethConfig[0].ethInfo.fileName[7] = 'o';\r
246 ibl.ethConfig[0].ethInfo.fileName[8] = 'b';\r
247 ibl.ethConfig[0].ethInfo.fileName[9] = '\0';\r
248 ibl.ethConfig[0].ethInfo.fileName[10] = '\0';\r
249 ibl.ethConfig[0].ethInfo.fileName[11] = '\0';\r
250 ibl.ethConfig[0].ethInfo.fileName[12] = '\0';\r
251 ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
252 ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
253 \r
254 \r
255 /* Even though the entire range of DDR2 is chosen, the load will\r
256 * stop when the ftp reaches the end of the file */\r
257 ibl.ethConfig[0].blob.startAddress = 0x80000000; /* Base address of DDR2 */\r
258 ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */\r
259 ibl.ethConfig[0].blob.branchAddress = 0x80000000; /* Base of DDR2 */\r
260 \r
261 /* There is no port 1 on the 6474 */\r
262 ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;\r
263 \r
264 /* SGMII is present */\r
265 ibl.sgmiiConfig[0].adviseAbility = 0x9801;\r
266 ibl.sgmiiConfig[0].control = 0x20;\r
267 ibl.sgmiiConfig[0].txConfig = 0x00000ea3;\r
268 ibl.sgmiiConfig[0].rxConfig = 0x00081023;\r
269 ibl.sgmiiConfig[0].auxConfig = 0x0000000b;\r
270 \r
271 /* MDIO configuration */\r
272 ibl.mdioConfig.nMdioOps = 8;\r
273 ibl.mdioConfig.mdioClkDiv = 0x26;\r
274 ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */\r
275 \r
276 ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;\r
277 ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;\r
278 ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;\r
279 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;\r
280 \r
281 ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;\r
282 ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
283 ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
284 ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;\r
285 \r
286 \r
287 /* Nand boot is disabled */\r
288 ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
289 \r
290 }\r
291 \r
292 menuitem "EVM c6474 Lite EVM IBL";\r
293 \r
294 hotmenu setConfig_c6474lite()\r
295 {\r
296 ibl.iblMagic = ibl_MAGIC_VALUE;\r
297 \r
298 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;\r
299 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;\r
300 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;\r
301 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;\r
302 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;\r
303 \r
304 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
305 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
306 \r
307 /* The network PLL. The multipliers/dividers are fixed */\r
308 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
309 \r
310 /* EMIF configuration. The values are for DDR at 533 MHz */\r
311 ibl.ddrConfig.configDdr = TRUE;\r
312 \r
313 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */\r
314 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */ \r
315 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */\r
316 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */\r
317 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */\r
318 \r
319 \r
320 /* Ethernet configuration for port 0 */\r
321 ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;\r
322 ibl.ethConfig[0].port = 0;\r
323 \r
324 /* Bootp is disabled. The server and file name are provided here */\r
325 ibl.ethConfig[0].doBootp = FALSE;\r
326 ibl.ethConfig[0].useBootpServerIp = FALSE;\r
327 ibl.ethConfig[0].useBootpFileName = FALSE;\r
328 ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;\r
329 \r
330 SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,114);\r
331 SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);\r
332 SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);\r
333 SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);\r
334 \r
335 /* Set the hardware address as 0 so the e-fuse value will be used */\r
336 ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;\r
337 ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;\r
338 ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;\r
339 ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;\r
340 ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;\r
341 ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;\r
342 \r
343 \r
344 ibl.ethConfig[0].ethInfo.fileName[0] = 'c';\r
345 ibl.ethConfig[0].ethInfo.fileName[1] = '6';\r
346 ibl.ethConfig[0].ethInfo.fileName[2] = '4';\r
347 ibl.ethConfig[0].ethInfo.fileName[3] = '7';\r
348 ibl.ethConfig[0].ethInfo.fileName[4] = '4';\r
349 ibl.ethConfig[0].ethInfo.fileName[5] = 'l';\r
350 ibl.ethConfig[0].ethInfo.fileName[6] = '-';\r
351 ibl.ethConfig[0].ethInfo.fileName[7] = 'l';\r
352 ibl.ethConfig[0].ethInfo.fileName[8] = 'e';\r
353 ibl.ethConfig[0].ethInfo.fileName[9] = '.';\r
354 ibl.ethConfig[0].ethInfo.fileName[10] = 'b';\r
355 ibl.ethConfig[0].ethInfo.fileName[11] = 'i';\r
356 ibl.ethConfig[0].ethInfo.fileName[12] = 'n';\r
357 ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
358 ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
359 \r
360 \r
361 /* Even though the entire range of DDR2 is chosen, the load will\r
362 * stop when the ftp reaches the end of the file */\r
363 ibl.ethConfig[0].blob.startAddress = 0x80000000; /* Base address of DDR2 */\r
364 ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */\r
365 ibl.ethConfig[0].blob.branchAddress = 0x80000000; /* Base of DDR2 */\r
366 \r
367 /* There is no port 1 on the 6474 Lite EVM */\r
368 ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;\r
369 \r
370 /* SGMII is present */\r
371 ibl.sgmiiConfig[0].adviseAbility = 0x9801;\r
372 ibl.sgmiiConfig[0].control = 0x20;\r
373 ibl.sgmiiConfig[0].txConfig = 0x00000e23;\r
374 ibl.sgmiiConfig[0].rxConfig = 0x00081023;\r
375 ibl.sgmiiConfig[0].auxConfig = 0x0000000b;\r
376 \r
377 /* MDIO configuration */\r
378 ibl.mdioConfig.nMdioOps = 8;\r
379 ibl.mdioConfig.mdioClkDiv = 0x26;\r
380 ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */\r
381 \r
382 ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;\r
383 ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;\r
384 ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;\r
385 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;\r
386 \r
387 ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;\r
388 ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
389 ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
390 ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;\r
391 \r
392 \r
393 /* This board has NAND. We will enable later */\r
394 ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
395 \r
396 }\r
397 \r
398 menuitem "EVM c6455 IBL";\r
399 \r
400 hotmenu setConfig_c6455()\r
401 {\r
402 ibl.iblMagic = ibl_MAGIC_VALUE;\r
403 \r
404 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;\r
405 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;\r
406 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;\r
407 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;\r
408 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;\r
409 \r
410 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
411 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
412 \r
413 /* The network PLL. The multipliers/dividers are fixed */\r
414 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
415 \r
416 /* EMIF configuration. The values are for DDR at 500 MHz */\r
417 ibl.ddrConfig.configDdr = TRUE;\r
418 \r
419 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538822; /* timing, 32bit wide */\r
420 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x000007a2; /* Refresh 500Mhz */ \r
421 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x3edb4b91; /* Timing 1 */\r
422 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00a2c722; /* Timing 2 */\r
423 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */\r
424 \r
425 /* Ethernet configuration for port 0 */\r
426 ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;\r
427 ibl.ethConfig[0].port = 0;\r
428 \r
429 /* Bootp is disabled. The server and file name are provided here */\r
430 ibl.ethConfig[0].doBootp = FALSE;\r
431 ibl.ethConfig[0].useBootpServerIp = FALSE;\r
432 ibl.ethConfig[0].useBootpFileName = FALSE;\r
433 ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;\r
434 \r
435 \r
436 SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,118);\r
437 SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);\r
438 SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);\r
439 SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);\r
440 \r
441 /* There is no e-fuse mac address. A value must be assigned\r
442 ibl.ethConfig[0].ethInfo.hwAddress[0] = 0x00;\r
443 ibl.ethConfig[0].ethInfo.hwAddress[1] = 0xe0;\r
444 ibl.ethConfig[0].ethInfo.hwAddress[2] = 0xa6;\r
445 ibl.ethConfig[0].ethInfo.hwAddress[3] = 0x66;\r
446 ibl.ethConfig[0].ethInfo.hwAddress[4] = 0x57;\r
447 ibl.ethConfig[0].ethInfo.hwAddress[5] = 0x19;\r
448 \r
449 \r
450 ibl.ethConfig[0].ethInfo.fileName[0] = 't';\r
451 ibl.ethConfig[0].ethInfo.fileName[1] = 'e';\r
452 ibl.ethConfig[0].ethInfo.fileName[2] = 's';\r
453 ibl.ethConfig[0].ethInfo.fileName[3] = 't';\r
454 ibl.ethConfig[0].ethInfo.fileName[4] = '.';\r
455 ibl.ethConfig[0].ethInfo.fileName[5] = 'b';\r
456 ibl.ethConfig[0].ethInfo.fileName[6] = 'l';\r
457 ibl.ethConfig[0].ethInfo.fileName[7] = 'o';\r
458 ibl.ethConfig[0].ethInfo.fileName[8] = 'b';\r
459 ibl.ethConfig[0].ethInfo.fileName[9] = '\0';\r
460 ibl.ethConfig[0].ethInfo.fileName[10] = '\0';\r
461 ibl.ethConfig[0].ethInfo.fileName[11] = '\0';\r
462 ibl.ethConfig[0].ethInfo.fileName[12] = '\0';\r
463 ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
464 ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
465 \r
466 \r
467 /* Even though the entire range of DDR2 is chosen, the load will\r
468 * stop when the ftp reaches the end of the file */\r
469 ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */\r
470 ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */\r
471 ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */\r
472 \r
473 /* There is no ethernet port 1 */\r
474 ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;\r
475 \r
476 \r
477 /* SGMII not present */\r
478 ibl.sgmiiConfig[0].adviseAbility = 0;\r
479 ibl.sgmiiConfig[0].control = 0;\r
480 ibl.sgmiiConfig[0].txConfig = 0;\r
481 ibl.sgmiiConfig[0].rxConfig = 0;\r
482 ibl.sgmiiConfig[0].auxConfig = 0;\r
483 \r
484 ibl.sgmiiConfig[1].adviseAbility = 0;\r
485 ibl.sgmiiConfig[1].control = 0;\r
486 ibl.sgmiiConfig[1].txConfig = 0;\r
487 ibl.sgmiiConfig[1].rxConfig = 0;\r
488 ibl.sgmiiConfig[1].auxConfig = 0;\r
489 \r
490 \r
491 \r
492 /* MDIO configuration */\r
493 ibl.mdioConfig.nMdioOps = 0;\r
494 ibl.mdioConfig.mdioClkDiv = 0x20;\r
495 ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */\r
496 \r
497 ibl.mdioConfig.mdio[0] = (1 << 30) | (14 << 21) | (0 << 16) | 0xd5d0;\r
498 \r
499 \r
500 /* Nand boot is disabled */\r
501 ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
502 \r
503 }\r
504 \r
505 \r