e8ae30af77b02a8502a98b2b8a777242df1cf421
1 #define TRUE 1\r
2 #define FALSE 0\r
3 \r
4 #define ibl_MAGIC_VALUE 0xCEC11EBB\r
5 \r
6 #define ibl_HIGHEST_PRIORITY 1 \r
7 #define ibl_LOWEST_PRIORITY 10\r
8 #define ibl_DEVICE_NOBOOT 20\r
9 \r
10 #define SETIP(array,i0,i1,i2,i3) array[0]=(i0); \\r
11 array[1]=(i1); \\r
12 array[2]=(i2); \\r
13 array[3]=(i3)\r
14 \r
15 #define ibl_BOOT_FORMAT_AUTO 0\r
16 #define ibl_BOOT_FORMAT_NAME 1\r
17 #define ibl_BOOT_FORMAT_BIS 2\r
18 #define ibl_BOOT_FORMAT_COFF 3\r
19 #define ibl_BOOT_FORMAT_ELF 4\r
20 #define ibl_BOOT_FORMAT_BBLOB 5\r
21 #define ibl_BOOT_FORMAT_BTBL 6\r
22 \r
23 #define ibl_MAIN_PLL 0\r
24 #define ibl_DDR_PLL 1\r
25 #define ibl_NET_PLL 2\r
26 \r
27 \r
28 menuitem "EVM c6472 IBL";\r
29 \r
30 hotmenu setConfig_c6472()\r
31 {\r
32 ibl.iblMagic = ibl_MAGIC_VALUE;\r
33 \r
34 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;\r
35 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;\r
36 ibl.pllConfig[ibl_MAIN_PLL].mult = 28;\r
37 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;\r
38 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 700;\r
39 \r
40 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
41 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
42 \r
43 /* The network PLL. The multipliers/dividers are fixed */\r
44 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
45 \r
46 /* EMIF configuration. The values are for DDR at 533 MHz */\r
47 ibl.ddrConfig.configDdr = TRUE;\r
48 \r
49 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538832; /* timing, 32bit wide */\r
50 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x0000073B; /* Refresh 533Mhz */ \r
51 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x47245BD2; /* Timing 1 */\r
52 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */\r
53 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */\r
54 \r
55 /* Ethernet configuration for port 0 */\r
56 ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;\r
57 ibl.ethConfig[0].port = 0;\r
58 \r
59 /* Bootp is disabled. The server and file name are provided here */\r
60 ibl.ethConfig[0].doBootp = FALSE;\r
61 ibl.ethConfig[0].useBootpServerIp = FALSE;\r
62 ibl.ethConfig[0].useBootpFileName = FALSE;\r
63 ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;\r
64 \r
65 \r
66 SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,113);\r
67 SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);\r
68 SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);\r
69 SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);\r
70 \r
71 /* Leave the hardware address as 0 so the e-fuse value will be used */\r
72 \r
73 \r
74 \r
75 \r
76 ibl.ethConfig[0].ethInfo.fileName[0] = 'c';\r
77 ibl.ethConfig[0].ethInfo.fileName[1] = '6';\r
78 ibl.ethConfig[0].ethInfo.fileName[2] = '4';\r
79 ibl.ethConfig[0].ethInfo.fileName[3] = '7';\r
80 ibl.ethConfig[0].ethInfo.fileName[4] = '2';\r
81 ibl.ethConfig[0].ethInfo.fileName[5] = '-';\r
82 ibl.ethConfig[0].ethInfo.fileName[6] = 'l';\r
83 ibl.ethConfig[0].ethInfo.fileName[7] = 'e';\r
84 ibl.ethConfig[0].ethInfo.fileName[8] = '.';\r
85 ibl.ethConfig[0].ethInfo.fileName[9] = 'b';\r
86 ibl.ethConfig[0].ethInfo.fileName[10] = 'i';\r
87 ibl.ethConfig[0].ethInfo.fileName[11] = 'n';\r
88 ibl.ethConfig[0].ethInfo.fileName[12] = '\0';\r
89 ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
90 ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
91 \r
92 /* Even though the entire range of DDR2 is chosen, the load will\r
93 * stop when the ftp reaches the end of the file */\r
94 ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */\r
95 ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */\r
96 ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */\r
97 \r
98 /* For port 1 use bootp */\r
99 /* Ethernet configuration for port 0 */\r
100 ibl.ethConfig[1].ethPriority = ibl_HIGHEST_PRIORITY + 1;\r
101 ibl.ethConfig[1].port = 1;\r
102 \r
103 /* Bootp is disabled. The server and file name are provided here */\r
104 ibl.ethConfig[1].doBootp = TRUE;\r
105 ibl.ethConfig[1].useBootpServerIp = TRUE;\r
106 ibl.ethConfig[1].useBootpFileName = TRUE;\r
107 ibl.ethConfig[1].bootFormat = ibl_BOOT_FORMAT_BBLOB;\r
108 \r
109 \r
110 /* SGMII not present */\r
111 ibl.sgmiiConfig[0].adviseAbility = 0;\r
112 ibl.sgmiiConfig[0].control = 0;\r
113 ibl.sgmiiConfig[0].txConfig = 0;\r
114 ibl.sgmiiConfig[0].rxConfig = 0;\r
115 ibl.sgmiiConfig[0].auxConfig = 0;\r
116 \r
117 ibl.sgmiiConfig[1].adviseAbility = 0;\r
118 ibl.sgmiiConfig[1].control = 0;\r
119 ibl.sgmiiConfig[1].txConfig = 0;\r
120 ibl.sgmiiConfig[1].rxConfig = 0;\r
121 ibl.sgmiiConfig[1].auxConfig = 0;\r
122 \r
123 \r
124 /* Leave the hardware address as 0 so the e-fuse value will be used */\r
125 ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;\r
126 ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;\r
127 ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;\r
128 ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;\r
129 ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;\r
130 ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;\r
131 \r
132 \r
133 /* Leave all remaining fields as 0 since bootp will fill them in */\r
134 \r
135 \r
136 /* Even though the entire range of DDR2 is chosen, the load will */\r
137 /* stop when the ftp reaches the end of the file */\r
138 \r
139 ibl.ethConfig[1].blob.startAddress = 0xe0000000; /* Base address of DDR2 */\r
140 ibl.ethConfig[1].blob.sizeBytes = 0x20000000; /* All of DDR2 */\r
141 ibl.ethConfig[1].blob.branchAddress = 0xe0000000; /* Base of DDR2 */\r
142 \r
143 \r
144 \r
145 /* MDIO configuration */\r
146 ibl.mdioConfig.nMdioOps = 8;\r
147 ibl.mdioConfig.mdioClkDiv = 0x20;\r
148 ibl.mdioConfig.interDelay = 1400; /* ~2ms at 700 MHz */\r
149 \r
150 ibl.mdioConfig.mdio[0] = (1 << 30) | (27 << 21) | (24 << 16) | 0x848b;\r
151 ibl.mdioConfig.mdio[1] = (1 << 30) | (20 << 21) | (24 << 16) | 0x0ce0;\r
152 ibl.mdioConfig.mdio[2] = (1 << 30) | (24 << 21) | (24 << 16) | 0x4101;\r
153 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (24 << 16) | 0x9140;\r
154 \r
155 ibl.mdioConfig.mdio[4] = (1 << 30) | (27 << 21) | (25 << 16) | 0x848b;\r
156 ibl.mdioConfig.mdio[5] = (1 << 30) | (20 << 21) | (25 << 16) | 0x0ce0;\r
157 ibl.mdioConfig.mdio[6] = (1 << 30) | (24 << 21) | (25 << 16) | 0x4101;\r
158 ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | (25 << 16) | 0x9140;\r
159 \r
160 \r
161 /* Nand boot is disabled */\r
162 ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
163 \r
164 }\r
165 \r
166 \r
167 menuitem "EVM c6474 Mez IBL";\r
168 \r
169 hotmenu setConfig_c6474()\r
170 {\r
171 ibl.iblMagic = ibl_MAGIC_VALUE;\r
172 \r
173 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;\r
174 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;\r
175 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;\r
176 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;\r
177 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;\r
178 \r
179 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
180 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
181 \r
182 /* The network PLL. The multipliers/dividers are fixed */\r
183 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
184 \r
185 /* EMIF configuration. The values are for DDR at 533 MHz */\r
186 ibl.ddrConfig.configDdr = TRUE;\r
187 \r
188 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */\r
189 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */ \r
190 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */\r
191 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */\r
192 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */\r
193 \r
194 \r
195 /* Ethernet configuration for port 0 */\r
196 ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;\r
197 ibl.ethConfig[0].port = 0;\r
198 \r
199 /* Bootp is disabled. The server and file name are provided here */\r
200 ibl.ethConfig[0].doBootp = FALSE;\r
201 ibl.ethConfig[0].useBootpServerIp = FALSE;\r
202 ibl.ethConfig[0].useBootpFileName = FALSE;\r
203 ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;\r
204 \r
205 SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,114);\r
206 SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);\r
207 SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);\r
208 SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);\r
209 \r
210 /* Set the hardware address as 0 so the e-fuse value will be used */\r
211 ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;\r
212 ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;\r
213 ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;\r
214 ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;\r
215 ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;\r
216 ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;\r
217 \r
218 \r
219 ibl.ethConfig[0].ethInfo.fileName[0] = 'c';\r
220 ibl.ethConfig[0].ethInfo.fileName[1] = '6';\r
221 ibl.ethConfig[0].ethInfo.fileName[2] = '4';\r
222 ibl.ethConfig[0].ethInfo.fileName[3] = '7';\r
223 ibl.ethConfig[0].ethInfo.fileName[4] = '4';\r
224 ibl.ethConfig[0].ethInfo.fileName[5] = '-';\r
225 ibl.ethConfig[0].ethInfo.fileName[6] = 'l';\r
226 ibl.ethConfig[0].ethInfo.fileName[7] = 'e';\r
227 ibl.ethConfig[0].ethInfo.fileName[8] = '.';\r
228 ibl.ethConfig[0].ethInfo.fileName[9] = 'b';\r
229 ibl.ethConfig[0].ethInfo.fileName[10] = 'i';\r
230 ibl.ethConfig[0].ethInfo.fileName[11] = 'n';\r
231 ibl.ethConfig[0].ethInfo.fileName[12] = '\0';\r
232 ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
233 ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
234 \r
235 \r
236 /* Even though the entire range of DDR2 is chosen, the load will\r
237 * stop when the ftp reaches the end of the file */\r
238 ibl.ethConfig[0].blob.startAddress = 0x80000000; /* Base address of DDR2 */\r
239 ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */\r
240 ibl.ethConfig[0].blob.branchAddress = 0x80000000; /* Base of DDR2 */\r
241 \r
242 /* There is no port 1 on the 6474 */\r
243 ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;\r
244 \r
245 /* SGMII is present */\r
246 ibl.sgmiiConfig[0].adviseAbility = 0x9801;\r
247 ibl.sgmiiConfig[0].control = 0x20;\r
248 ibl.sgmiiConfig[0].txConfig = 0x00000ea3;\r
249 ibl.sgmiiConfig[0].rxConfig = 0x00081023;\r
250 ibl.sgmiiConfig[0].auxConfig = 0x0000000b;\r
251 \r
252 /* MDIO configuration */\r
253 ibl.mdioConfig.nMdioOps = 8;\r
254 ibl.mdioConfig.mdioClkDiv = 0x26;\r
255 ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */\r
256 \r
257 ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;\r
258 ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;\r
259 ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;\r
260 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;\r
261 \r
262 ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;\r
263 ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
264 ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
265 ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;\r
266 \r
267 \r
268 /* Nand boot is disabled */\r
269 ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
270 \r
271 }\r
272 \r
273 \r
274 menuitem "EVM c6455 IBL";\r
275 \r
276 hotmenu setConfig_c6455()\r
277 {\r
278 ibl.iblMagic = ibl_MAGIC_VALUE;\r
279 \r
280 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;\r
281 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;\r
282 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;\r
283 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;\r
284 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;\r
285 \r
286 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
287 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
288 \r
289 /* The network PLL. The multipliers/dividers are fixed */\r
290 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
291 \r
292 /* EMIF configuration. The values are for DDR at 500 MHz */\r
293 ibl.ddrConfig.configDdr = TRUE;\r
294 \r
295 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538822; /* timing, 32bit wide */\r
296 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x000007a2; /* Refresh 500Mhz */ \r
297 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x3edb4b91; /* Timing 1 */\r
298 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00a2c722; /* Timing 2 */\r
299 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */\r
300 \r
301 /* Ethernet configuration for port 0 */\r
302 ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;\r
303 ibl.ethConfig[0].port = 0;\r
304 \r
305 /* Bootp is disabled. The server and file name are provided here */\r
306 ibl.ethConfig[0].doBootp = FALSE;\r
307 ibl.ethConfig[0].useBootpServerIp = FALSE;\r
308 ibl.ethConfig[0].useBootpFileName = FALSE;\r
309 ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;\r
310 \r
311 \r
312 SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,118);\r
313 SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);\r
314 SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);\r
315 SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);\r
316 \r
317 /* There is no e-fuse mac address. A value must be assigned\r
318 ibl.ethConfig[0].ethInfo.hwAddress[0] = 0x00;\r
319 ibl.ethConfig[0].ethInfo.hwAddress[1] = 0xe0;\r
320 ibl.ethConfig[0].ethInfo.hwAddress[2] = 0xa6;\r
321 ibl.ethConfig[0].ethInfo.hwAddress[3] = 0x66;\r
322 ibl.ethConfig[0].ethInfo.hwAddress[4] = 0x57;\r
323 ibl.ethConfig[0].ethInfo.hwAddress[5] = 0x19;\r
324 \r
325 \r
326 ibl.ethConfig[0].ethInfo.fileName[0] = 't';\r
327 ibl.ethConfig[0].ethInfo.fileName[1] = 'e';\r
328 ibl.ethConfig[0].ethInfo.fileName[2] = 's';\r
329 ibl.ethConfig[0].ethInfo.fileName[3] = 't';\r
330 ibl.ethConfig[0].ethInfo.fileName[4] = '.';\r
331 ibl.ethConfig[0].ethInfo.fileName[5] = 'b';\r
332 ibl.ethConfig[0].ethInfo.fileName[6] = 'l';\r
333 ibl.ethConfig[0].ethInfo.fileName[7] = 'o';\r
334 ibl.ethConfig[0].ethInfo.fileName[8] = 'b';\r
335 ibl.ethConfig[0].ethInfo.fileName[9] = '\0';\r
336 ibl.ethConfig[0].ethInfo.fileName[10] = '\0';\r
337 ibl.ethConfig[0].ethInfo.fileName[11] = '\0';\r
338 ibl.ethConfig[0].ethInfo.fileName[12] = '\0';\r
339 ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
340 ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
341 \r
342 \r
343 /* Even though the entire range of DDR2 is chosen, the load will\r
344 * stop when the ftp reaches the end of the file */\r
345 ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */\r
346 ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */\r
347 ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */\r
348 \r
349 /* There is no ethernet port 1 */\r
350 ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;\r
351 \r
352 \r
353 /* SGMII not present */\r
354 ibl.sgmiiConfig[0].adviseAbility = 0;\r
355 ibl.sgmiiConfig[0].control = 0;\r
356 ibl.sgmiiConfig[0].txConfig = 0;\r
357 ibl.sgmiiConfig[0].rxConfig = 0;\r
358 ibl.sgmiiConfig[0].auxConfig = 0;\r
359 \r
360 ibl.sgmiiConfig[1].adviseAbility = 0;\r
361 ibl.sgmiiConfig[1].control = 0;\r
362 ibl.sgmiiConfig[1].txConfig = 0;\r
363 ibl.sgmiiConfig[1].rxConfig = 0;\r
364 ibl.sgmiiConfig[1].auxConfig = 0;\r
365 \r
366 \r
367 \r
368 /* MDIO configuration */\r
369 ibl.mdioConfig.nMdioOps = 0;\r
370 ibl.mdioConfig.mdioClkDiv = 0x20;\r
371 ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */\r
372 \r
373 ibl.mdioConfig.mdio[0] = (1 << 30) | (14 << 21) | (0 << 16) | 0xd5d0;\r
374 \r
375 \r
376 /* Nand boot is disabled */\r
377 ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
378 \r
379 }\r
380 \r
381 \r