1 #define TRUE 1
2 #define FALSE 0
4 #define ibl_MAGIC_VALUE 0xCEC11EBB
6 #define ibl_HIGHEST_PRIORITY 1
7 #define ibl_LOWEST_PRIORITY 10
8 #define ibl_DEVICE_NOBOOT 20
10 #define ibl_PORT_SWITCH_ALL -2
12 #define SETIP(array,i0,i1,i2,i3) array[0]=(i0); \
13 array[1]=(i1); \
14 array[2]=(i2); \
15 array[3]=(i3)
17 #define ibl_BOOT_MODE_TFTP 10
18 #define ibl_BOOT_MODE_NAND 11
19 #define ibl_BOOT_MODE_NOR 12
20 #define ibl_BOOT_MODE_NONE 13
23 #define ibl_BOOT_FORMAT_AUTO 0
24 #define ibl_BOOT_FORMAT_NAME 1
25 #define ibl_BOOT_FORMAT_BIS 2
26 #define ibl_BOOT_FORMAT_COFF 3
27 #define ibl_BOOT_FORMAT_ELF 4
28 #define ibl_BOOT_FORMAT_BBLOB 5
29 #define ibl_BOOT_FORMAT_BTBL 6
31 #define ibl_PMEM_IF_GPIO 0
33 #define ibl_PMEM_IF_CHIPSEL_2 2 /* EMIF interface using chip select 2, no wait enabled */
34 #define ibl_PMEM_IF_CHIPSEL_3 3 /* EMIF interface using chip select 3, no wait enabled */
35 #define ibl_PMEM_IF_CHIPSEL_4 4 /* EMIF interface using chip select 4 */
36 #define ibl_PMEM_IF_CHIPSEL_5 5 /* EMIF interface using chip select 5 */
38 #define ibl_PMEM_IF_SPI 100 /* Interface through SPI */
41 #define ibl_MAIN_PLL 0
42 #define ibl_DDR_PLL 1
43 #define ibl_NET_PLL 2
45 #define ibl_EMIF4_ENABLE_sdRamConfig (1 << 0)
46 #define ibl_EMIF4_ENABLE_sdRamConfig2 (1 << 1)
47 #define ibl_EMIF4_ENABLE_sdRamRefreshCtl (1 << 2)
48 #define ibl_EMIF4_ENABLE_sdRamTiming1 (1 << 3)
49 #define ibl_EMIF4_ENABLE_sdRamTiming2 (1 << 4)
50 #define ibl_EMIF4_ENABLE_sdRamTiming3 (1 << 5)
51 #define ibl_EMIF4_ENABLE_lpDdrNvmTiming (1 << 6)
52 #define ibl_EMIF4_ENABLE_powerManageCtl (1 << 7)
53 #define ibl_EMIF4_ENABLE_iODFTTestLogic (1 << 8)
54 #define ibl_EMIF4_ENABLE_performCountCfg (1 << 9)
55 #define ibl_EMIF4_ENABLE_performCountMstRegSel (1 << 10)
56 #define ibl_EMIF4_ENABLE_readIdleCtl (1 << 11)
57 #define ibl_EMIF4_ENABLE_sysVbusmIntEnSet (1 << 12)
58 #define ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg (1 << 13)
59 #define ibl_EMIF4_ENABLE_tempAlterCfg (1 << 14)
60 #define ibl_EMIF4_ENABLE_ddrPhyCtl1 (1 << 15)
61 #define ibl_EMIF4_ENABLE_ddrPhyCtl2 (1 << 16)
62 #define ibl_EMIF4_ENABLE_priClassSvceMap (1 << 17)
63 #define ibl_EMIF4_ENABLE_mstId2ClsSvce1Map (1 << 18)
64 #define ibl_EMIF4_ENABLE_mstId2ClsSvce2Map (1 << 11)
65 #define ibl_EMIF4_ENABLE_eccCtl (1 << 19)
66 #define ibl_EMIF4_ENABLE_eccRange1 (1 << 20)
67 #define ibl_EMIF4_ENABLE_eccRange2 (1 << 21)
68 #define ibl_EMIF4_ENABLE_rdWrtExcThresh (1 << 22)
69 #define ibl_BOOT_EMIF4_ENABLE_ALL 0x007fffff
71 /* @} */
73 menuitem "EVM c6472 IBL";
75 hotmenu setConfig_c6472()
76 {
77 ibl.iblMagic = ibl_MAGIC_VALUE;
79 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
80 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
81 ibl.pllConfig[ibl_MAIN_PLL].mult = 28;
82 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
83 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 700;
85 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
86 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
88 /* The network PLL. The multipliers/dividers are fixed */
89 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
91 /* EMIF configuration. The values are for DDR at 533 MHz */
92 ibl.ddrConfig.configDdr = TRUE;
94 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538832; /* timing, 32bit wide */
95 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x0000073B; /* Refresh 533Mhz */
96 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x47245BD2; /* Timing 1 */
97 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */
98 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
100 /* Ethernet configuration for port 0 */
101 ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
102 ibl.ethConfig[0].port = 0;
104 /* Bootp is disabled. The server and file name are provided here */
105 ibl.ethConfig[0].doBootp = FALSE;
106 ibl.ethConfig[0].useBootpServerIp = FALSE;
107 ibl.ethConfig[0].useBootpFileName = FALSE;
108 ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
111 SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 10,218,109,21);
112 SETIP(ibl.ethConfig[0].ethInfo.serverIp, 10,218,109,196);
113 SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,2);
114 SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
116 /* Leave the hardware address as 0 so the e-fuse value will be used */
121 ibl.ethConfig[0].ethInfo.fileName[0] = 'c';
122 ibl.ethConfig[0].ethInfo.fileName[1] = '6';
123 ibl.ethConfig[0].ethInfo.fileName[2] = '4';
124 ibl.ethConfig[0].ethInfo.fileName[3] = '7';
125 ibl.ethConfig[0].ethInfo.fileName[4] = '2';
126 ibl.ethConfig[0].ethInfo.fileName[5] = '-';
127 ibl.ethConfig[0].ethInfo.fileName[6] = 'l';
128 ibl.ethConfig[0].ethInfo.fileName[7] = 'e';
129 ibl.ethConfig[0].ethInfo.fileName[8] = '.';
130 ibl.ethConfig[0].ethInfo.fileName[9] = 'b';
131 ibl.ethConfig[0].ethInfo.fileName[10] = 'i';
132 ibl.ethConfig[0].ethInfo.fileName[11] = 'n';
133 ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
134 ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
135 ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
137 /* Even though the entire range of DDR2 is chosen, the load will
138 * stop when the ftp reaches the end of the file */
139 ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
140 ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
141 ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
143 /* For port 1 use bootp */
144 /* Ethernet configuration for port 0 */
145 ibl.ethConfig[1].ethPriority = ibl_HIGHEST_PRIORITY + 1;
146 ibl.ethConfig[1].port = 1;
148 /* Bootp is disabled. The server and file name are provided here */
149 ibl.ethConfig[1].doBootp = TRUE;
150 ibl.ethConfig[1].useBootpServerIp = TRUE;
151 ibl.ethConfig[1].useBootpFileName = TRUE;
152 ibl.ethConfig[1].bootFormat = ibl_BOOT_FORMAT_BBLOB;
155 /* SGMII not present */
156 ibl.sgmiiConfig[0].adviseAbility = 0;
157 ibl.sgmiiConfig[0].control = 0;
158 ibl.sgmiiConfig[0].txConfig = 0;
159 ibl.sgmiiConfig[0].rxConfig = 0;
160 ibl.sgmiiConfig[0].auxConfig = 0;
162 ibl.sgmiiConfig[1].adviseAbility = 0;
163 ibl.sgmiiConfig[1].control = 0;
164 ibl.sgmiiConfig[1].txConfig = 0;
165 ibl.sgmiiConfig[1].rxConfig = 0;
166 ibl.sgmiiConfig[1].auxConfig = 0;
169 /* Leave the hardware address as 0 so the e-fuse value will be used */
170 ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
171 ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
172 ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
173 ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
174 ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
175 ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
178 /* Leave all remaining fields as 0 since bootp will fill them in */
181 /* Even though the entire range of DDR2 is chosen, the load will */
182 /* stop when the ftp reaches the end of the file */
184 ibl.ethConfig[1].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
185 ibl.ethConfig[1].blob.sizeBytes = 0x20000000; /* All of DDR2 */
186 ibl.ethConfig[1].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
190 /* MDIO configuration */
191 ibl.mdioConfig.nMdioOps = 8;
192 ibl.mdioConfig.mdioClkDiv = 0x20;
193 ibl.mdioConfig.interDelay = 1400; /* ~2ms at 700 MHz */
195 ibl.mdioConfig.mdio[0] = (1 << 30) | (27 << 21) | (24 << 16) | 0x848b;
196 ibl.mdioConfig.mdio[1] = (1 << 30) | (20 << 21) | (24 << 16) | 0x0ce0;
197 ibl.mdioConfig.mdio[2] = (1 << 30) | (24 << 21) | (24 << 16) | 0x4101;
198 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (24 << 16) | 0x9140;
200 ibl.mdioConfig.mdio[4] = (1 << 30) | (27 << 21) | (25 << 16) | 0x848b;
201 ibl.mdioConfig.mdio[5] = (1 << 30) | (20 << 21) | (25 << 16) | 0x0ce0;
202 ibl.mdioConfig.mdio[6] = (1 << 30) | (24 << 21) | (25 << 16) | 0x4101;
203 ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | (25 << 16) | 0x9140;
206 /* Nand boot is disabled */
207 ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
209 ibl.nandConfig.bootFormat = ibl_BOOT_FORMAT_AUTO;
211 ibl.nandConfig.nandInfo.busWidthBits = 8;
212 ibl.nandConfig.nandInfo.pageSizeBytes = 2048;
213 ibl.nandConfig.nandInfo.pageEccBytes = 64;
214 ibl.nandConfig.nandInfo.pagesPerBlock = 64;
215 ibl.nandConfig.nandInfo.totalBlocks = 1024;
217 ibl.nandConfig.nandInfo.addressBytes = 4;
218 ibl.nandConfig.nandInfo.lsbFirst = TRUE;
219 ibl.nandConfig.nandInfo.blockOffset = 22;
220 ibl.nandConfig.nandInfo.pageOffset = 16;
221 ibl.nandConfig.nandInfo.columnOffset = 0;
223 ibl.nandConfig.nandInfo.resetCommand = 0xff;
224 ibl.nandConfig.nandInfo.readCommandPre = 0;
225 ibl.nandConfig.nandInfo.readCommandPost = 0x30;
226 ibl.nandConfig.nandInfo.postCommand = TRUE;
228 }
231 menuitem "EVM c6474 Mez IBL";
233 hotmenu setConfig_c6474()
234 {
235 ibl.iblMagic = ibl_MAGIC_VALUE;
237 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
238 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
239 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
240 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
241 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
243 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
244 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
246 /* The network PLL. The multipliers/dividers are fixed */
247 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
249 /* EMIF configuration. The values are for DDR at 533 MHz */
250 ibl.ddrConfig.configDdr = TRUE;
252 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
253 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
254 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
255 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
256 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
259 /* Ethernet configuration for port 0 */
260 ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
261 ibl.ethConfig[0].port = 0;
263 /* Bootp is disabled. The server and file name are provided here */
264 ibl.ethConfig[0].doBootp = FALSE;
265 ibl.ethConfig[0].useBootpServerIp = FALSE;
266 ibl.ethConfig[0].useBootpFileName = FALSE;
267 ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
269 SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 10,218,109,35);
270 SETIP(ibl.ethConfig[0].ethInfo.serverIp, 10,218,109,196);
271 SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,1);
272 SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
274 /* Set the hardware address as 0 so the e-fuse value will be used */
275 ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
276 ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
277 ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
278 ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
279 ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
280 ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
283 ibl.ethConfig[0].ethInfo.fileName[0] = 'c';
284 ibl.ethConfig[0].ethInfo.fileName[1] = '6';
285 ibl.ethConfig[0].ethInfo.fileName[2] = '4';
286 ibl.ethConfig[0].ethInfo.fileName[3] = '7';
287 ibl.ethConfig[0].ethInfo.fileName[4] = '4';
288 ibl.ethConfig[0].ethInfo.fileName[5] = '-';
289 ibl.ethConfig[0].ethInfo.fileName[6] = 'l';
290 ibl.ethConfig[0].ethInfo.fileName[7] = 'e';
291 ibl.ethConfig[0].ethInfo.fileName[8] = '.';
292 ibl.ethConfig[0].ethInfo.fileName[9] = 'b';
293 ibl.ethConfig[0].ethInfo.fileName[10] = 'i';
294 ibl.ethConfig[0].ethInfo.fileName[11] = 'n';
295 ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
296 ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
297 ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
299 /* Even though the entire range of DDR2 is chosen, the load will
300 * stop when the ftp reaches the end of the file */
301 ibl.ethConfig[0].blob.startAddress = 0x80000000; /* Base address of DDR2 */
302 ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
303 ibl.ethConfig[0].blob.branchAddress = 0x80000000; /* Base of DDR2 */
305 /* There is no port 1 on the 6474 */
306 ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
308 /* SGMII is present */
309 ibl.sgmiiConfig[0].adviseAbility = 0x9801;
310 ibl.sgmiiConfig[0].control = 0x20;
311 ibl.sgmiiConfig[0].txConfig = 0x00000ea3;
312 ibl.sgmiiConfig[0].rxConfig = 0x00081023;
313 ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
315 /* MDIO configuration */
316 ibl.mdioConfig.nMdioOps = 8;
317 ibl.mdioConfig.mdioClkDiv = 0x26;
318 ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
320 ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
321 ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;
322 ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
323 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;
325 ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
326 ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
327 ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
328 ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
331 /* Nand boot is disabled */
332 ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
334 }
336 menuitem "EVM c6474 Lite EVM IBL";
338 hotmenu setConfig_c6474lite()
339 {
340 ibl.iblMagic = ibl_MAGIC_VALUE;
342 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
343 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
344 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
345 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
346 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
348 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
349 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
351 /* The network PLL. The multipliers/dividers are fixed */
352 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
354 /* EMIF configuration. The values are for DDR at 533 MHz */
355 ibl.ddrConfig.configDdr = TRUE;
357 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
358 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
359 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
360 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
361 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
364 /* Ethernet configuration for port 0 */
365 ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
366 ibl.ethConfig[0].port = 0;
368 /* Bootp is disabled. The server and file name are provided here */
369 ibl.ethConfig[0].doBootp = FALSE;
370 ibl.ethConfig[0].useBootpServerIp = FALSE;
371 ibl.ethConfig[0].useBootpFileName = FALSE;
372 ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
374 SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,114);
375 SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);
376 SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);
377 SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
379 /* Set the hardware address as 0 so the e-fuse value will be used */
380 ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
381 ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
382 ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
383 ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
384 ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
385 ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
388 ibl.ethConfig[0].ethInfo.fileName[0] = 'c';
389 ibl.ethConfig[0].ethInfo.fileName[1] = '6';
390 ibl.ethConfig[0].ethInfo.fileName[2] = '4';
391 ibl.ethConfig[0].ethInfo.fileName[3] = '7';
392 ibl.ethConfig[0].ethInfo.fileName[4] = '4';
393 ibl.ethConfig[0].ethInfo.fileName[5] = 'l';
394 ibl.ethConfig[0].ethInfo.fileName[6] = '-';
395 ibl.ethConfig[0].ethInfo.fileName[7] = 'l';
396 ibl.ethConfig[0].ethInfo.fileName[8] = 'e';
397 ibl.ethConfig[0].ethInfo.fileName[9] = '.';
398 ibl.ethConfig[0].ethInfo.fileName[10] = 'b';
399 ibl.ethConfig[0].ethInfo.fileName[11] = 'i';
400 ibl.ethConfig[0].ethInfo.fileName[12] = 'n';
401 ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
402 ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
405 /* Even though the entire range of DDR2 is chosen, the load will
406 * stop when the ftp reaches the end of the file */
407 ibl.ethConfig[0].blob.startAddress = 0x80000000; /* Base address of DDR2 */
408 ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
409 ibl.ethConfig[0].blob.branchAddress = 0x80000000; /* Base of DDR2 */
411 /* There is no port 1 on the 6474 Lite EVM */
412 ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
414 /* SGMII is present */
415 ibl.sgmiiConfig[0].adviseAbility = 0x9801;
416 ibl.sgmiiConfig[0].control = 0x20;
417 ibl.sgmiiConfig[0].txConfig = 0x00000e23;
418 ibl.sgmiiConfig[0].rxConfig = 0x00081023;
419 ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
421 /* MDIO configuration */
422 ibl.mdioConfig.nMdioOps = 5;
423 ibl.mdioConfig.mdioClkDiv = 0x20;
424 ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
426 ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
427 ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
428 ibl.mdioConfig.mdio[2] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
430 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
431 ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
434 /* This board has NAND. We will enable later */
435 ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
437 }
439 menuitem "EVM c6457 EVM IBL";
441 hotmenu setConfig_c6457()
442 {
443 ibl.iblMagic = ibl_MAGIC_VALUE;
445 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
446 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
447 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
448 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
449 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
451 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
452 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
454 /* The network PLL. The multipliers/dividers are fixed */
455 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
457 /* EMIF configuration */
458 ibl.ddrConfig.configDdr = TRUE;
460 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
461 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a0e; /* Refresh 333Mhz */
462 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x832474da; /* Timing 1 */
463 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0144c742; /* Timing 2 */
464 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x001800C6;
467 /* Ethernet configuration for port 0 */
468 ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
469 ibl.ethConfig[0].port = 0;
471 /* Bootp is disabled. The server and file name are provided here */
472 ibl.ethConfig[0].doBootp = FALSE;
473 ibl.ethConfig[0].useBootpServerIp = FALSE;
474 ibl.ethConfig[0].useBootpFileName = FALSE;
475 ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
477 SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,115);
478 SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);
479 SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);
480 SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
482 /* Set the hardware address as 0 so the e-fuse value will be used */
483 ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
484 ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
485 ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
486 ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
487 ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
488 ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
491 ibl.ethConfig[0].ethInfo.fileName[0] = 'c';
492 ibl.ethConfig[0].ethInfo.fileName[1] = '6';
493 ibl.ethConfig[0].ethInfo.fileName[2] = '4';
494 ibl.ethConfig[0].ethInfo.fileName[3] = '5';
495 ibl.ethConfig[0].ethInfo.fileName[4] = '7';
496 ibl.ethConfig[0].ethInfo.fileName[5] = '-';
497 ibl.ethConfig[0].ethInfo.fileName[6] = 'l';
498 ibl.ethConfig[0].ethInfo.fileName[7] = 'e';
499 ibl.ethConfig[0].ethInfo.fileName[8] = '.';
500 ibl.ethConfig[0].ethInfo.fileName[9] = 'b';
501 ibl.ethConfig[0].ethInfo.fileName[10] = 'i';
502 ibl.ethConfig[0].ethInfo.fileName[11] = 'n';
503 ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
504 ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
505 ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
508 /* Even though the entire range of DDR2 is chosen, the load will
509 * stop when the ftp reaches the end of the file */
510 ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
511 ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
512 ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
514 /* There is no port 1 on the 6457 Lite EVM */
515 ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
517 /* SGMII is present */
518 ibl.sgmiiConfig[0].adviseAbility = 0x9801;
519 ibl.sgmiiConfig[0].control = 0x20;
520 ibl.sgmiiConfig[0].txConfig = 0x00000e21;
521 ibl.sgmiiConfig[0].rxConfig = 0x00081021;
522 ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
524 /* MDIO configuration */
525 ibl.mdioConfig.nMdioOps = 5;
526 ibl.mdioConfig.mdioClkDiv = 0xa5;
527 ibl.mdioConfig.interDelay = 3000; /* ~2ms at 1000 MHz */
529 ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
530 ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
531 ibl.mdioConfig.mdio[2] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
532 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
533 ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x8140;
536 /* This board has NAND. We will enable later */
537 ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
539 }
541 menuitem "EVM c6455 IBL";
543 hotmenu setConfig_c6455()
544 {
545 ibl.iblMagic = ibl_MAGIC_VALUE;
547 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
548 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
549 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
550 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
551 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
553 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
554 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
556 /* The network PLL. The multipliers/dividers are fixed */
557 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
559 /* EMIF configuration. The values are for DDR at 500 MHz */
560 ibl.ddrConfig.configDdr = TRUE;
562 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538822; /* timing, 32bit wide */
563 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x000007a2; /* Refresh 500Mhz */
564 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x3edb4b91; /* Timing 1 */
565 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00a2c722; /* Timing 2 */
566 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */
568 /* Ethernet configuration for port 0 */
569 ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
570 ibl.ethConfig[0].port = 0;
572 /* Bootp is disabled. The server and file name are provided here */
573 ibl.ethConfig[0].doBootp = FALSE;
574 ibl.ethConfig[0].useBootpServerIp = FALSE;
575 ibl.ethConfig[0].useBootpFileName = FALSE;
576 ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
579 SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,118);
580 SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);
581 SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);
582 SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
584 /* There is no e-fuse mac address. A value must be assigned */
585 ibl.ethConfig[0].ethInfo.hwAddress[0] = 10;
586 ibl.ethConfig[0].ethInfo.hwAddress[1] = 224;
587 ibl.ethConfig[0].ethInfo.hwAddress[2] = 166;
588 ibl.ethConfig[0].ethInfo.hwAddress[3] = 102;
589 ibl.ethConfig[0].ethInfo.hwAddress[4] = 87;
590 ibl.ethConfig[0].ethInfo.hwAddress[5] = 25;
593 ibl.ethConfig[0].ethInfo.fileName[0] = 'c';
594 ibl.ethConfig[0].ethInfo.fileName[1] = '6';
595 ibl.ethConfig[0].ethInfo.fileName[2] = '4';
596 ibl.ethConfig[0].ethInfo.fileName[3] = '5';
597 ibl.ethConfig[0].ethInfo.fileName[4] = '5';
598 ibl.ethConfig[0].ethInfo.fileName[5] = '-';
599 ibl.ethConfig[0].ethInfo.fileName[6] = 'l';
600 ibl.ethConfig[0].ethInfo.fileName[7] = 'e';
601 ibl.ethConfig[0].ethInfo.fileName[8] = '.';
602 ibl.ethConfig[0].ethInfo.fileName[9] = 'b';
603 ibl.ethConfig[0].ethInfo.fileName[10] = 'i';
604 ibl.ethConfig[0].ethInfo.fileName[11] = 'n';
605 ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
606 ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
607 ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
610 /* Even though the entire range of DDR2 is chosen, the load will
611 * stop when the ftp reaches the end of the file */
612 ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
613 ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
614 ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
616 /* There is no ethernet port 1 */
617 ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
620 /* SGMII not present */
621 ibl.sgmiiConfig[0].adviseAbility = 0;
622 ibl.sgmiiConfig[0].control = 0;
623 ibl.sgmiiConfig[0].txConfig = 0;
624 ibl.sgmiiConfig[0].rxConfig = 0;
625 ibl.sgmiiConfig[0].auxConfig = 0;
627 ibl.sgmiiConfig[1].adviseAbility = 0;
628 ibl.sgmiiConfig[1].control = 0;
629 ibl.sgmiiConfig[1].txConfig = 0;
630 ibl.sgmiiConfig[1].rxConfig = 0;
631 ibl.sgmiiConfig[1].auxConfig = 0;
635 /* MDIO configuration */
636 ibl.mdioConfig.nMdioOps = 0;
637 ibl.mdioConfig.mdioClkDiv = 0x20;
638 ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
640 ibl.mdioConfig.mdio[0] = (1 << 30) | (14 << 21) | (0 << 16) | 0xd5d0;
643 /* Nand boot is disabled */
644 ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
646 }
649 menuitem "EVM c6678 IBL";
651 hotmenu setConfig_c6678()
652 {
653 ibl.iblMagic = ibl_MAGIC_VALUE;
655 /* Main PLL: 100 MHz reference, 1GHz output */
656 ibl.pllConfig[ibl_MAIN_PLL].doEnable = 1;
657 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
658 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
659 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 2;
660 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
662 /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
663 ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
664 ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
665 ibl.pllConfig[ibl_DDR_PLL].mult = 12;
666 ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
667 ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 400;
669 /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */
670 ibl.pllConfig[ibl_NET_PLL].doEnable = 1;
671 ibl.pllConfig[ibl_NET_PLL].prediv = 1;
672 ibl.pllConfig[ibl_NET_PLL].mult = 21;
673 ibl.pllConfig[ibl_NET_PLL].postdiv = 2;
674 ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz = 1050;
677 ibl.ddrConfig.configDdr = 1;
678 ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;
680 ibl.ddrConfig.uEmif.emif4p0.sdRamConfig = 0x63C452B2;
681 ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2 = 0;
682 ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl = 0x000030D4;
683 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1 = 0x0AAAE51B;
684 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2 = 0x2A2F7FDA;
685 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3 = 0x057F82B8;
686 ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming = 0;
687 ibl.ddrConfig.uEmif.emif4p0.powerManageCtl = 0;
688 ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic = 0;
689 ibl.ddrConfig.uEmif.emif4p0.performCountCfg = 0;
690 ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel = 0;
691 ibl.ddrConfig.uEmif.emif4p0.readIdleCtl = 0;
692 ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet = 0;
693 ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg = 0;
694 ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg = 0;
695 ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1 = 0x0010010d;
696 ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2 = 0;
697 ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap = 0;
698 ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map = 0;
699 ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map = 0;
700 ibl.ddrConfig.uEmif.emif4p0.eccCtl = 0;
701 ibl.ddrConfig.uEmif.emif4p0.eccRange1 = 0;
702 ibl.ddrConfig.uEmif.emif4p0.eccRange2 = 0;
703 ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh = 0;
706 ibl.sgmiiConfig[0].configure = 1;
707 ibl.sgmiiConfig[0].adviseAbility = 1;
708 ibl.sgmiiConfig[0].control = 1;
709 ibl.sgmiiConfig[0].txConfig = 0x108a1;
710 ibl.sgmiiConfig[0].rxConfig = 0x700621;
711 ibl.sgmiiConfig[0].auxConfig = 0x41;
713 ibl.sgmiiConfig[1].configure = 1;
714 ibl.sgmiiConfig[1].adviseAbility = 1;
715 ibl.sgmiiConfig[1].control = 1;
716 ibl.sgmiiConfig[1].txConfig = 0x108a1;
717 ibl.sgmiiConfig[1].rxConfig = 0x700621;
718 ibl.sgmiiConfig[1].auxConfig = 0x41;
720 ibl.mdioConfig.nMdioOps = 0;
722 ibl.spiConfig.addrWidth = 24;
723 ibl.spiConfig.nPins = 5;
724 ibl.spiConfig.mode = 1;
725 ibl.spiConfig.csel = 2;
726 ibl.spiConfig.c2tdelay = 1;
727 ibl.spiConfig.busFreqMHz = 20;
729 ibl.emifConfig[0].csSpace = 2;
730 ibl.emifConfig[0].busWidth = 8;
731 ibl.emifConfig[0].waitEnable = 0;
733 ibl.emifConfig[1].csSpace = 0;
734 ibl.emifConfig[1].busWidth = 0;
735 ibl.emifConfig[1].waitEnable = 0;
737 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NOR;
738 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
739 ibl.bootModes[0].port = 0;
741 ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
742 ibl.bootModes[0].u.norBoot.bootAddress = 0;
743 ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
744 ibl.bootModes[0].u.norBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
745 ibl.bootModes[0].u.norBoot.blob.sizeBytes = 0x80000; /* 512 KB */
746 ibl.bootModes[0].u.norBoot.blob.branchAddress = 0x80000000; /* Base address of DDR2 */
748 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_TFTP;
749 ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY+1;
750 ibl.bootModes[1].port = ibl_PORT_SWITCH_ALL;
752 ibl.bootModes[1].u.ethBoot.doBootp = FALSE;
753 ibl.bootModes[1].u.ethBoot.useBootpServerIp = FALSE;
754 ibl.bootModes[1].u.ethBoot.useBootpFileName = FALSE;
755 ibl.bootModes[1].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
758 SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.ipAddr, 192,168,1,100);
759 SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.serverIp, 192,168,1,101);
760 SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
761 SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.netmask, 255,255,255,0);
763 /* Use the e-fuse value */
764 ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[0] = 0;
765 ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[1] = 0;
766 ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[2] = 0;
767 ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[3] = 0;
768 ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[4] = 0;
769 ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[5] = 0;
772 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[0] = 'c';
773 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[1] = '6';
774 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[2] = '6';
775 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[3] = '7';
776 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[4] = '8';
777 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[5] = '-';
778 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[6] = 'l';
779 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[7] = 'e';
780 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[8] = '.';
781 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[9] = 'b';
782 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[10] = 'i';
783 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[11] = 'n';
784 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[12] = '\0';
785 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[13] = '\0';
786 ibl.bootModes[1].u.ethBoot.ethInfo.fileName[14] = '\0';
788 ibl.bootModes[1].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
789 ibl.bootModes[1].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
790 ibl.bootModes[1].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
792 ibl.chkSum = 0;
794 }
796 menuitem "EVM c6678 NAND Boot IBL";
798 hotmenu setConfig_c6678_nand()
799 {
800 /* Nand boot is higher priority */
801 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NAND;
802 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
803 ibl.bootModes[0].port = 0;
805 ibl.bootModes[0].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
806 ibl.bootModes[0].u.nandBoot.bootAddress = 0;
807 ibl.bootModes[0].u.nandBoot.interface = ibl_PMEM_IF_CHIPSEL_2;
808 ibl.bootModes[0].u.nandBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
809 ibl.bootModes[0].u.nandBoot.blob.sizeBytes = 0x80000; /* 512 KB */
810 ibl.bootModes[0].u.nandBoot.blob.branchAddress = 0x80000000; /* Base address of DDR2 */
812 ibl.bootModes[0].u.nandBoot.nandInfo.busWidthBits = 8;
813 ibl.bootModes[0].u.nandBoot.nandInfo.pageSizeBytes = 512;
814 ibl.bootModes[0].u.nandBoot.nandInfo.pageEccBytes = 16;
815 ibl.bootModes[0].u.nandBoot.nandInfo.pagesPerBlock = 32;
816 ibl.bootModes[0].u.nandBoot.nandInfo.totalBlocks = 4096;
818 ibl.bootModes[0].u.nandBoot.nandInfo.addressBytes = 4;
819 ibl.bootModes[0].u.nandBoot.nandInfo.lsbFirst = TRUE;
820 ibl.bootModes[0].u.nandBoot.nandInfo.blockOffset = 14;
821 ibl.bootModes[0].u.nandBoot.nandInfo.pageOffset = 9;
822 ibl.bootModes[0].u.nandBoot.nandInfo.columnOffset = 0;
824 ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
825 ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
826 ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
827 ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
828 ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[4] = 6;
829 ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[5] = 7;
831 ibl.bootModes[0].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
832 ibl.bootModes[0].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xffff;
834 ibl.bootModes[0].u.nandBoot.nandInfo.resetCommand = 0xff;
835 ibl.bootModes[0].u.nandBoot.nandInfo.readCommandPre = 0;
836 ibl.bootModes[0].u.nandBoot.nandInfo.readCommandPost = 0;
837 ibl.bootModes[0].u.nandBoot.nandInfo.postCommand = FALSE;
838 }