1 #define TRUE 1
2 #define FALSE 0
4 #define ibl_MAGIC_VALUE 0xCEC11EBC
6 #define ibl_HIGHEST_PRIORITY 1
7 #define ibl_LOWEST_PRIORITY 10
8 #define ibl_DEVICE_NOBOOT 20
10 #define ibl_PORT_SWITCH_ALL -2
12 #define SETIP(array,i0,i1,i2,i3) array[0]=(i0); \
13 array[1]=(i1); \
14 array[2]=(i2); \
15 array[3]=(i3)
17 #define ibl_BOOT_MODE_TFTP 10
18 #define ibl_BOOT_MODE_NAND 11
19 #define ibl_BOOT_MODE_NOR 12
20 #define ibl_BOOT_MODE_NONE 13
23 #define ibl_BOOT_FORMAT_AUTO 0
24 #define ibl_BOOT_FORMAT_NAME 1
25 #define ibl_BOOT_FORMAT_BIS 2
26 #define ibl_BOOT_FORMAT_COFF 3
27 #define ibl_BOOT_FORMAT_ELF 4
28 #define ibl_BOOT_FORMAT_BBLOB 5
29 #define ibl_BOOT_FORMAT_BTBL 6
31 #define ibl_PMEM_IF_GPIO 0
33 #define ibl_PMEM_IF_CHIPSEL_2 2 /* EMIF interface using chip select 2, no wait enabled */
34 #define ibl_PMEM_IF_CHIPSEL_3 3 /* EMIF interface using chip select 3, no wait enabled */
35 #define ibl_PMEM_IF_CHIPSEL_4 4 /* EMIF interface using chip select 4 */
36 #define ibl_PMEM_IF_CHIPSEL_5 5 /* EMIF interface using chip select 5 */
38 #define ibl_PMEM_IF_SPI 100 /* Interface through SPI */
41 #define ibl_MAIN_PLL 0
42 #define ibl_DDR_PLL 1
43 #define ibl_NET_PLL 2
45 #define ibl_EMIF4_ENABLE_sdRamConfig (1 << 0)
46 #define ibl_EMIF4_ENABLE_sdRamConfig2 (1 << 1)
47 #define ibl_EMIF4_ENABLE_sdRamRefreshCtl (1 << 2)
48 #define ibl_EMIF4_ENABLE_sdRamTiming1 (1 << 3)
49 #define ibl_EMIF4_ENABLE_sdRamTiming2 (1 << 4)
50 #define ibl_EMIF4_ENABLE_sdRamTiming3 (1 << 5)
51 #define ibl_EMIF4_ENABLE_lpDdrNvmTiming (1 << 6)
52 #define ibl_EMIF4_ENABLE_powerManageCtl (1 << 7)
53 #define ibl_EMIF4_ENABLE_iODFTTestLogic (1 << 8)
54 #define ibl_EMIF4_ENABLE_performCountCfg (1 << 9)
55 #define ibl_EMIF4_ENABLE_performCountMstRegSel (1 << 10)
56 #define ibl_EMIF4_ENABLE_readIdleCtl (1 << 11)
57 #define ibl_EMIF4_ENABLE_sysVbusmIntEnSet (1 << 12)
58 #define ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg (1 << 13)
59 #define ibl_EMIF4_ENABLE_tempAlterCfg (1 << 14)
60 #define ibl_EMIF4_ENABLE_ddrPhyCtl1 (1 << 15)
61 #define ibl_EMIF4_ENABLE_ddrPhyCtl2 (1 << 16)
62 #define ibl_EMIF4_ENABLE_priClassSvceMap (1 << 17)
63 #define ibl_EMIF4_ENABLE_mstId2ClsSvce1Map (1 << 18)
64 #define ibl_EMIF4_ENABLE_mstId2ClsSvce2Map (1 << 11)
65 #define ibl_EMIF4_ENABLE_eccCtl (1 << 19)
66 #define ibl_EMIF4_ENABLE_eccRange1 (1 << 20)
67 #define ibl_EMIF4_ENABLE_eccRange2 (1 << 21)
68 #define ibl_EMIF4_ENABLE_rdWrtExcThresh (1 << 22)
69 #define ibl_BOOT_EMIF4_ENABLE_ALL 0x007fffff
72 #define ibl_EVM_C6455L 0x10 /**< C6455 Low Cost EVM */
73 #define ibl_EVM_C6457L 0x20 /**< C6457 Low Cost EVM */
74 #define ibl_EVM_C6472L 0x30 /**< C6472 Low Cost EVM */
75 #define ibl_EVM_C6474L 0x40 /**< C6474 Low Cost EVM */
76 #define ibl_EVM_C6670L 0x50 /**< C6670 Low Cost EVM */
77 #define ibl_EVM_C6678L 0x60 /**< C6678 Low Cost EVM */
79 /* @} */
81 menuitem "EVM c6472 IBL";
83 hotmenu setConfig_c6472()
84 {
85 ibl.iblMagic = ibl_MAGIC_VALUE;
87 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
88 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
89 ibl.pllConfig[ibl_MAIN_PLL].mult = 28;
90 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
91 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 700;
93 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
94 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
96 /* The network PLL. The multipliers/dividers are fixed */
97 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
99 /* EMIF configuration. The values are for DDR at 533 MHz */
100 ibl.ddrConfig.configDdr = TRUE;
102 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538832; /* timing, 32bit wide */
103 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x0000073B; /* Refresh 533Mhz */
104 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x47245BD2; /* Timing 1 */
105 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */
106 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
108 /* SGMII not present */
109 ibl.sgmiiConfig[0].configure = FALSE;
110 ibl.sgmiiConfig[1].configure = FALSE;
112 /* MDIO configuration */
113 ibl.mdioConfig.nMdioOps = 8;
114 ibl.mdioConfig.mdioClkDiv = 0x20;
115 ibl.mdioConfig.interDelay = 1400; /* ~2ms at 700 MHz */
117 ibl.mdioConfig.mdio[0] = (1 << 30) | (27 << 21) | (24 << 16) | 0x848b;
118 ibl.mdioConfig.mdio[1] = (1 << 30) | (20 << 21) | (24 << 16) | 0x0ce0;
119 ibl.mdioConfig.mdio[2] = (1 << 30) | (24 << 21) | (24 << 16) | 0x4101;
120 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (24 << 16) | 0x9140;
122 ibl.mdioConfig.mdio[4] = (1 << 30) | (27 << 21) | (25 << 16) | 0x848b;
123 ibl.mdioConfig.mdio[5] = (1 << 30) | (20 << 21) | (25 << 16) | 0x0ce0;
124 ibl.mdioConfig.mdio[6] = (1 << 30) | (24 << 21) | (25 << 16) | 0x4101;
125 ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | (25 << 16) | 0x9140;
127 /* spiConfig and emifConfig not needed */
129 /* Ethernet configuration for Boot mode 0 */
130 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
131 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
132 ibl.bootModes[0].port = 0;
134 /* Bootp is disabled. The server and file name are provided here */
135 ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
136 ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
137 ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
138 ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
140 /* Even though the entire range of DDR2 is chosen, the load will
141 * stop when the ftp reaches the end of the file */
142 ibl.bootModes[0].u.ethBoot.blob.startAddress = 0xe0000000; /* Base address of DDR2 */
143 ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
144 ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
146 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,103,200);
147 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,103,58);
148 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,103,1);
149 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
151 /* Leave the hardware address as 0 so the e-fuse value will be used */
152 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
153 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
154 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
155 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
156 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
157 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
159 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
160 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
161 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
162 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '7';
163 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '2';
164 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
165 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
166 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
167 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
168 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
169 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
170 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
171 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
172 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
173 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
175 /* Alternative bootMode not configured for now */
176 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
178 ibl.chkSum = 0;
179 }
182 menuitem "EVM c6474 Mez IBL";
184 hotmenu setConfig_c6474()
185 {
186 ibl.iblMagic = ibl_MAGIC_VALUE;
188 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
189 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
190 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
191 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
192 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
194 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
195 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
197 /* The network PLL. The multipliers/dividers are fixed */
198 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
200 /* EMIF configuration. The values are for DDR at 533 MHz */
201 ibl.ddrConfig.configDdr = TRUE;
203 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
204 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
205 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
206 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
207 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
209 /* SGMII 0 is present */
210 ibl.sgmiiConfig[0].configure = TRUE;
211 ibl.sgmiiConfig[0].adviseAbility = 0x9801;
212 ibl.sgmiiConfig[0].control = 0x20;
213 ibl.sgmiiConfig[0].txConfig = 0x00000ea3;
214 ibl.sgmiiConfig[0].rxConfig = 0x00081023;
215 ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
217 /* There is no port 1 on the 6474 */
218 ibl.sgmiiConfig[1].configure = FALSE;
220 /* MDIO configuration */
221 ibl.mdioConfig.nMdioOps = 8;
222 ibl.mdioConfig.mdioClkDiv = 0x26;
223 ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
225 ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
226 ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
227 ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (13 << 16) | 0x0047;
228 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
230 ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (13 << 16) | 0x8140;
231 ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
232 ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
233 ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
235 /* spiConfig and emifConfig not needed */
237 /* Ethernet configuration for Boot mode 0 */
238 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
239 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
240 ibl.bootModes[0].port = 0;
242 /* Bootp is disabled. The server and file name are provided here */
243 ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
244 ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
245 ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
246 ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
248 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 10,218,109,35);
249 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 10,218,109,196);
250 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 10,218,109,1);
251 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
253 /* Set the hardware address as 0 so the e-fuse value will be used */
254 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
255 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
256 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
257 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
258 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
259 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
261 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
262 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
263 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
264 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '7';
265 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '4';
266 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
267 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
268 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
269 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
270 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
271 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
272 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
273 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
274 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
275 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
277 /* Even though the entire range of DDR2 is chosen, the load will
278 * stop when the ftp reaches the end of the file */
279 ibl.bootModes[0].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
280 ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
281 ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
283 /* Alternative bootMode not configured for now */
284 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
286 ibl.chkSum = 0;
287 }
289 menuitem "EVM c6474 Lite EVM IBL";
291 hotmenu setConfig_c6474lite()
292 {
293 ibl.iblMagic = ibl_MAGIC_VALUE;
295 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
296 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
297 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
298 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
299 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
301 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
302 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
304 /* The network PLL. The multipliers/dividers are fixed */
305 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
307 /* EMIF configuration. The values are for DDR at 533 MHz */
308 ibl.ddrConfig.configDdr = TRUE;
310 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
311 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
312 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
313 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
314 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
316 /* SGMII 0 is present */
317 ibl.sgmiiConfig[0].configure = TRUE;
318 ibl.sgmiiConfig[0].adviseAbility = 0x9801;
319 ibl.sgmiiConfig[0].control = 0x20;
320 ibl.sgmiiConfig[0].txConfig = 0x00000e23;
321 ibl.sgmiiConfig[0].rxConfig = 0x00081023;
322 ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
324 /* There is no port 1 on the 6474 */
325 ibl.sgmiiConfig[1].configure = FALSE;
327 /* MDIO configuration */
328 ibl.mdioConfig.nMdioOps = 5;
329 ibl.mdioConfig.mdioClkDiv = 0x20;
330 ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
332 ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
333 ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
334 ibl.mdioConfig.mdio[2] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
336 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
337 ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
339 /* spiConfig and emifConfig not needed */
341 /* Ethernet configuration for Boot mode 0 */
342 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
343 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
344 ibl.bootModes[0].port = 0;
346 /* Bootp is disabled. The server and file name are provided here */
347 ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
348 ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
349 ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
350 ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
352 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,114);
353 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,100,25);
354 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,100,2);
355 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
357 /* Set the hardware address as 0 so the e-fuse value will be used */
358 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
359 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
360 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
361 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
362 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
363 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
366 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
367 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
368 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
369 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '7';
370 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '4';
371 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = 'l';
372 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = '-';
373 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'l';
374 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = 'e';
375 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = '.';
376 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'b';
377 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'i';
378 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = 'n';
379 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
380 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
383 /* Even though the entire range of DDR2 is chosen, the load will
384 * stop when the ftp reaches the end of the file */
385 ibl.bootModes[0].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
386 ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
387 ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
389 /* Alternative bootMode not configured for now */
390 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
392 ibl.chkSum = 0;
393 }
395 menuitem "EVM c6457 EVM IBL";
397 hotmenu setConfig_c6457()
398 {
399 ibl.iblMagic = ibl_MAGIC_VALUE;
401 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
402 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
403 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
404 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
405 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
407 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
408 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
410 /* The network PLL. The multipliers/dividers are fixed */
411 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
413 /* EMIF configuration */
414 ibl.ddrConfig.configDdr = TRUE;
416 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
417 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a0e; /* Refresh 333Mhz */
418 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x832474da; /* Timing 1 */
419 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0144c742; /* Timing 2 */
420 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x001800C6;
422 /* SGMII 0 is present */
423 ibl.sgmiiConfig[0].configure = TRUE;
424 ibl.sgmiiConfig[0].adviseAbility = 0x9801;
425 ibl.sgmiiConfig[0].control = 0x20;
426 ibl.sgmiiConfig[0].txConfig = 0x00000e21;
427 ibl.sgmiiConfig[0].rxConfig = 0x00081021;
428 ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
430 /* There is no port 1 on the 6457 */
431 ibl.sgmiiConfig[1].configure = FALSE;
433 /* MDIO configuration */
434 ibl.mdioConfig.nMdioOps = 5;
435 ibl.mdioConfig.mdioClkDiv = 0xa5;
436 ibl.mdioConfig.interDelay = 3000; /* ~2ms at 1000 MHz */
438 ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
439 ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
440 ibl.mdioConfig.mdio[2] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
441 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
442 ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x8140;
444 /* spiConfig and emifConfig not needed */
446 /* Ethernet configuration for Boot mode 0 */
447 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
448 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
449 ibl.bootModes[0].port = 0;
451 /* Bootp is disabled. The server and file name are provided here */
452 ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
453 ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
454 ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
455 ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
457 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,115);
458 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,100,25);
459 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,100,2);
460 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
462 /* Set the hardware address as 0 so the e-fuse value will be used */
463 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
464 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
465 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
466 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
467 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
468 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
470 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
471 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
472 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
473 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '5';
474 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '7';
475 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
476 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
477 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
478 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
479 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
480 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
481 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
482 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
483 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
484 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
487 /* Even though the entire range of DDR2 is chosen, the load will
488 * stop when the ftp reaches the end of the file */
489 ibl.bootModes[0].u.ethBoot.blob.startAddress = 0xe0000000; /* Base address of DDR2 */
490 ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
491 ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
493 /* Alternative bootMode not configured for now */
494 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
496 ibl.chkSum = 0;
497 }
499 menuitem "EVM c6455 IBL";
501 hotmenu setConfig_c6455()
502 {
503 ibl.iblMagic = ibl_MAGIC_VALUE;
505 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
506 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
507 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
508 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
509 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
511 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
512 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
514 /* The network PLL. The multipliers/dividers are fixed */
515 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
517 /* EMIF configuration. The values are for DDR at 500 MHz */
518 ibl.ddrConfig.configDdr = TRUE;
520 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538822; /* timing, 32bit wide */
521 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x000007a2; /* Refresh 500Mhz */
522 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x3edb4b91; /* Timing 1 */
523 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00a2c722; /* Timing 2 */
524 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */
526 /* SGMII not present */
527 ibl.sgmiiConfig[0].configure = FALSE;
528 ibl.sgmiiConfig[1].configure = FALSE;
530 /* MDIO configuration */
531 ibl.mdioConfig.nMdioOps = 0;
532 ibl.mdioConfig.mdioClkDiv = 0x20;
533 ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
535 ibl.mdioConfig.mdio[0] = (1 << 30) | (14 << 21) | (0 << 16) | 0xd5d0;
537 /* spiConfig and emifConfig not needed */
539 /* Ethernet configuration for Boot mode 0 */
540 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
541 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
542 ibl.bootModes[0].port = 0;
544 /* Bootp is disabled. The server and file name are provided here */
545 ibl.bootModes[0].u.ethBoot.doBootp = FALSE;
546 ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;
547 ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;
548 ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
550 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,100,118);
551 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,100,25);
552 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,100,2);
553 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
555 /* There is no e-fuse mac address. A value must be assigned */
556 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 10;
557 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 224;
558 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 166;
559 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 102;
560 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 87;
561 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 25;
564 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
565 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
566 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
567 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '5';
568 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '5';
569 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
570 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
571 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
572 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
573 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
574 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
575 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
576 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
577 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
578 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
580 /* Even though the entire range of DDR2 is chosen, the load will
581 * stop when the ftp reaches the end of the file */
582 ibl.bootModes[0].u.ethBoot.blob.startAddress = 0xe0000000; /* Base address of DDR2 */
583 ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
584 ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
586 /* Alternative bootMode not configured for now */
587 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
589 ibl.chkSum = 0;
590 }
593 menuitem "EVM c6678 IBL";
595 hotmenu setConfig_c6678_main()
596 {
597 ibl.iblMagic = ibl_MAGIC_VALUE;
598 ibl.iblEvmType = ibl_EVM_C6678L;
600 /* Main PLL: 100 MHz reference, 1GHz output */
601 ibl.pllConfig[ibl_MAIN_PLL].doEnable = 1;
602 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
603 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
604 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 2;
605 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
607 /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
608 ibl.pllConfig[ibl_DDR_PLL].doEnable = 0;
609 ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
610 ibl.pllConfig[ibl_DDR_PLL].mult = 12;
611 ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
612 ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 400;
614 /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */
615 ibl.pllConfig[ibl_NET_PLL].doEnable = 1;
616 ibl.pllConfig[ibl_NET_PLL].prediv = 1;
617 ibl.pllConfig[ibl_NET_PLL].mult = 21;
618 ibl.pllConfig[ibl_NET_PLL].postdiv = 2;
619 ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz = 1050;
622 ibl.ddrConfig.configDdr = 1;
623 ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;
625 ibl.ddrConfig.uEmif.emif4p0.sdRamConfig = 0x63C452B2;
626 ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2 = 0;
627 ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl = 0x000030D4;
628 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1 = 0x0AAAE51B;
629 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2 = 0x2A2F7FDA;
630 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3 = 0x057F82B8;
631 ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming = 0;
632 ibl.ddrConfig.uEmif.emif4p0.powerManageCtl = 0;
633 ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic = 0;
634 ibl.ddrConfig.uEmif.emif4p0.performCountCfg = 0;
635 ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel = 0;
636 ibl.ddrConfig.uEmif.emif4p0.readIdleCtl = 0;
637 ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet = 0;
638 ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg = 0;
639 ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg = 0;
640 ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1 = 0x0010010d;
641 ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2 = 0;
642 ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap = 0;
643 ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map = 0;
644 ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map = 0;
645 ibl.ddrConfig.uEmif.emif4p0.eccCtl = 0;
646 ibl.ddrConfig.uEmif.emif4p0.eccRange1 = 0;
647 ibl.ddrConfig.uEmif.emif4p0.eccRange2 = 0;
648 ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh = 0;
651 ibl.sgmiiConfig[0].configure = 1;
652 ibl.sgmiiConfig[0].adviseAbility = 1;
653 ibl.sgmiiConfig[0].control = 1;
654 ibl.sgmiiConfig[0].txConfig = 0x108a1;
655 ibl.sgmiiConfig[0].rxConfig = 0x700621;
656 ibl.sgmiiConfig[0].auxConfig = 0x41;
658 ibl.sgmiiConfig[1].configure = 1;
659 ibl.sgmiiConfig[1].adviseAbility = 1;
660 ibl.sgmiiConfig[1].control = 1;
661 ibl.sgmiiConfig[1].txConfig = 0x108a1;
662 ibl.sgmiiConfig[1].rxConfig = 0x700621;
663 ibl.sgmiiConfig[1].auxConfig = 0x41;
665 ibl.mdioConfig.nMdioOps = 0;
667 ibl.spiConfig.addrWidth = 24;
668 ibl.spiConfig.nPins = 5;
669 ibl.spiConfig.mode = 1;
670 ibl.spiConfig.csel = 2;
671 ibl.spiConfig.c2tdelay = 1;
672 ibl.spiConfig.busFreqMHz = 20;
674 ibl.emifConfig[0].csSpace = 2;
675 ibl.emifConfig[0].busWidth = 8;
676 ibl.emifConfig[0].waitEnable = 0;
678 ibl.emifConfig[1].csSpace = 0;
679 ibl.emifConfig[1].busWidth = 0;
680 ibl.emifConfig[1].waitEnable = 0;
682 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NOR;
683 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
684 ibl.bootModes[0].port = 0;
686 ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
687 ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0;
688 ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0;
689 ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
690 ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Base address of DDR2 */
691 ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* 10 MB */
692 ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Base address of DDR2 */
693 ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Base address of DDR2 */
694 ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* 10 MB */
695 ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Base address of DDR2 */
697 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
698 ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
699 ibl.bootModes[1].port = 0;
701 ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
702 ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x4000;
703 ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x4000;
704 ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_CHIPSEL_2;
706 ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Base address of DDR2 */
707 ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* 10 MB */
708 ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Base address of DDR2 */
709 ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Base address of DDR2 */
710 ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* 10 MB */
711 ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Base address of DDR2 */
713 ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
714 ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 512;
715 ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 16;
716 ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 32;
717 ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 4096;
719 ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
720 ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
721 ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 14;
722 ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 9;
723 ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
725 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
726 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
727 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
728 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
729 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
730 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
731 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
732 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
733 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
734 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
736 ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
737 ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
739 ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
740 ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
741 ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
742 ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
744 ibl.bootModes[2].bootMode = ibl_BOOT_MODE_TFTP;
745 ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
746 ibl.bootModes[2].port = ibl_PORT_SWITCH_ALL;
748 ibl.bootModes[2].u.ethBoot.doBootp = FALSE;
749 ibl.bootModes[2].u.ethBoot.useBootpServerIp = FALSE;
750 ibl.bootModes[2].u.ethBoot.useBootpFileName = FALSE;
751 ibl.bootModes[2].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
754 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr, 192,168,2,100);
755 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp, 192,168,2,101);
756 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 192,168,2,1);
757 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.netmask, 255,255,255,0);
759 /* Use the e-fuse value */
760 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[0] = 0;
761 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[1] = 0;
762 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[2] = 0;
763 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[3] = 0;
764 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[4] = 0;
765 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[5] = 0;
768 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[0] = 'a';
769 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[1] = 'p';
770 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[2] = 'p';
771 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[3] = '.';
772 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[4] = 'o';
773 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[5] = 'u';
774 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[6] = 't';
775 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[7] = '\0';
776 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[8] = '\0';
777 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[9] = '\0';
778 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[10] = '\0';
779 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[11] = '\0';
780 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[12] = '\0';
781 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
782 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
784 ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
785 ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0xA00000; /* 10 MB */
786 ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
788 ibl.chkSum = 0;
789 }
791 menuitem "EVM c6670 IBL";
793 hotmenu setConfig_c6670_main()
794 {
795 ibl.iblMagic = ibl_MAGIC_VALUE;
796 ibl.iblEvmType = ibl_EVM_C6670L;
798 /* Main PLL: 122.88 MHz reference, 983 MHz output */
799 ibl.pllConfig[ibl_MAIN_PLL].doEnable = 1;
800 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
801 ibl.pllConfig[ibl_MAIN_PLL].mult = 16;
802 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 2;
803 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
805 /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
806 ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
807 ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
808 ibl.pllConfig[ibl_DDR_PLL].mult = 12;
809 ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
810 ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 400;
812 /* Net PLL: 122.88 MHz reference, 1044 MHz output (followed by a built in divide by 3 to give 348 MHz to PA) */
813 ibl.pllConfig[ibl_NET_PLL].doEnable = 1;
814 ibl.pllConfig[ibl_NET_PLL].prediv = 1;
815 ibl.pllConfig[ibl_NET_PLL].mult = 17;
816 ibl.pllConfig[ibl_NET_PLL].postdiv = 2;
817 ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz = 1044;
820 ibl.ddrConfig.configDdr = 1;
821 ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;
823 ibl.ddrConfig.uEmif.emif4p0.sdRamConfig = 0x63C452B2;
824 ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2 = 0;
825 ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl = 0x000030D4;
826 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1 = 0x0AAAE51B;
827 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2 = 0x2A2F7FDA;
828 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3 = 0x057F82B8;
829 ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming = 0;
830 ibl.ddrConfig.uEmif.emif4p0.powerManageCtl = 0;
831 ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic = 0;
832 ibl.ddrConfig.uEmif.emif4p0.performCountCfg = 0;
833 ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel = 0;
834 ibl.ddrConfig.uEmif.emif4p0.readIdleCtl = 0;
835 ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet = 0;
836 ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg = 0;
837 ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg = 0;
838 ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1 = 0x0010010d;
839 ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2 = 0;
840 ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap = 0;
841 ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map = 0;
842 ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map = 0;
843 ibl.ddrConfig.uEmif.emif4p0.eccCtl = 0;
844 ibl.ddrConfig.uEmif.emif4p0.eccRange1 = 0;
845 ibl.ddrConfig.uEmif.emif4p0.eccRange2 = 0;
846 ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh = 0;
849 ibl.sgmiiConfig[0].configure = 1;
850 ibl.sgmiiConfig[0].adviseAbility = 1;
851 ibl.sgmiiConfig[0].control = 1;
852 ibl.sgmiiConfig[0].txConfig = 0x108a1;
853 ibl.sgmiiConfig[0].rxConfig = 0x700621;
854 ibl.sgmiiConfig[0].auxConfig = 0x41;
856 ibl.sgmiiConfig[1].configure = 1;
857 ibl.sgmiiConfig[1].adviseAbility = 1;
858 ibl.sgmiiConfig[1].control = 1;
859 ibl.sgmiiConfig[1].txConfig = 0x108a1;
860 ibl.sgmiiConfig[1].rxConfig = 0x700621;
861 ibl.sgmiiConfig[1].auxConfig = 0x51;
863 ibl.mdioConfig.nMdioOps = 0;
865 ibl.spiConfig.addrWidth = 24;
866 ibl.spiConfig.nPins = 5;
867 ibl.spiConfig.mode = 1;
868 ibl.spiConfig.csel = 2;
869 ibl.spiConfig.c2tdelay = 1;
870 ibl.spiConfig.busFreqMHz = 20;
872 ibl.emifConfig[0].csSpace = 2;
873 ibl.emifConfig[0].busWidth = 8;
874 ibl.emifConfig[0].waitEnable = 0;
876 ibl.emifConfig[1].csSpace = 0;
877 ibl.emifConfig[1].busWidth = 0;
878 ibl.emifConfig[1].waitEnable = 0;
880 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NOR;
881 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
882 ibl.bootModes[0].port = 0;
884 ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
885 ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0;
886 ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0;
887 ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
888 ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Base address of DDR2 */
889 ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* 10 MB */
890 ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Base address of DDR2 */
891 ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Base address of DDR2 */
892 ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* 10 MB */
893 ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Base address of DDR2 */
895 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
896 ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
897 ibl.bootModes[1].port = 0;
899 ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
900 ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x4000;
901 ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x4000;
902 ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
904 ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Base address of DDR2 */
905 ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* 10 MB */
906 ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Base address of DDR2 */
907 ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Base address of DDR2 */
908 ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* 10 MB */
909 ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Base address of DDR2 */
911 ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
912 ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 512;
913 ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 16;
914 ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 32;
915 ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 4096;
917 ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
918 ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
919 ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 14;
920 ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 9;
921 ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
923 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
924 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
925 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
926 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
927 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
928 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
929 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
930 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
931 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
932 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
934 ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
935 ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
937 ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
938 ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
939 ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
940 ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
942 ibl.bootModes[2].bootMode = ibl_BOOT_MODE_TFTP;
943 ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
944 ibl.bootModes[2].port = ibl_PORT_SWITCH_ALL;
946 ibl.bootModes[2].u.ethBoot.doBootp = FALSE;
947 ibl.bootModes[2].u.ethBoot.useBootpServerIp = FALSE;
948 ibl.bootModes[2].u.ethBoot.useBootpFileName = FALSE;
949 ibl.bootModes[2].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
952 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr, 192,168,2,100);
953 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp, 192,168,2,101);
954 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 192,168,2,1);
955 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.netmask, 255,255,255,0);
957 /* Use the e-fuse value */
958 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[0] = 0;
959 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[1] = 0;
960 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[2] = 0;
961 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[3] = 0;
962 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[4] = 0;
963 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[5] = 0;
966 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[0] = 'a';
967 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[1] = 'p';
968 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[2] = 'p';
969 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[3] = '.';
970 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[4] = 'o';
971 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[5] = 'u';
972 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[6] = 't';
973 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[7] = '\0';
974 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[8] = '\0';
975 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[9] = '\0';
976 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[10] = '\0';
977 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[11] = '\0';
978 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[12] = '\0';
979 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
980 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
982 ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
983 ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0xA00000; /* 10 MB */
984 ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
986 ibl.chkSum = 0;
987 }