5e63eb66339b37efb87a2ed493ba96a5603e5f7f
1 /************************************************************************************
2 * FILE PURPOSE: C6455 Device Specific functions used in the 1st load stage
3 ************************************************************************************
4 * FILE NAME: c6455init.c
5 *
6 * DESCRIPTION: Implements the device specific functions for the IBL
7 *
8 * @file c6455.c
9 *
10 * @brief
11 * This file implements the device specific functions for the IBL
12 *
13 ************************************************************************************/
14 #include "device.h"
16 ibl_t c6455_ibl_config(void)
17 {
18 ibl_t ibl;
20 ibl.iblMagic = ibl_MAGIC_VALUE;
21 ibl.iblEvmType = ibl_EVM_C6455L;
23 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
24 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
25 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
26 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
27 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
29 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
30 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
32 /* The network PLL. The multipliers/dividers are fixed */
33 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
35 /* EMIF configuration. The values are for DDR at 500 MHz */
36 ibl.ddrConfig.configDdr = TRUE;
38 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538822; /* timing, 32bit wide */
39 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x000007a2; /* Refresh 500Mhz */
40 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x3edb4b91; /* Timing 1 */
41 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00a2c722; /* Timing 2 */
42 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */
44 /* SGMII not present */
45 ibl.sgmiiConfig[0].configure = FALSE;
46 ibl.sgmiiConfig[1].configure = FALSE;
48 /* MDIO configuration */
49 ibl.mdioConfig.nMdioOps = 0;
50 ibl.mdioConfig.mdioClkDiv = 0x20;
51 ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
53 ibl.mdioConfig.mdio[0] = (1 << 30) | (14 << 21) | (0 << 16) | 0xd5d0;
55 /* spiConfig and emifConfig not needed */
57 /* Ethernet configuration for Boot mode 0 */
58 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
59 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
60 ibl.bootModes[0].port = 0;
62 /* Bootp is disabled. The server and file name are provided here */
63 ibl.bootModes[0].u.ethBoot.doBootp = TRUE;
64 ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
65 ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
66 ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
68 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 192,168,1,3);
69 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 192,168,1,2);
70 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
71 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
73 /* There is no e-fuse mac address. A value must be assigned */
74 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 10;
75 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 224;
76 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 166;
77 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 102;
78 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 87;
79 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 25;
82 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
83 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
84 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
85 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '5';
86 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '5';
87 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
88 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
89 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
90 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
91 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
92 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
93 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
94 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
95 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
96 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
98 /* Even though the entire range of DDR2 is chosen, the load will
99 * stop when the ftp reaches the end of the file */
100 ibl.bootModes[0].u.ethBoot.blob.startAddress = 0xe0000000; /* Base address of DDR2 */
101 ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
102 ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
104 /* Alternative bootMode not configured for now */
105 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
107 ibl.chkSum = 0;
109 return(ibl);
110 }
112 ibl_t c6474_ibl_config(void)
113 {
114 ibl_t ibl;
116 ibl.iblMagic = ibl_MAGIC_VALUE;
117 ibl.iblEvmType = ibl_EVM_C6474M;
119 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
120 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
121 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
122 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
123 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
125 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
126 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
128 /* The network PLL. The multipliers/dividers are fixed */
129 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
131 /* EMIF configuration. The values are for DDR at 533 MHz */
132 ibl.ddrConfig.configDdr = TRUE;
134 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
135 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
136 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
137 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
138 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
140 /* SGMII 0 is present */
141 ibl.sgmiiConfig[0].configure = TRUE;
142 ibl.sgmiiConfig[0].adviseAbility = 0x9801;
143 ibl.sgmiiConfig[0].control = 0x20;
144 ibl.sgmiiConfig[0].txConfig = 0x00000ea3;
145 ibl.sgmiiConfig[0].rxConfig = 0x00081023;
146 ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
148 /* There is no port 1 on the 6474 */
149 ibl.sgmiiConfig[1].configure = FALSE;
151 /* MDIO configuration */
152 ibl.mdioConfig.nMdioOps = 8;
153 ibl.mdioConfig.mdioClkDiv = 0x26;
154 ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
156 ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
157 ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
158 ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (13 << 16) | 0x0047;
159 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
161 ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (13 << 16) | 0x8140;
162 ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
163 ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
164 ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
166 /* spiConfig and emifConfig not needed */
168 /* Ethernet configuration for Boot mode 0 */
169 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
170 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
171 ibl.bootModes[0].port = 0;
173 /* Bootp is disabled. The server and file name are provided here */
174 ibl.bootModes[0].u.ethBoot.doBootp = TRUE;
175 ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
176 ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
177 ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
179 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 192,168,1,3);
180 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 192,168,1,2);
181 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
182 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
184 /* Set the hardware address as 0 so the e-fuse value will be used */
185 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
186 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
187 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
188 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
189 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
190 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
192 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
193 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
194 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
195 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '7';
196 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '4';
197 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
198 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
199 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
200 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
201 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
202 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
203 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
204 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
205 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
206 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
208 /* Even though the entire range of DDR2 is chosen, the load will
209 * stop when the ftp reaches the end of the file */
210 ibl.bootModes[0].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
211 ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
212 ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
214 /* Alternative bootMode not configured for now */
215 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;
217 ibl.chkSum = 0;
219 return(ibl);
220 }
222 ibl_t c6474l_ibl_config(void)
223 {
224 ibl_t ibl;
226 ibl.iblMagic = ibl_MAGIC_VALUE;
227 ibl.iblEvmType = ibl_EVM_C6474L;
229 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
230 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
231 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
232 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
233 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
235 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
236 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
238 /* The network PLL. The multipliers/dividers are fixed */
239 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
241 /* EMIF configuration. The values are for DDR at 533 MHz */
242 ibl.ddrConfig.configDdr = TRUE;
244 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
245 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
246 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
247 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
248 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
250 /* SGMII 0 is present */
251 ibl.sgmiiConfig[0].configure = TRUE;
252 ibl.sgmiiConfig[0].adviseAbility = 0x9801;
253 ibl.sgmiiConfig[0].control = 0x20;
254 ibl.sgmiiConfig[0].txConfig = 0x00000e23;
255 ibl.sgmiiConfig[0].rxConfig = 0x00081023;
256 ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
258 /* There is no port 1 on the 6474 */
259 ibl.sgmiiConfig[1].configure = FALSE;
261 /* MDIO configuration */
262 ibl.mdioConfig.nMdioOps = 5;
263 ibl.mdioConfig.mdioClkDiv = 0x20;
264 ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
266 ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
267 ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
268 ibl.mdioConfig.mdio[2] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
270 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
271 ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
273 /* spiConfig and emifConfig not needed */
275 /* Ethernet configuration for Boot mode 0 */
276 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
277 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
278 ibl.bootModes[0].port = 0;
280 /* Bootp is disabled. The server and file name are provided here */
281 ibl.bootModes[0].u.ethBoot.doBootp = TRUE;
282 ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
283 ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
284 ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
286 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 192,168,1,3);
287 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 192,168,1,2);
288 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
289 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
291 /* Set the hardware address as 0 so the e-fuse value will be used */
292 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
293 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
294 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
295 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
296 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
297 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
300 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
301 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
302 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
303 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '7';
304 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '4';
305 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = 'l';
306 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = '-';
307 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'l';
308 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = 'e';
309 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = '.';
310 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'b';
311 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'i';
312 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = 'n';
313 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
314 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
317 /* Even though the entire range of DDR2 is chosen, the load will
318 * stop when the ftp reaches the end of the file */
319 ibl.bootModes[0].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
320 ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
321 ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
323 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
324 ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
325 ibl.bootModes[1].port = 0;
327 ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
328 ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x200000; /* Image 0 NAND offset address (block 1) in LE mode */
329 ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in LE mode */
330 ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x200000; /* Image 0 NAND offset address (block 1) in BE mode */
331 ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in BE mode */
332 ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
334 ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
335 ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
336 ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
337 ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
338 ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
339 ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
340 ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
341 ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
342 ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
343 ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
344 ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
345 ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
348 ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
349 ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 2048;
350 ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 64;
351 ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 64;
352 ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 512;
354 ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
355 ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
356 ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 22;
357 ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
358 ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
360 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
361 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
362 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
363 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
364 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
365 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
366 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
367 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
368 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
369 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
371 ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
372 ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
374 ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
375 ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
376 ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
377 ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
380 /* bootMode[2] not configured */
381 ibl.bootModes[2].bootMode = ibl_BOOT_MODE_NONE;
383 ibl.chkSum = 0;
385 return(ibl);
386 }
388 ibl_t c6457_ibl_config(void)
389 {
390 ibl_t ibl;
392 ibl.iblMagic = ibl_MAGIC_VALUE;
393 ibl.iblEvmType = ibl_EVM_C6457L;
395 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
396 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
397 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
398 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
399 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
401 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
402 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
404 /* The network PLL. The multipliers/dividers are fixed */
405 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
407 /* EMIF configuration */
408 ibl.ddrConfig.configDdr = TRUE;
410 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
411 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a0e; /* Refresh 333Mhz */
412 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x832474da; /* Timing 1 */
413 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0144c742; /* Timing 2 */
414 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x001800C6;
416 /* SGMII 0 is present */
417 ibl.sgmiiConfig[0].configure = TRUE;
418 ibl.sgmiiConfig[0].adviseAbility = 0x9801;
419 ibl.sgmiiConfig[0].control = 0x20;
420 ibl.sgmiiConfig[0].txConfig = 0x00000e21;
421 ibl.sgmiiConfig[0].rxConfig = 0x00081021;
422 ibl.sgmiiConfig[0].auxConfig = 0x0000000b;
424 /* There is no port 1 on the 6457 */
425 ibl.sgmiiConfig[1].configure = FALSE;
427 /* MDIO configuration */
428 ibl.mdioConfig.nMdioOps = 5;
429 ibl.mdioConfig.mdioClkDiv = 0xa5;
430 ibl.mdioConfig.interDelay = 3000; /* ~2ms at 1000 MHz */
432 ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
433 ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
434 ibl.mdioConfig.mdio[2] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
435 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
436 ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0x9140;
438 /* spiConfig and emifConfig not needed */
440 /* Ethernet configuration for Boot mode 0 */
441 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
442 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
443 ibl.bootModes[0].port = 0;
445 /* Bootp is disabled. The server and file name are provided here */
446 ibl.bootModes[0].u.ethBoot.doBootp = TRUE;
447 ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
448 ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
449 ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
451 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 192,168,1,3);
452 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 192,168,1,2);
453 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
454 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
456 /* Set the hardware address as 0 so the e-fuse value will be used */
457 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
458 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
459 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
460 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
461 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
462 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
464 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
465 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
466 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
467 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '5';
468 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '7';
469 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
470 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
471 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
472 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
473 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
474 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
475 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
476 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
477 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
478 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
481 /* Even though the entire range of DDR2 is chosen, the load will
482 * stop when the ftp reaches the end of the file */
483 ibl.bootModes[0].u.ethBoot.blob.startAddress = 0xe0000000; /* Base address of DDR2 */
484 ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
485 ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
487 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
488 ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
489 ibl.bootModes[1].port = 0;
491 ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
492 ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x200000; /* Image 0 NAND offset address (block 1) in LE mode */
493 ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in LE mode */
494 ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x200000; /* Image 0 NAND offset address (block 1) in BE mode */
495 ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in BE mode */
496 ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
498 ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0xe0000000; /* Image 0 load start address in LE mode */
499 ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
500 ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in LE mode */
501 ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0xe0000000; /* Image 1 load start address in LE mode */
502 ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
503 ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in LE mode */
504 ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0xe0000000; /* Image 0 load start address in BE mode */
505 ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
506 ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in BE mode */
507 ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0xe0000000; /* Image 1 load start address in BE mode */
508 ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
509 ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in BE mode */
512 ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
513 ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 2048;
514 ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 64;
515 ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 64;
516 ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 512;
518 ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
519 ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
520 ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 22;
521 ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
522 ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
524 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
525 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
526 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
527 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
528 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
529 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
530 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
531 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
532 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
533 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
535 ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
536 ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
538 ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
539 ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
540 ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
541 ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
544 /* bootMode[2] not configured */
545 ibl.bootModes[2].bootMode = ibl_BOOT_MODE_NONE;
547 ibl.chkSum = 0;
549 return(ibl);
550 }
552 ibl_t c6472_ibl_config(void)
553 {
554 ibl_t ibl;
556 ibl.iblMagic = ibl_MAGIC_VALUE;
557 ibl.iblEvmType = ibl_EVM_C6472L;
559 ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
560 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
561 ibl.pllConfig[ibl_MAIN_PLL].mult = 28;
562 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
563 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 700;
565 /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
566 ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
568 /* The network PLL. The multipliers/dividers are fixed */
569 ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
571 /* EMIF configuration. The values are for DDR at 533 MHz */
572 ibl.ddrConfig.configDdr = TRUE;
574 ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538832; /* timing, 32bit wide */
575 ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x0000073B; /* Refresh 533Mhz */
576 ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x47245BD2; /* Timing 1 */
577 ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */
578 ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
580 /* SGMII not present */
581 ibl.sgmiiConfig[0].configure = FALSE;
582 ibl.sgmiiConfig[1].configure = FALSE;
584 /* MDIO configuration */
585 ibl.mdioConfig.nMdioOps = 8;
586 ibl.mdioConfig.mdioClkDiv = 0x20;
587 ibl.mdioConfig.interDelay = 1400; /* ~2ms at 700 MHz */
589 ibl.mdioConfig.mdio[0] = (1 << 30) | (27 << 21) | (24 << 16) | 0x848b;
590 ibl.mdioConfig.mdio[1] = (1 << 30) | (20 << 21) | (24 << 16) | 0x0ce0;
591 ibl.mdioConfig.mdio[2] = (1 << 30) | (24 << 21) | (24 << 16) | 0x4101;
592 ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (24 << 16) | 0x9140;
594 ibl.mdioConfig.mdio[4] = (1 << 30) | (27 << 21) | (25 << 16) | 0x848b;
595 ibl.mdioConfig.mdio[5] = (1 << 30) | (20 << 21) | (25 << 16) | 0x0ce0;
596 ibl.mdioConfig.mdio[6] = (1 << 30) | (24 << 21) | (25 << 16) | 0x4101;
597 ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | (25 << 16) | 0x9140;
599 /* spiConfig and emifConfig not needed */
601 /* Ethernet configuration for Boot mode 0 */
602 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;
603 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
604 ibl.bootModes[0].port = 0;
606 /* Bootp is disabled. The server and file name are provided here */
607 ibl.bootModes[0].u.ethBoot.doBootp = TRUE;
608 ibl.bootModes[0].u.ethBoot.useBootpServerIp = TRUE;
609 ibl.bootModes[0].u.ethBoot.useBootpFileName = TRUE;
610 ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
612 /* Even though the entire range of DDR2 is chosen, the load will
613 * stop when the ftp reaches the end of the file */
614 ibl.bootModes[0].u.ethBoot.blob.startAddress = 0xe0000000; /* Base address of DDR2 */
615 ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
616 ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0xe0000000; /* Base of DDR2 */
618 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 192,168,1,3);
619 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 192,168,1,2);
620 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
621 SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0);
623 /* Leave the hardware address as 0 so the e-fuse value will be used */
624 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;
625 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;
626 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;
627 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;
628 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;
629 ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;
631 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 'c';
632 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = '6';
633 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = '4';
634 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = '7';
635 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '2';
636 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = '-';
637 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l';
638 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'e';
639 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = '.';
640 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = 'b';
641 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = 'i';
642 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = 'n';
643 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';
644 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';
645 ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';
647 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
648 ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
649 ibl.bootModes[1].port = 0;
651 ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
652 ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x200000; /* Image 0 NAND offset address (block 1) in LE mode */
653 ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in LE mode */
654 ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x200000; /* Image 0 NAND offset address (block 1) in BE mode */
655 ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in BE mode */
656 ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
658 ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0xe0000000; /* Image 0 load start address in LE mode */
659 ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
660 ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in LE mode */
661 ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0xe0000000; /* Image 1 load start address in LE mode */
662 ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
663 ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in LE mode */
664 ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0xe0000000; /* Image 0 load start address in BE mode */
665 ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
666 ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in BE mode */
667 ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0xe0000000; /* Image 1 load start address in BE mode */
668 ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
669 ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0xe0000000; /* Image 1 branch address after loading in BE mode */
672 ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
673 ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 2048;
674 ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 64;
675 ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 64;
676 ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 512;
678 ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
679 ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
680 ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 22;
681 ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
682 ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
684 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
685 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
686 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
687 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
688 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
689 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
690 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
691 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
692 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
693 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
695 ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
696 ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
698 ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
699 ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
700 ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
701 ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
703 /* bootMode[2] not configured */
704 ibl.bootModes[2].bootMode = ibl_BOOT_MODE_NONE;
706 ibl.chkSum = 0;
708 return(ibl);
709 }
711 ibl_t c6678_ibl_config(void)
712 {
713 ibl_t ibl;
715 ibl.iblMagic = ibl_MAGIC_VALUE;
716 ibl.iblEvmType = ibl_EVM_C6678L;
718 /* Main PLL: 100 MHz reference, 1GHz output */
719 ibl.pllConfig[ibl_MAIN_PLL].doEnable = 1;
720 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
721 ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
722 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 2;
723 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
725 /* DDR PLL: */
726 ibl.pllConfig[ibl_DDR_PLL].doEnable = 0;
727 ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
728 ibl.pllConfig[ibl_DDR_PLL].mult = 20;
729 ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
730 ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 1333;
732 /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */
733 ibl.pllConfig[ibl_NET_PLL].doEnable = 1;
734 ibl.pllConfig[ibl_NET_PLL].prediv = 1;
735 ibl.pllConfig[ibl_NET_PLL].mult = 21;
736 ibl.pllConfig[ibl_NET_PLL].postdiv = 2;
737 ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz = 1050;
740 ibl.ddrConfig.configDdr = 1;
741 ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;
743 ibl.ddrConfig.uEmif.emif4p0.sdRamConfig = 0x63C452B2;
744 ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2 = 0;
745 ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl = 0x000030D4;
746 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1 = 0x0AAAE51B;
747 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2 = 0x2A2F7FDA;
748 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3 = 0x057F82B8;
749 ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming = 0;
750 ibl.ddrConfig.uEmif.emif4p0.powerManageCtl = 0;
751 ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic = 0;
752 ibl.ddrConfig.uEmif.emif4p0.performCountCfg = 0;
753 ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel = 0;
754 ibl.ddrConfig.uEmif.emif4p0.readIdleCtl = 0;
755 ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet = 0;
756 ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg = 0;
757 ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg = 0;
758 ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1 = 0x0010010d;
759 ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2 = 0;
760 ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap = 0;
761 ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map = 0;
762 ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map = 0;
763 ibl.ddrConfig.uEmif.emif4p0.eccCtl = 0;
764 ibl.ddrConfig.uEmif.emif4p0.eccRange1 = 0;
765 ibl.ddrConfig.uEmif.emif4p0.eccRange2 = 0;
766 ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh = 0;
769 ibl.sgmiiConfig[0].configure = 1;
770 ibl.sgmiiConfig[0].adviseAbility = 1;
771 ibl.sgmiiConfig[0].control = 1;
772 ibl.sgmiiConfig[0].txConfig = 0x108a1;
773 ibl.sgmiiConfig[0].rxConfig = 0x700621;
774 ibl.sgmiiConfig[0].auxConfig = 0x41;
776 ibl.sgmiiConfig[1].configure = 1;
777 ibl.sgmiiConfig[1].adviseAbility = 1;
778 ibl.sgmiiConfig[1].control = 1;
779 ibl.sgmiiConfig[1].txConfig = 0x108a1;
780 ibl.sgmiiConfig[1].rxConfig = 0x700621;
781 ibl.sgmiiConfig[1].auxConfig = 0x41;
783 ibl.mdioConfig.nMdioOps = 0;
785 ibl.spiConfig.addrWidth = 24;
786 ibl.spiConfig.nPins = 5;
787 ibl.spiConfig.mode = 1;
788 ibl.spiConfig.csel = 2;
789 ibl.spiConfig.c2tdelay = 1;
790 ibl.spiConfig.busFreqMHz = 20;
792 ibl.emifConfig[0].csSpace = 2;
793 ibl.emifConfig[0].busWidth = 8;
794 ibl.emifConfig[0].waitEnable = 0;
796 ibl.emifConfig[1].csSpace = 0;
797 ibl.emifConfig[1].busWidth = 0;
798 ibl.emifConfig[1].waitEnable = 0;
800 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NOR;
801 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
802 ibl.bootModes[0].port = 0;
804 ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
805 ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
806 ibl.bootModes[0].u.norBoot.bootAddress[0][1] = 0xA00000; /* Image 1 NOR offset byte address in LE mode */
807 ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
808 ibl.bootModes[0].u.norBoot.bootAddress[1][1] = 0xA00000; /* Image 1 NOR offset byte address in BE mode */
809 ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
810 ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
811 ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
812 ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
813 ibl.bootModes[0].u.norBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
814 ibl.bootModes[0].u.norBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
815 ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
816 ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
817 ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
818 ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
819 ibl.bootModes[0].u.norBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
820 ibl.bootModes[0].u.norBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
821 ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
823 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
824 ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
825 ibl.bootModes[1].port = 0;
827 ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
828 ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x4000; /* Image 0 NAND offset address (block 1) in LE mode */
829 ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in LE mode */
830 ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x4000; /* Image 0 NAND offset address (block 1) in BE mode */
831 ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in BE mode */
832 ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_CHIPSEL_2;
834 ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
835 ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xFFC000; /* Image 0 size in LE mode */
836 ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
837 ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
838 ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xFFC000; /* Image 1 size in LE mode */
839 ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
840 ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
841 ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xFFC000; /* Image 0 size in BE mode */
842 ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
843 ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
844 ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xFFC000; /* Image 1 size in BE mode */
845 ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
848 ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
849 ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 512;
850 ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 16;
851 ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 32;
852 ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 4096;
854 ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
855 ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
856 ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 14;
857 ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 9;
858 ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
860 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
861 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
862 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
863 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
864 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
865 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
866 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
867 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
868 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
869 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
871 ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
872 ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
874 ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
875 ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
876 ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
877 ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
879 ibl.bootModes[2].bootMode = ibl_BOOT_MODE_TFTP;
880 ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
881 ibl.bootModes[2].port = ibl_PORT_SWITCH_ALL;
883 ibl.bootModes[2].u.ethBoot.doBootp = TRUE;
884 ibl.bootModes[2].u.ethBoot.useBootpServerIp = TRUE;
885 ibl.bootModes[2].u.ethBoot.useBootpFileName = TRUE;
886 ibl.bootModes[2].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
889 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr, 192,168,1,3);
890 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp, 192,168,1,2);
891 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
892 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.netmask, 255,255,255,0);
894 /* Use the e-fuse value */
895 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[0] = 0;
896 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[1] = 0;
897 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[2] = 0;
898 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[3] = 0;
899 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[4] = 0;
900 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[5] = 0;
903 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[0] = 'c';
904 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[1] = '6';
905 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[2] = '6';
906 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[3] = '7';
907 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[4] = '8';
908 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[5] = '-';
909 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[6] = 'l';
910 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[7] = 'e';
911 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[8] = '.';
912 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[9] = 'b';
913 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[10] = 'i';
914 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[11] = 'n';
915 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[12] = '\0';
916 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
917 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
919 ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Load start address */
920 ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0x20000000;
921 ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Branch address after loading */
923 ibl.chkSum = 0;
925 return(ibl);
926 }
928 ibl_t c6670_ibl_config(void)
929 {
930 ibl_t ibl;
932 ibl.iblMagic = ibl_MAGIC_VALUE;
933 ibl.iblEvmType = ibl_EVM_C6670L;
935 /* Main PLL: 122.88 MHz reference, 983 MHz output */
936 ibl.pllConfig[ibl_MAIN_PLL].doEnable = 1;
937 ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
938 ibl.pllConfig[ibl_MAIN_PLL].mult = 16;
939 ibl.pllConfig[ibl_MAIN_PLL].postdiv = 2;
940 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
942 /* DDR PLL */
943 ibl.pllConfig[ibl_DDR_PLL].doEnable = 0;
944 ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
945 ibl.pllConfig[ibl_DDR_PLL].mult = 20;
946 ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
947 ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 1333;
949 /* Net PLL: 122.88 MHz reference, 1044 MHz output (followed by a built in divide by 3 to give 348 MHz to PA) */
950 ibl.pllConfig[ibl_NET_PLL].doEnable = 1;
951 ibl.pllConfig[ibl_NET_PLL].prediv = 1;
952 ibl.pllConfig[ibl_NET_PLL].mult = 17;
953 ibl.pllConfig[ibl_NET_PLL].postdiv = 2;
954 ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz = 1044;
957 ibl.ddrConfig.configDdr = 1;
958 ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;
960 ibl.ddrConfig.uEmif.emif4p0.sdRamConfig = 0x63C452B2;
961 ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2 = 0;
962 ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl = 0x000030D4;
963 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1 = 0x0AAAE51B;
964 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2 = 0x2A2F7FDA;
965 ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3 = 0x057F82B8;
966 ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming = 0;
967 ibl.ddrConfig.uEmif.emif4p0.powerManageCtl = 0;
968 ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic = 0;
969 ibl.ddrConfig.uEmif.emif4p0.performCountCfg = 0;
970 ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel = 0;
971 ibl.ddrConfig.uEmif.emif4p0.readIdleCtl = 0;
972 ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet = 0;
973 ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg = 0;
974 ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg = 0;
975 ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1 = 0x0010010d;
976 ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2 = 0;
977 ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap = 0;
978 ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map = 0;
979 ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map = 0;
980 ibl.ddrConfig.uEmif.emif4p0.eccCtl = 0;
981 ibl.ddrConfig.uEmif.emif4p0.eccRange1 = 0;
982 ibl.ddrConfig.uEmif.emif4p0.eccRange2 = 0;
983 ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh = 0;
986 ibl.sgmiiConfig[0].configure = 1;
987 ibl.sgmiiConfig[0].adviseAbility = 1;
988 ibl.sgmiiConfig[0].control = 1;
989 ibl.sgmiiConfig[0].txConfig = 0x108a1;
990 ibl.sgmiiConfig[0].rxConfig = 0x700621;
991 ibl.sgmiiConfig[0].auxConfig = 0x41;
993 ibl.sgmiiConfig[1].configure = 1;
994 ibl.sgmiiConfig[1].adviseAbility = 1;
995 ibl.sgmiiConfig[1].control = 1;
996 ibl.sgmiiConfig[1].txConfig = 0x108a1;
997 ibl.sgmiiConfig[1].rxConfig = 0x700621;
998 ibl.sgmiiConfig[1].auxConfig = 0x51;
1000 ibl.mdioConfig.nMdioOps = 0;
1002 ibl.spiConfig.addrWidth = 24;
1003 ibl.spiConfig.nPins = 5;
1004 ibl.spiConfig.mode = 1;
1005 ibl.spiConfig.csel = 2;
1006 ibl.spiConfig.c2tdelay = 1;
1007 ibl.spiConfig.busFreqMHz = 20;
1009 ibl.emifConfig[0].csSpace = 2;
1010 ibl.emifConfig[0].busWidth = 8;
1011 ibl.emifConfig[0].waitEnable = 0;
1013 ibl.emifConfig[1].csSpace = 0;
1014 ibl.emifConfig[1].busWidth = 0;
1015 ibl.emifConfig[1].waitEnable = 0;
1017 ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NOR;
1018 ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
1019 ibl.bootModes[0].port = 0;
1021 ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
1022 ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
1023 ibl.bootModes[0].u.norBoot.bootAddress[0][1] = 0xA00000; /* Image 1 NOR offset byte address in LE mode */
1024 ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
1025 ibl.bootModes[0].u.norBoot.bootAddress[1][1] = 0xA00000; /* Image 1 NOR offset byte address in BE mode */
1026 ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
1027 ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
1028 ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
1029 ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
1030 ibl.bootModes[0].u.norBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
1031 ibl.bootModes[0].u.norBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
1032 ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
1033 ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
1034 ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
1035 ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
1036 ibl.bootModes[0].u.norBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
1037 ibl.bootModes[0].u.norBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
1038 ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
1040 ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
1041 ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
1042 ibl.bootModes[1].port = 0;
1044 ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
1045 ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x4000; /* Image 0 NAND offset address (block 1) in LE mode */
1046 ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in LE mode */
1047 ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x4000; /* Image 0 NAND offset address (block 1) in BE mode */
1048 ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x2000000; /* Image 1 NAND offset address (block 2048) in BE mode */
1049 ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
1051 ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
1052 ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xFFC000; /* Image 0 size in LE mode */
1053 ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
1054 ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
1055 ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xFFC000; /* Image 1 size in LE mode */
1056 ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
1057 ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
1058 ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xFFC000; /* Image 0 size mode */
1059 ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
1060 ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
1061 ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xFFC000; /* Image 1 size in BE mode */
1062 ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
1065 ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
1066 ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 512;
1067 ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 16;
1068 ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 32;
1069 ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 4096;
1071 ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
1072 ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
1073 ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 14;
1074 ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 9;
1075 ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
1077 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
1078 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
1079 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
1080 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
1081 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
1082 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
1083 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
1084 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
1085 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
1086 ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
1088 ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
1089 ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
1091 ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
1092 ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
1093 ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
1094 ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
1096 ibl.bootModes[2].bootMode = ibl_BOOT_MODE_TFTP;
1097 ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
1098 ibl.bootModes[2].port = ibl_PORT_SWITCH_ALL;
1100 ibl.bootModes[2].u.ethBoot.doBootp = FALSE;
1101 ibl.bootModes[2].u.ethBoot.useBootpServerIp = TRUE;
1102 ibl.bootModes[2].u.ethBoot.useBootpFileName = TRUE;
1103 ibl.bootModes[2].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
1106 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr, 158,218,100,113);
1107 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp, 158,218,100,251);
1108 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 158,218,100,1);
1109 SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.netmask, 255,255,255,0);
1111 /* Use the e-fuse value */
1112 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[0] = 0;
1113 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[1] = 0;
1114 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[2] = 0;
1115 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[3] = 0;
1116 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[4] = 0;
1117 ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[5] = 0;
1120 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[0] = 'c';
1121 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[1] = '6';
1122 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[2] = '6';
1123 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[3] = '7';
1124 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[4] = '0';
1125 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[5] = '-';
1126 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[6] = 'l';
1127 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[7] = 'e';
1128 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[8] = '.';
1129 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[9] = 'b';
1130 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[10] = 'i';
1131 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[11] = 'n';
1132 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[12] = '\0';
1133 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
1134 ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
1136 ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Load start address */
1137 ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0x20000000;
1138 ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Branch address after loading */
1140 ibl.chkSum = 0;
1142 return(ibl);
1143 }