1 /*
2 *
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
38 /********************************************************************************************************
39 * FILE PURPOSE: IBL configuration and control definitions
40 ********************************************************************************************************
41 * FILE NAME: ibl.h
42 *
43 * DESCRIPTION: Defines the data structure used to handle initial configuration and control
44 * of the ibl. This data structure resides at a fixed location in the device memory
45 * map. It is initially populated either during the rom boot. The table can be
46 * over-written during the ibl process to redirect the boot. For example the ibl
47 * can initially load from an i2c which repopulates this table with parameters
48 * for an ethernet boot.
49 *
50 * @file ibl.h
51 *
52 * @brief
53 * This file defines the configuration and control of the IBL
54 *
55 *
56 ********************************************************************************************************/
57 #ifndef IBL_H
58 #define IBL_H
60 #include "types.h"
63 #define ibl_MAKE_VERSION(a,b,c,d) ((a << 24) | (b << 16) | (c << 8) | (d << 0))
66 /**
67 * @brief
68 * The version number, 1.0.0.11
69 */
70 #define ibl_VERSION ibl_MAKE_VERSION(1,0,0,11)
72 #define SETIP(array,i0,i1,i2,i3) array[0]=(i0); \
73 array[1]=(i1); \
74 array[2]=(i2); \
75 array[3]=(i3)
76 /**
77 * @defgroup iblBootModes Defines the boot modes supported by the IBL
78 *
79 * @ingroup iblBootModes
80 * @{
81 *
82 * @def ibl_BOOT_MODE_TFTP */
83 #define ibl_BOOT_MODE_TFTP 10 /* Boot through a tftp interface */
85 /* @def ibl_BOOT_MODE_NAND */
86 #define ibl_BOOT_MODE_NAND 11 /* Boot through a nand interface */
88 /* @def ibl_BOOT_MODE_NOR */
89 #define ibl_BOOT_MODE_NOR 12 /* Boot through a nor (or flash) interface */
91 /* @def ibl_BOOT_MODE_NONE */
92 #define ibl_BOOT_MODE_NONE 13 /* Boot mode selection is inactive */
94 /* @} */
96 /**
97 * @brief
98 * Define the number of different boot modes which can be configured for
99 * a single execution of the IBL.
100 */
101 #define ibl_N_BOOT_MODES 3
103 /* Information used to make generate a bootp request */
104 /**
105 * @brief
106 * Defines parameters used for making a bootp request
107 *
108 * @details
109 * The bootp request parameters are created from these fields
110 */
111 typedef struct iblBootp_s
112 {
113 uint8 hwAddress[6]; /**< The hardware (mac) address of this device. If set to 0
114 the ibl will values from e-fuse */
116 uint8 ipDest[4]; /**< The IP address of this device. This is typically set
117 to IP broadcast */
119 } iblBootp_t;
122 /**
123 * @brief
124 * This structure contains information used for tftp boot.
125 *
126 * @details These fields are typically filled in by the bootp packet, but
127 * can be provided if bootp will not be used.
128 */
129 typedef struct iblEthBootInfo_s
130 {
131 uint8 ipAddr[4]; /**< The IP address of this device */
132 uint8 serverIp[4]; /**< The IP address of the tftp server */
133 uint8 gatewayIp[4]; /**< The IP address of the gateway */
134 uint8 netmask[4]; /**< The IP netmask */
135 uint8 hwAddress[6]; /**< The hardware (mac) address of this device */
136 char8 fileName[64]; /**< The file name to load */
138 } iblEthBootInfo_t;
141 /**
142 * @def ibl_ETH_PORT_FROM_RBL
143 */
144 #define ibl_ETH_PORT_FROM_RBL -1 /**< The ethernet port used is the same one used
145 during the ROM boot load process. */
147 /**
148 * @def ibl_PORT_SWITCH_ALL
149 */
150 #define ibl_PORT_SWITCH_ALL -2 /**< The ethernet subsystem is connected to a switch, and
151 all ports on the subsystem should be configured */
154 /**
155 * @defgroup iblBootFormats
156 *
157 * @ingroup iblBootFormats
158 * @{
159 */
160 #define ibl_BOOT_FORMAT_AUTO 0 /**< Auto determine the boot format from the data */
161 #define ibl_BOOT_FORMAT_NAME 1 /**< Determines the boot format based on file name (bootp/tftp only) */
162 #define ibl_BOOT_FORMAT_BIS 2 /**< Boot TI AIS format */
163 #define ibl_BOOT_FORMAT_COFF 3 /**< Boot a COFF file */
164 #define ibl_BOOT_FORMAT_ELF 4 /**< Boot an ELF file */
165 #define ibl_BOOT_FORMAT_BBLOB 5 /**< Boot a binary blob */
166 #define ibl_BOOT_FORMAT_BTBL 6 /**< Boot a TI boot table file */
168 /* @} */
170 /**
171 * @defgroup iblPeriphPriority Defines the boot sequence
172 *
173 * @ingroup iblPeriphPriority
174 * @{
175 * @def ibl_LOWEST_PRIORITY
176 */
177 #define ibl_LOWEST_PRIORITY 10 /**< The lowest priority assignable to a peripheral for boot */
179 /**
180 * @def ibl_HIGHEST_PRIORITY
181 */
182 #define ibl_HIGHEST_PRIORITY 1 /**< The highest priority assignable to a peripheral for boot */
184 /**
185 * @def ibl_DEVICE_NOBOOT
186 */
187 #define ibl_DEVICE_NOBOOT 20 /**< Indicates that the device is not to be used for boot */
189 /* @} */
192 /**
193 * @brief
194 * Emif controller 3.1 configuration
195 *
196 * @details
197 * The paramters are directly placed into the emif controller
198 */
199 typedef struct iblEmif3p1_s
200 {
201 uint32 sdcfg; /**< SD configuration register */
202 uint32 sdrfc; /**< Refresh timing register */
203 uint32 sdtim1; /**< DDR timing register 1 */
204 uint32 sdtim2; /**< DDR timing register 2 */
205 uint32 dmcctl; /**< CAS match timing */
207 } iblEmif3p1_t;
210 /**
211 * @brief
212 * Emif controller 4.0 configuration
213 *
214 * @details
215 * The parameters are placed directly into the emif controller
216 */
217 typedef struct iblEmif4p0_s
218 {
219 uint32 registerMask; /**< Identifies which registers will be configured */
220 uint32 sdRamConfig; /**< SDRAM Config Register */
221 uint32 sdRamConfig2; /**< SDRAM Config2 Register */
222 uint32 sdRamRefreshCtl; /**< SDRAM Refresh Control Register */
223 uint32 sdRamTiming1; /**< SDRAM Timing 1 Register */
224 uint32 sdRamTiming2; /**< SDRAM Timing 2 Register */
225 uint32 sdRamTiming3; /**< SDRAM Timing 3 Register */
226 uint32 lpDdrNvmTiming; /**< LPDDR2-NVM Timing Register */
227 uint32 powerManageCtl; /**< Power Management Control Register */
228 uint32 iODFTTestLogic; /**< IODFT Test Logic Global Control Register */
229 uint32 performCountCfg; /**< Performance Counter Config Register */
230 uint32 performCountMstRegSel; /**< Performance Counter Master Region Select Register */
231 uint32 readIdleCtl; /**< Read Idle Control Register */
232 uint32 sysVbusmIntEnSet; /**< VBUSM Interrupt Enable Set Register */
233 uint32 sdRamOutImpdedCalCfg; /**< SDRAM Output Impedance Calibratin Config Register */
234 uint32 tempAlterCfg; /**< Temperature Alert Config Register */
235 uint32 ddrPhyCtl1; /**< DDR PHY Control 1 Register */
236 uint32 ddrPhyCtl2; /**< DDR PHY Control 2 Register */
237 uint32 priClassSvceMap; /**< DDR Priority to Class of Service Mapping Register */
238 uint32 mstId2ClsSvce1Map; /**< Master ID to Class of Service 1 Mapping Register */
239 uint32 mstId2ClsSvce2Map; /**< Master ID to Class of Service 2 Mapping Register */
240 uint32 eccCtl; /**< ECC Control Register */
241 uint32 eccRange1; /**< ECC Address Range 1 Register */
242 uint32 eccRange2; /**< ECC Address Range 2 Register */
243 uint32 rdWrtExcThresh; /**< Read Write Execution Threshold Register */
245 } iblEmif4p0_t;
248 /**
249 * @defgroup iblEmif4Select Defines the EMIF4 registers configured by IBL
250 *
251 * @ingroup iblEmif4Select
252 * @{
253 * @def ibl_EMIF4_ENABLE_sdRamConfig
254 */
255 #define ibl_EMIF4_ENABLE_sdRamConfig (1 << 0)
257 /** @def ibl_EMIF4_ENABLE_sdRamConfig2 */
258 #define ibl_EMIF4_ENABLE_sdRamConfig2 (1 << 1)
260 /** @def ibl_EMIF4_ENABLE_sdRamRefreshCtl */
261 #define ibl_EMIF4_ENABLE_sdRamRefreshCtl (1 << 2)
263 /** @def ibl_EMIF4_ENABLE_sdRamTiming1 */
264 #define ibl_EMIF4_ENABLE_sdRamTiming1 (1 << 3)
266 /** @def ibl_EMIF4_ENABLE_sdRamTiming2 */
267 #define ibl_EMIF4_ENABLE_sdRamTiming2 (1 << 4)
269 /** @def ibl_EMIF4_ENABLE_sdRamTiming3 */
270 #define ibl_EMIF4_ENABLE_sdRamTiming3 (1 << 5)
272 /** @def ibl_EMIF4_ENABLE_lpDdrNvmTiming */
273 #define ibl_EMIF4_ENABLE_lpDdrNvmTiming (1 << 6)
275 /** @def ibl_EMIF4_ENABLE_powerManageCtl */
276 #define ibl_EMIF4_ENABLE_powerManageCtl (1 << 7)
278 /** @def ibl_EMIF4_ENABLE_iODFTTestLogic */
279 #define ibl_EMIF4_ENABLE_iODFTTestLogic (1 << 8)
281 /** @def ibl_EMIF4_ENABLE_performCountCfg */
282 #define ibl_EMIF4_ENABLE_performCountCfg (1 << 9)
284 /** @def ibl_EMIF4_ENABLE_performCountMstRegSel */
285 #define ibl_EMIF4_ENABLE_performCountMstRegSel (1 << 10)
287 /** @def ibl_EMIF4_ENABLE_readIdleCtl */
288 #define ibl_EMIF4_ENABLE_readIdleCtl (1 << 11)
290 /** @def ibl_EMIF4_ENABLE_sysVbusmIntEnSet */
291 #define ibl_EMIF4_ENABLE_sysVbusmIntEnSet (1 << 12)
293 /** @def ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg */
294 #define ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg (1 << 13)
296 /** @def ibl_EMIF4_ENABLE_tempAlterCfg */
297 #define ibl_EMIF4_ENABLE_tempAlterCfg (1 << 14)
299 /** @def ibl_EMIF4_ENABLE_ddrPhyCtl1 */
300 #define ibl_EMIF4_ENABLE_ddrPhyCtl1 (1 << 15)
302 /** @def ibl_EMIF4_ENABLE_ddrPhyCtl2 */
303 #define ibl_EMIF4_ENABLE_ddrPhyCtl2 (1 << 16)
305 /** @def ibl_EMIF4_ENABLE_priClassSvceMap */
306 #define ibl_EMIF4_ENABLE_priClassSvceMap (1 << 17)
308 /** @def ibl_EMIF4_ENABLE_mstId2ClsSvce1Map */
309 #define ibl_EMIF4_ENABLE_mstId2ClsSvce1Map (1 << 18)
311 /** @def ibl_EMIF4_ENABLE_mstId2ClsSvce2Map */
312 #define ibl_EMIF4_ENABLE_mstId2ClsSvce2Map (1 << 11)
314 /** @def ibl_EMIF4_ENABLE_eccCtl */
315 #define ibl_EMIF4_ENABLE_eccCtl (1 << 19)
317 /** @def ibl_EMIF4_ENABLE_eccRange1 */
318 #define ibl_EMIF4_ENABLE_eccRange1 (1 << 20)
320 /** @def ibl_EMIF4_ENABLE_eccRange2 */
321 #define ibl_EMIF4_ENABLE_eccRange2 (1 << 21)
323 /** @def ibl_EMIF4_ENABLE_rdWrtExcThresh */
324 #define ibl_EMIF4_ENABLE_rdWrtExcThresh (1 << 22)
326 /** @def ibl_BOOT_EMIF4_ENABLE_ALL */
327 #define ibl_BOOT_EMIF4_ENABLE_ALL 0x007fffff
329 /* @} */
332 /**
333 * @defgroup iblEmifType Defines the EMIF4 type on a device
334 *
335 * @ingroup iblEmifType
336 * @{
337 */
338 /** @def ibl_EMIF_TYPE_31 */
339 #define ibl_EMIF_TYPE_31 31
341 /** @def ibl_EMIF_TYPE_40 */
342 #define ibl_EMIF_TYPE_40 40
344 /* @} */
346 /**
347 * @brief
348 * This structure is used to configure the DDR interface
349 *
350 * @details
351 * The DDR configuration parameters are setup
352 *
353 */
354 typedef struct idblDdr_s
355 {
356 bool configDdr; /**< Set to non-zero to enable EMIF configuration */
358 union {
360 iblEmif3p1_t emif3p1; /**< Configuration of devices with emif controller version 3.1 */
361 iblEmif4p0_t emif4p0; /**< Configuration of devices with emif controller version 4.0 */
362 } uEmif;
364 } iblDdr_t;
366 /**
367 * @brief
368 * This structure is used to identify binary blob load parameters.
369 *
370 * @details
371 * Since binary blob is formatless the start address, size and branch to address
372 * can be specified. In the case of network boot, boot will terminate when no
373 * more data is received (or timed out), even if the size is not reached.
374 */
375 typedef struct iblBinBlob_s
376 {
377 uint32 startAddress; /**< Where the loaded data is placed */
378 uint32 sizeBytes; /**< How much data to load */
379 uint32 branchAddress; /**< Where to branch to when the load is complete */
381 } iblBinBlob_t;
383 /**
384 * @brief
385 * This structure is used to control the operation of the ibl ethernet boot.
386 *
387 * @details
388 * The ethernet port and bootp request are controlled through this structure.
389 */
390 typedef struct iblEth_s
391 {
392 bool doBootp; /**< If true a bootp request is generated. If false the @ref iblEthBootInfo_t
393 table must be populated before the ibl begins execution */
394 bool useBootpServerIp; /**< If TRUE then the server IP received from the bootp server
395 is used, if FALSE the one in the ethInfo field is used */
396 bool useBootpFileName; /**< If TRUE then the file name received from the bootp server
397 is used, if FALSE the one in the ethInfo field is used */
398 int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
400 iblBinBlob_t blob; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
402 iblEthBootInfo_t ethInfo; /**< Low level ethernet information */
404 } iblEth_t;
407 /**
408 * @brief
409 * This structure is used to control the operation of the ibl sgmii ports
410 *
411 * @details
412 * The physical register configuration is provided
413 */
414 typedef struct iblSgmii_s
415 {
416 bool configure; /**< Set to false to disable configuration */
417 uint32 adviseAbility; /**< The advise ability register */
418 uint32 control; /**< The control register */
419 uint32 txConfig; /**< Serdes Tx config */
420 uint32 rxConfig; /**< Serdes Rx config */
421 uint32 auxConfig; /**< Serdes Aux config */
423 } iblSgmii_t;
426 /**
427 * @def ibl_N_ETH_PORTS
428 */
429 #define ibl_N_ETH_PORTS 2 /**< The number of ethernet port configurations available */
431 /**
432 * @def ibl_N_MDIO_CFGS
433 */
434 #define ibl_N_MDIO_CFGS 16 /**< The maximum number of mdio configurations */
437 /**
438 * @brief
439 * This structure is used to configure phys through the mdio interface
440 *
441 * @details
442 * Defines optional configuration through MDIO.
443 *
444 * The mdio transaction values are mapped as follows:
445 *
446 * /-------------------------------------------------------------\
447 * | 31 | 30 | 29 26 | 25 21 | 20 16 | 15 0|
448 * | rsvd | write | rsvd | register | phy addr | data |
449 * \-------------------------------------------------------------/
450 */
451 typedef struct iblMdio_s
452 {
453 int16 nMdioOps; /**< The number of mdio writes to perform */
454 uint16 mdioClkDiv; /**< The divide down of the mac clock which drives the mdio */
456 uint32 interDelay; /**< The number of cpu cycles to wait between mdio writes */
458 uint32 mdio[ibl_N_MDIO_CFGS]; /* The MDIO transactions */
460 } iblMdio_t;
462 /**
463 * @def ibl_N_ECC_BYTES
464 */
465 #define ibl_N_ECC_BYTES 10 /**< The number of ECC bytes to be computed for each page */
467 /**
468 * @def ibl_N_BAD_BLOCK_MARKER
469 */
470 #define ibl_N_BAD_BLOCK_PAGE 2 /**< The number of pages in each block that has the bad block marker */
472 /**
473 * @brief
474 * This structure defines the physical parameters of the NAND device
475 */
476 typedef struct nandDevInfo_s
477 {
478 uint32 busWidthBits; /**< 8 or 16 bit bus width */
479 uint32 pageSizeBytes; /**< The size of each page */
480 uint32 pageEccBytes; /**< Number of ecc bytes in each page */
481 uint32 pagesPerBlock; /**< The number of pages in each block */
482 uint32 totalBlocks; /**< The total number of blocks in a device */
484 uint32 addressBytes; /**< Number of bytes in the address */
485 bool lsbFirst; /**< Set to true if the LSB is output first, otherwise msb is first */
486 uint32 blockOffset; /**< Address bits which specify the block number */
487 uint32 pageOffset; /**< Address bits which specify the page number */
488 uint32 columnOffset; /**< Address bits which specify the column number */
490 uint8 eccBytesIdx[ibl_N_ECC_BYTES];
491 /**< Index of each ECC byte in each page data */
492 uint8 badBlkMarkIdx[ibl_N_BAD_BLOCK_PAGE];
493 /**< Index of bad block marker in each page data */
495 uint8 resetCommand; /**< The command to reset the flash */
496 uint8 readCommandPre; /**< The read command sent before the address */
497 uint8 readCommandPost; /**< The read command sent after the address */
498 bool postCommand; /**< If TRUE the post command is sent */
500 } nandDevInfo_t;
503 /**
504 * @def ibl_N_ENDIANS
505 */
506 #define ibl_N_ENDIANS 2 /**< The number of endians supported */
508 #define ibl_ENDIAN_BIG 0 /**< Big endian */
509 #define ibl_ENDIAN_LITTLE 1 /**< Little endian */
511 /**
512 * @def ibl_N_IMAGES
513 */
514 #define ibl_N_IMAGES 2 /**< The number of boot images supported on the same device */
516 /**
517 * @brief
518 * This structure is used to control the operation of the NAND boot
519 *
520 */
521 typedef struct iblNand_s
522 {
524 int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
525 uint32 bootAddress[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< The start address of each image for booting */
526 int32 interface; /**< The nand interface @ref iblPmemf */
527 iblBinBlob_t blob[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
530 nandDevInfo_t nandInfo; /** Low level device info */
532 } iblNand_t;
534 /**
535 * @brief
536 * Nor boot configuration.
537 */
538 typedef struct iblNor_s
539 {
540 int32 bootFormat; /**< The format of the boot data file. @ref iblBootFormats */
541 uint32 bootAddress[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< The start address for booting */
542 int32 interface; /**< The nor interface. @ref iblPmemIf */
543 iblBinBlob_t blob[ibl_N_ENDIANS][ibl_N_IMAGES]; /**< Used only if the format is ibl_BOOT_FORMAT_BBLOB */
545 } iblNor_t;
547 extern uint32 iblEndianIdx;
548 extern uint32 iblImageIdx;
550 /**
551 * @defgroup iblPmemIf defines the interfaces used for NOR memory. Not all values are
552 * valid for all devices
553 *
554 * @ingroup iblPmemIf
555 * @{
556 */
558 /** @def ibl_PMEM_IF_GPIO - GPIO interface */
559 #define ibl_PMEM_IF_GPIO 0
561 /** @def ibl_PMEM_IF_CHIPSEL_2 */
562 #define ibl_PMEM_IF_CHIPSEL_2 2 /* EMIF interface using chip select 2, no wait enabled */
564 /** @def ibl_PMEM_IF_CHIPSEL_3 */
565 #define ibl_PMEM_IF_CHIPSEL_3 3 /* EMIF interface using chip select 3, no wait enabled */
567 /** @def ibl_PMEM_IF_CHIPSEL_4 */
568 #define ibl_PMEM_IF_CHIPSEL_4 4 /* EMIF interface using chip select 4 */
570 /** @def ibl_PMEM_IF_CHIPSEL_5 */
571 #define ibl_PMEM_IF_CHIPSEL_5 5 /* EMIF interface using chip select 5 */
573 /** @def ibl_PMEM_IF_SPI */
574 #define ibl_PMEM_IF_SPI 100 /* Interface through SPI */
576 /* @} */
579 /**
580 * @brief
581 * EMIF (nand/nor) configuration
582 */
583 typedef struct iblEmif_s {
585 int16 csSpace; /**< Chip select space, @ref iblPmemIf */
586 int16 busWidth; /**< Bus width, bits */
587 bool waitEnable; /**< Valid only for NOR devices */
589 } iblEmif_t;
591 /**
592 * @brief
593 * The maximum number of chip select spaces for emif boot (not ddr) configuration
594 */
595 #define ibl_MAX_EMIF_PMEM 2
598 /**
599 * @brief
600 * SPI configuration used for either NOR or NAND
601 */
602 typedef struct iblSpi_s
603 {
604 int16 addrWidth; /**< 16 or 24 are the only valid values */
605 int16 nPins; /**< 4 or 5 are the only valid values */
606 int16 mode; /**< Clock / data polarities (valid values 0-3) */
607 int16 csel; /**< Chip select value (5 pin). Only 0b10 and 0b01 are valid */
608 uint16 c2tdelay; /**< Setup time between chip select and the transaction */
609 uint16 busFreqMHz; /**< Bus speed */
611 } iblSpi_t;
615 /**
616 * @brief
617 * This structure is used to control the programming of the device PLL
618 *
619 * @details
620 * The system PLLs are optionally configured
621 */
622 typedef struct iblPll_s {
624 bool doEnable; /**< If true the PLL is configured */
626 Uint32 prediv; /**< The pll pre-divisor */
627 Uint32 mult; /**< The pll multiplier */
628 Uint32 postdiv; /**< The pll post divider */
630 Uint32 pllOutFreqMhz; /**< The resulting output frequency, required for timer setup */
632 } iblPll_t;
635 /**
636 * @defgroup iblPllNum
637 *
638 * @ingroup iblPllNum
639 * @{
640 *
641 * @def ibl_MAIN_PLL
642 */
643 #define ibl_MAIN_PLL 0 /**< The main cpu pll */
645 /**
646 * @def ibl_DDR_PLL
647 */
648 #define ibl_DDR_PLL 1 /**< The ddr pll */
650 /**
651 * @def ibl_NET_PLL
652 */
653 #define ibl_NET_PLL 2 /**< The network pll */
655 /**
656 * @def the number of PLL configuration entries in the table
657 */
658 #define ibl_N_PLL_CFGS (ibl_NET_PLL + 1)
660 /* @} */
663 /**
664 * @def iblBoot_t
665 * Configures an ibl boot attempt
666 *
667 * @details
668 * The ibl allows for the configuration for multiple boot attempts. This structure is
669 * used to configure the ibl boot attempt.
670 */
671 typedef struct iblBoot_s
672 {
674 int32 bootMode; /**< Identifies the boot mode @ref iblBootModes */
676 uint32 priority; /**< The boot priority. @ref iblPeriphPriority */
677 int32 port; /**< The port to use, or @ref ibl_PORT_FROM_RBL */
679 union {
681 iblEth_t ethBoot; /**< Ethernet boot configuration. @ref iblEth_t */
683 iblNand_t nandBoot; /**< NAND boot configuration @ref iblNand_t */
685 iblNor_t norBoot; /**< NOR boot configuration @ref iblNor_t */
687 } u;
689 } iblBoot_t;
692 /**
693 * @def ibl_MAGIC_VALUE
694 */
695 #define ibl_MAGIC_VALUE 0xCEC11EBC /**< Indicates that the configuration table is valid */
697 /**
698 * @def ibl_EVM_TYPE
699 */
700 #define ibl_EVM_C6455L 0x10 /**< C6455 Low Cost EVM */
701 #define ibl_EVM_C6457L 0x20 /**< C6457 Low Cost EVM */
702 #define ibl_EVM_C6472L 0x30 /**< C6472 Low Cost EVM */
703 #define ibl_EVM_C6474L 0x40 /**< C6474 Low Cost EVM */
704 #define ibl_EVM_C6474M 0x41 /**< C6474 Mez EVM */
705 #define ibl_EVM_C6670L 0x50 /**< C6670 Low Cost EVM */
706 #define ibl_EVM_C6678L 0x60 /**< C6678 Low Cost EVM */
707 #define ibl_EVM_C6657L 0x70 /**< C6657 Low Cost EVM */
708 #define ibl_EVM_TCI6634K2K 0x80 /**< TCI6634K2K Low Cost EVM */
710 /**
711 * @brief
712 * The main configuration/control structure for the ibl
713 *
714 * @details
715 * The operation of the ibl is configured/controlled based on the values in this structure.
716 * This structure resides at a fixed location in the memory map. It can be changed during
717 * the boot operation itself by loading new values into it, but these changes must occur
718 * as part of the boot process itself (not through an asynchronous write through a master
719 * peripheral).
720 *
721 * Each boot mode is assigned a priority, with lower values indicating a higher
722 * priority. The lowest valid priority is @ref ibl_LOWEST_BOOT_PRIORITY, and the value
723 * @ref ibl_DEVICE_NOBOOT indicates no boot will be attempted on that peripheral.
724 */
725 typedef struct ibl_s
726 {
727 uint32 iblMagic; /**< @ref ibl_MAGIC_VALUE */
729 iblPll_t pllConfig[ibl_N_PLL_CFGS]; /**< PLL Configuration. @ref iblPll_t */
731 iblDdr_t ddrConfig; /**< DDR configuration @ref iblDdr_t */
733 iblSgmii_t sgmiiConfig[ibl_N_ETH_PORTS]; /**< SGMII boot configuration. @ref iblSgmii_t */
735 iblMdio_t mdioConfig; /**< MDIO configuration. @ref iblMdio_t */
737 iblSpi_t spiConfig; /**< SPI configuration @ref iblSpi_s */
739 iblEmif_t emifConfig[ibl_MAX_EMIF_PMEM]; /**< EMIF (nand/nor, not ddr) configuration. @ref iblEmif_t */
741 iblBoot_t bootModes[ibl_N_BOOT_MODES]; /**< Boot configuration */
743 uint16 iblEvmType; /**< @ref ibl_EVM_TYPE */
745 uint16 chkSum; /**< Ones complement checksum over the whole config structure */
747 } ibl_t;
750 extern ibl_t ibl;
753 /**
754 * @defgroup iblActiveDevice
755 *
756 * @ingroup iblActiveDevice
757 * @{
758 * @def ibl_ACTIVE_DEVICE_ETH
759 */
760 #define ibl_ACTIVE_DEVICE_ETH 100 /**< Data received through an ethernet interface */
762 /**
763 * @def ibl_ACTIVE_DEVICE_EMIF
764 */
765 #define ibl_ACTIVE_DEVICE_EMIF 101 /**< Data read through an EMIF interface */
767 /**
768 * @def ibl_ACTIVE_DEVICE_I2C
769 */
770 #define ibl_ACTIVE_DEVICE_I2C 102 /**< Data read through an I2C interface */
772 /**
773 * @def ibl_ACTIVE_DEVICE_SPI
774 */
775 #define ibl_ACTIVE_DEVICE_SPI 103 /**< Data read through an SPI interface */
777 /* @} */
780 /**
781 * @defgroup iblFailCode
782 *
783 * @ingroup iblFailCode
784 * @{
785 * @def ibl_FAIL_CODE_INVALID_I2C_ADDRESS
786 */
787 #define ibl_FAIL_CODE_INVALID_I2C_ADDRESS 700 /**< Invalid i2c eeprom address encountered */
789 /**
790 * @def ibl_FAIL_CODE_BTBL_FAIL
791 */
792 #define ibl_FAIL_CODE_BTBL_FAIL 701 /**< Boot table processing function error */
794 /**
795 * @def ibl_FAIL_CODE_PA
796 */
797 #define ibl_FAIL_CODE_PA 702 /**< Packet Accelerator setup failed */
800 /**
801 * @def ibl_FAIL_CODE_SPI_PARAMS
802 */
803 #define ibl_FAIL_CODE_SPI_PARAMS 703 /**< Invalid SPI configuration found */
805 /**
806 * @def ibl_FAIL_CODE_INVALID_INIT_DEVICE
807 */
808 #define ibl_FAIL_CODE_INVALID_INIT_DEVICE 704 /**< Second stage boot device specified is invalid */
810 /**
811 * @def ibl_FAIL_CODE_INVALID_SPI_ADDRESS
812 */
813 #define ibl_FAIL_CODE_INVALID_SPI_ADDRESS 705 /**< Invalid data address specified on SPI */
815 /**
816 * @def ibl_FAIL_CODE_PERIPH_POWER_UP
817 */
818 #define ibl_FAIL_CODE_PERIPH_POWER_UP 706 /**< Boot peripheral failed to power up */
820 /**
821 * @def ibl_FAIL_CODE_INVALID_NAND_PERIPH
822 */
823 #define ibl_FAIL_CODE_INVALID_NAND_PERIPH 707 /**< Invalid nand boot peripheral specified */
825 /**
826 * @def ibl_FAIL_CODE_NO_EMIF_CFG
827 */
828 #define ibl_FAIL_CODE_NO_EMIF_CFG 708 /**< No emif configuration found to match specified cs space */
830 /**
831 * @def ibl_FAIL_CODE_EMIF_CFG_FAIL
832 */
833 #define ibl_FAIL_CODE_EMIF_CFG_FAIL 709 /**< Hardware setup of emif failed */
835 /* @} */
838 /**
839 * @brief
840 * Provide status on the boot operation
841 *
842 * @details
843 * Run time status of the IBL is provided to aid in debugging
844 *
845 */
846 typedef struct iblStatus_s
847 {
848 uint32 iblMagic; /**< The @ref ibl_MAGIC_VALUE is placed here to indicate the boot has begun */
850 uint32 iblVersion; /**< The version number. MSB = major, SMSB = minor, SLSB = minor minor LSB= tiny */
852 uint32 iblFail; /**< If non-zero the IBL has encountered a fatal error */
854 uint32 i2cRetries; /**< Count of I2C read retries */
855 uint32 i2cDataRetries; /**< Number of retries while reading block data from the i2c */
857 uint32 spiRetries; /**< Count of SPI read retries */
858 uint32 spiDataRetries; /**< Number of retries while reading block data from the spi */
860 uint32 magicRetries; /**< Count of I2C/SPI re-reads because the magic number was incorrect */
861 uint32 mapSizeFail; /**< Number of times an invalid map table size was read from the i2c/spi */
862 uint32 mapRetries; /**< Number of times the checksum failed on the read of the i2c/spi map */
864 int32 heartBeat; /**< An increasing value as long as the boot code is running */
866 int32 activeBoot; /**< Describes the active boot mode @ref iblBootModes */
867 int32 activeDevice; /**< Describes the active boot peripheral device @ref iblActiveDevice */
868 int32 activeFileFormat; /**< Describes the format being decoded */
870 uint32 autoDetectFailCnt; /**< Counts the number of times an auto detect of the data format failed */
871 uint32 nameDetectFailCnt; /**< Counts the number of times an name detect of the data format failed */
873 uint32 invalidDataFormatSpec; /**< Counts the number of times the main boot found an invalid boot format request */
875 uint32 exitAddress; /**< If non-zero the IBL exited and branched to this address */
877 iblEthBootInfo_t ethParams; /**< Last ethernet boot attemp parameters */
879 } iblStatus_t;
881 extern iblStatus_t iblStatus;
884 /**
885 * @brief
886 * The ibl boot map structure
887 *
888 * @details
889 * The ibl boot device contains a structure which identifies the location of the big and little
890 * endian ibl images on the external device.
891 */
892 typedef struct iblBootMap_s
893 {
894 uint16 length; /**< Size of the structure in bytes */
895 uint16 chkSum; /**< Value which makes the ones complement checksum over the block equal to 0 or -0 */
897 uint32 addrLe; /**< Base address of the boot tables for the little endian image */
898 uint32 configLe; /**< Base address of the ibl structure for use with the little endian image */
900 uint32 addrBe; /**< Base address of the boot tables for the big endian image */
901 uint32 configBe; /**< Base address of the ibl structure for use with the big endian image */
903 } iblBootMap_t;
906 ibl_t c6455_ibl_config(void);
907 ibl_t c6474_ibl_config(void);
908 ibl_t c6474l_ibl_config(void);
909 ibl_t c6457_ibl_config(void);
910 ibl_t c6472_ibl_config(void);
911 ibl_t c6678_ibl_config(void);
912 ibl_t c6670_ibl_config(void);
913 ibl_t c6657_ibl_config(void);
914 ibl_t tci6634k2k_ibl_config(void);
919 #endif /* IBL_H */