Defines |
#define | ibl_EMIF4_ENABLE_sdRamConfig (1 << 0) |
#define | ibl_EMIF4_ENABLE_sdRamConfig2 (1 << 1) |
#define | ibl_EMIF4_ENABLE_sdRamRefreshCtl (1 << 2) |
#define | ibl_EMIF4_ENABLE_sdRamTiming1 (1 << 3) |
#define | ibl_EMIF4_ENABLE_sdRamTiming2 (1 << 4) |
#define | ibl_EMIF4_ENABLE_sdRamTiming3 (1 << 5) |
#define | ibl_EMIF4_ENABLE_lpDdrNvmTiming (1 << 6) |
#define | ibl_EMIF4_ENABLE_powerManageCtl (1 << 7) |
#define | ibl_EMIF4_ENABLE_iODFTTestLogic (1 << 8) |
#define | ibl_EMIF4_ENABLE_performCountCfg (1 << 9) |
#define | ibl_EMIF4_ENABLE_performCountMstRegSel (1 << 10) |
#define | ibl_EMIF4_ENABLE_readIdleCtl (1 << 11) |
#define | ibl_EMIF4_ENABLE_sysVbusmIntEnSet (1 << 12) |
#define | ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg (1 << 13) |
#define | ibl_EMIF4_ENABLE_tempAlterCfg (1 << 14) |
#define | ibl_EMIF4_ENABLE_ddrPhyCtl1 (1 << 15) |
#define | ibl_EMIF4_ENABLE_ddrPhyCtl2 (1 << 16) |
#define | ibl_EMIF4_ENABLE_priClassSvceMap (1 << 17) |
#define | ibl_EMIF4_ENABLE_mstId2ClsSvce1Map (1 << 18) |
#define | ibl_EMIF4_ENABLE_mstId2ClsSvce2Map (1 << 11) |
#define | ibl_EMIF4_ENABLE_eccCtl (1 << 19) |
#define | ibl_EMIF4_ENABLE_eccRange1 (1 << 20) |
#define | ibl_EMIF4_ENABLE_eccRange2 (1 << 21) |
#define | ibl_EMIF4_ENABLE_rdWrtExcThresh (1 << 22) |
#define | ibl_BOOT_EMIF4_ENABLE_ALL 0x007fffff |