IBL Configuration
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00001 /* 00002 * 00003 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 00004 * 00005 * 00006 * Redistribution and use in source and binary forms, with or without 00007 * modification, are permitted provided that the following conditions 00008 * are met: 00009 * 00010 * Redistributions of source code must retain the above copyright 00011 * notice, this list of conditions and the following disclaimer. 00012 * 00013 * Redistributions in binary form must reproduce the above copyright 00014 * notice, this list of conditions and the following disclaimer in the 00015 * documentation and/or other materials provided with the 00016 * distribution. 00017 * 00018 * Neither the name of Texas Instruments Incorporated nor the names of 00019 * its contributors may be used to endorse or promote products derived 00020 * from this software without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 00023 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00024 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 00025 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 00026 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 00027 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 00028 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 00029 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 00030 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00031 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00032 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00033 * 00034 */ 00035 00036 00037 00038 /******************************************************************************************************** 00039 * FILE PURPOSE: IBL configuration and control definitions 00040 ******************************************************************************************************** 00041 * FILE NAME: ibl.h 00042 * 00043 * DESCRIPTION: Defines the data structure used to handle initial configuration and control 00044 * of the ibl. This data structure resides at a fixed location in the device memory 00045 * map. It is initially populated either during the rom boot. The table can be 00046 * over-written during the ibl process to redirect the boot. For example the ibl 00047 * can initially load from an i2c which repopulates this table with parameters 00048 * for an ethernet boot. 00049 * 00050 * @file ibl.h 00051 * 00052 * @brief 00053 * This file defines the configuration and control of the IBL 00054 * 00055 * 00056 ********************************************************************************************************/ 00057 #ifndef IBL_H 00058 #define IBL_H 00059 00060 #include "types.h" 00061 00062 00063 #define ibl_MAKE_VERSION(a,b,c,d) ((a << 24) | (b << 16) | (c << 8) | (d << 0)) 00064 00065 00070 #define ibl_VERSION ibl_MAKE_VERSION(1,0,0,4) 00071 00072 00080 #define ibl_BOOT_MODE_TFTP 10 /* Boot through a tftp interface */ 00081 00082 /* @def ibl_BOOT_MODE_NAND */ 00083 #define ibl_BOOT_MODE_NAND 11 /* Boot through a nand interface */ 00084 00085 /* @def ibl_BOOT_MODE_NOR */ 00086 #define ibl_BOOT_MODE_NOR 12 /* Boot through a nor (or flash) interface */ 00087 00088 /* @def ibl_BOOT_MODE_NONE */ 00089 #define ibl_BOOT_MODE_NONE 13 /* Boot mode selection is inactive */ 00090 00091 /* @} */ 00092 00098 #define ibl_N_BOOT_MODES 3 00099 00100 /* Information used to make generate a bootp request */ 00108 typedef struct iblBootp_s 00109 { 00110 uint8 hwAddress[6]; 00113 uint8 ipDest[4]; 00116 } iblBootp_t; 00117 00118 00126 typedef struct iblEthBootInfo_s 00127 { 00128 uint8 ipAddr[4]; 00129 uint8 serverIp[4]; 00130 uint8 gatewayIp[4]; 00131 uint8 netmask[4]; 00132 uint8 hwAddress[6]; 00133 char8 fileName[64]; 00135 } iblEthBootInfo_t; 00136 00137 00141 #define ibl_ETH_PORT_FROM_RBL -1 00147 #define ibl_PORT_SWITCH_ALL -2 00157 #define ibl_BOOT_FORMAT_AUTO 0 00158 #define ibl_BOOT_FORMAT_NAME 1 00159 #define ibl_BOOT_FORMAT_BIS 2 00160 #define ibl_BOOT_FORMAT_COFF 3 00161 #define ibl_BOOT_FORMAT_ELF 4 00162 #define ibl_BOOT_FORMAT_BBLOB 5 00163 #define ibl_BOOT_FORMAT_BTBL 6 00165 /* @} */ 00166 00174 #define ibl_LOWEST_PRIORITY 10 00179 #define ibl_HIGHEST_PRIORITY 1 00184 #define ibl_DEVICE_NOBOOT 20 00186 /* @} */ 00187 00188 00196 typedef struct iblEmif3p1_s 00197 { 00198 uint32 sdcfg; 00199 uint32 sdrfc; 00200 uint32 sdtim1; 00201 uint32 sdtim2; 00202 uint32 dmcctl; 00204 } iblEmif3p1_t; 00205 00206 00214 typedef struct iblEmif4p0_s 00215 { 00216 uint32 registerMask; 00217 uint32 sdRamConfig; 00218 uint32 sdRamConfig2; 00219 uint32 sdRamRefreshCtl; 00220 uint32 sdRamTiming1; 00221 uint32 sdRamTiming2; 00222 uint32 sdRamTiming3; 00223 uint32 lpDdrNvmTiming; 00224 uint32 powerManageCtl; 00225 uint32 iODFTTestLogic; 00226 uint32 performCountCfg; 00227 uint32 performCountMstRegSel; 00228 uint32 readIdleCtl; 00229 uint32 sysVbusmIntEnSet; 00230 uint32 sdRamOutImpdedCalCfg; 00231 uint32 tempAlterCfg; 00232 uint32 ddrPhyCtl1; 00233 uint32 ddrPhyCtl2; 00234 uint32 priClassSvceMap; 00235 uint32 mstId2ClsSvce1Map; 00236 uint32 mstId2ClsSvce2Map; 00237 uint32 eccCtl; 00238 uint32 eccRange1; 00239 uint32 eccRange2; 00240 uint32 rdWrtExcThresh; 00242 } iblEmif4p0_t; 00243 00244 00252 #define ibl_EMIF4_ENABLE_sdRamConfig (1 << 0) 00253 00255 #define ibl_EMIF4_ENABLE_sdRamConfig2 (1 << 1) 00256 00258 #define ibl_EMIF4_ENABLE_sdRamRefreshCtl (1 << 2) 00259 00261 #define ibl_EMIF4_ENABLE_sdRamTiming1 (1 << 3) 00262 00264 #define ibl_EMIF4_ENABLE_sdRamTiming2 (1 << 4) 00265 00267 #define ibl_EMIF4_ENABLE_sdRamTiming3 (1 << 5) 00268 00270 #define ibl_EMIF4_ENABLE_lpDdrNvmTiming (1 << 6) 00271 00273 #define ibl_EMIF4_ENABLE_powerManageCtl (1 << 7) 00274 00276 #define ibl_EMIF4_ENABLE_iODFTTestLogic (1 << 8) 00277 00279 #define ibl_EMIF4_ENABLE_performCountCfg (1 << 9) 00280 00282 #define ibl_EMIF4_ENABLE_performCountMstRegSel (1 << 10) 00283 00285 #define ibl_EMIF4_ENABLE_readIdleCtl (1 << 11) 00286 00288 #define ibl_EMIF4_ENABLE_sysVbusmIntEnSet (1 << 12) 00289 00291 #define ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg (1 << 13) 00292 00294 #define ibl_EMIF4_ENABLE_tempAlterCfg (1 << 14) 00295 00297 #define ibl_EMIF4_ENABLE_ddrPhyCtl1 (1 << 15) 00298 00300 #define ibl_EMIF4_ENABLE_ddrPhyCtl2 (1 << 16) 00301 00303 #define ibl_EMIF4_ENABLE_priClassSvceMap (1 << 17) 00304 00306 #define ibl_EMIF4_ENABLE_mstId2ClsSvce1Map (1 << 18) 00307 00309 #define ibl_EMIF4_ENABLE_mstId2ClsSvce2Map (1 << 11) 00310 00312 #define ibl_EMIF4_ENABLE_eccCtl (1 << 19) 00313 00315 #define ibl_EMIF4_ENABLE_eccRange1 (1 << 20) 00316 00318 #define ibl_EMIF4_ENABLE_eccRange2 (1 << 21) 00319 00321 #define ibl_EMIF4_ENABLE_rdWrtExcThresh (1 << 22) 00322 00324 #define ibl_BOOT_EMIF4_ENABLE_ALL 0x007fffff 00325 00326 /* @} */ 00327 00328 00336 #define ibl_EMIF_TYPE_31 31 00337 00339 #define ibl_EMIF_TYPE_40 40 00340 00341 /* @} */ 00342 00351 typedef struct idblDdr_s 00352 { 00353 bool configDdr; 00355 union { 00356 00357 iblEmif3p1_t emif3p1; 00358 iblEmif4p0_t emif4p0; 00359 } uEmif; 00360 00361 } iblDdr_t; 00362 00372 typedef struct iblBinBlob_s 00373 { 00374 uint32 startAddress; 00375 uint32 sizeBytes; 00376 uint32 branchAddress; 00378 } iblBinBlob_t; 00379 00387 typedef struct iblEth_s 00388 { 00389 bool doBootp; 00391 bool useBootpServerIp; 00393 bool useBootpFileName; 00395 int32 bootFormat; 00397 iblBinBlob_t blob; 00399 iblEthBootInfo_t ethInfo; 00401 } iblEth_t; 00402 00403 00411 typedef struct iblSgmii_s 00412 { 00413 bool configure; 00414 uint32 adviseAbility; 00415 uint32 control; 00416 uint32 txConfig; 00417 uint32 rxConfig; 00418 uint32 auxConfig; 00420 } iblSgmii_t; 00421 00422 00426 #define ibl_N_ETH_PORTS 2 00431 #define ibl_N_MDIO_CFGS 16 00448 typedef struct iblMdio_s 00449 { 00450 int16 nMdioOps; 00451 uint16 mdioClkDiv; 00453 uint32 interDelay; 00455 uint32 mdio[ibl_N_MDIO_CFGS]; /* The MDIO transactions */ 00456 00457 } iblMdio_t; 00458 00462 #define ibl_N_ECC_BYTES 10 00467 #define ibl_N_BAD_BLOCK_PAGE 2 00473 typedef struct nandDevInfo_s 00474 { 00475 uint32 busWidthBits; 00476 uint32 pageSizeBytes; 00477 uint32 pageEccBytes; 00478 uint32 pagesPerBlock; 00479 uint32 totalBlocks; 00481 uint32 addressBytes; 00482 bool lsbFirst; 00483 uint32 blockOffset; 00484 uint32 pageOffset; 00485 uint32 columnOffset; 00487 uint8 eccBytesIdx[ibl_N_ECC_BYTES]; 00489 uint8 badBlkMarkIdx[ibl_N_BAD_BLOCK_PAGE]; 00492 uint8 resetCommand; 00493 uint8 readCommandPre; 00494 uint8 readCommandPost; 00495 bool postCommand; 00497 } nandDevInfo_t; 00498 00499 00503 #define ibl_N_ENDIANS 2 00505 #define ibl_ENDIAN_BIG 0 00506 #define ibl_ENDIAN_LITTLE 1 00511 #define ibl_N_IMAGES 2 00518 typedef struct iblNand_s 00519 { 00520 00521 int32 bootFormat; 00522 uint32 bootAddress[ibl_N_ENDIANS][ibl_N_IMAGES]; 00523 int32 interface; 00524 iblBinBlob_t blob[ibl_N_ENDIANS][ibl_N_IMAGES]; 00527 nandDevInfo_t nandInfo; 00529 } iblNand_t; 00530 00535 typedef struct iblNor_s 00536 { 00537 int32 bootFormat; 00538 uint32 bootAddress[ibl_N_ENDIANS][ibl_N_IMAGES]; 00539 int32 interface; 00540 iblBinBlob_t blob[ibl_N_ENDIANS][ibl_N_IMAGES]; 00542 } iblNor_t; 00543 00544 extern uint32 iblEndianIdx; 00545 extern uint32 iblImageIdx; 00546 00556 #define ibl_PMEM_IF_GPIO 0 00557 00559 #define ibl_PMEM_IF_CHIPSEL_2 2 /* EMIF interface using chip select 2, no wait enabled */ 00560 00562 #define ibl_PMEM_IF_CHIPSEL_3 3 /* EMIF interface using chip select 3, no wait enabled */ 00563 00565 #define ibl_PMEM_IF_CHIPSEL_4 4 /* EMIF interface using chip select 4 */ 00566 00568 #define ibl_PMEM_IF_CHIPSEL_5 5 /* EMIF interface using chip select 5 */ 00569 00571 #define ibl_PMEM_IF_SPI 100 /* Interface through SPI */ 00572 00573 /* @} */ 00574 00575 00580 typedef struct iblEmif_s { 00581 00582 int16 csSpace; 00583 int16 busWidth; 00584 bool waitEnable; 00586 } iblEmif_t; 00587 00592 #define ibl_MAX_EMIF_PMEM 2 00593 00594 00599 typedef struct iblSpi_s 00600 { 00601 int16 addrWidth; 00602 int16 nPins; 00603 int16 mode; 00604 int16 csel; 00605 uint16 c2tdelay; 00606 uint16 busFreqMHz; 00608 } iblSpi_t; 00609 00610 00611 00619 typedef struct iblPll_s { 00620 00621 bool doEnable; 00623 Uint32 prediv; 00624 Uint32 mult; 00625 Uint32 postdiv; 00627 Uint32 pllOutFreqMhz; 00629 } iblPll_t; 00630 00631 00640 #define ibl_MAIN_PLL 0 00645 #define ibl_DDR_PLL 1 00650 #define ibl_NET_PLL 2 00658 #define ibl_N_PLL_CFGS (ibl_NET_PLL + 1) 00659 00660 /* @} */ 00661 00662 00671 typedef struct iblBoot_s 00672 { 00673 00674 int32 bootMode; 00676 uint32 priority; 00677 int32 port; 00679 union { 00680 00681 iblEth_t ethBoot; 00683 iblNand_t nandBoot; 00685 iblNor_t norBoot; 00687 } u; 00688 00689 } iblBoot_t; 00690 00691 00695 #define ibl_MAGIC_VALUE 0xCEC11EBC 00700 #define ibl_EVM_C6455L 0x10 00701 #define ibl_EVM_C6457L 0x20 00702 #define ibl_EVM_C6472L 0x30 00703 #define ibl_EVM_C6474L 0x40 00704 #define ibl_EVM_C6474M 0x41 00705 #define ibl_EVM_C6670L 0x50 00706 #define ibl_EVM_C6678L 0x60 00724 typedef struct ibl_s 00725 { 00726 uint32 iblMagic; 00728 iblPll_t pllConfig[ibl_N_PLL_CFGS]; 00730 iblDdr_t ddrConfig; 00732 iblSgmii_t sgmiiConfig[ibl_N_ETH_PORTS]; 00734 iblMdio_t mdioConfig; 00736 iblSpi_t spiConfig; 00738 iblEmif_t emifConfig[ibl_MAX_EMIF_PMEM]; 00740 iblBoot_t bootModes[ibl_N_BOOT_MODES]; 00742 uint16 iblEvmType; 00744 uint16 chkSum; 00746 } ibl_t; 00747 00748 00749 extern ibl_t ibl; 00750 00751 00759 #define ibl_ACTIVE_DEVICE_ETH 100 00764 #define ibl_ACTIVE_DEVICE_EMIF 101 00769 #define ibl_ACTIVE_DEVICE_I2C 102 00774 #define ibl_ACTIVE_DEVICE_SPI 103 00776 /* @} */ 00777 00778 00786 #define ibl_FAIL_CODE_INVALID_I2C_ADDRESS 700 00791 #define ibl_FAIL_CODE_BTBL_FAIL 701 00796 #define ibl_FAIL_CODE_PA 702 00802 #define ibl_FAIL_CODE_SPI_PARAMS 703 00807 #define ibl_FAIL_CODE_INVALID_INIT_DEVICE 704 00812 #define ibl_FAIL_CODE_INVALID_SPI_ADDRESS 705 00817 #define ibl_FAIL_CODE_PERIPH_POWER_UP 706 00822 #define ibl_FAIL_CODE_INVALID_NAND_PERIPH 707 00827 #define ibl_FAIL_CODE_NO_EMIF_CFG 708 00832 #define ibl_FAIL_CODE_EMIF_CFG_FAIL 709 00834 /* @} */ 00835 00836 00845 typedef struct iblStatus_s 00846 { 00847 uint32 iblMagic; 00849 uint32 iblVersion; 00851 uint32 iblFail; 00853 uint32 i2cRetries; 00854 uint32 i2cDataRetries; 00856 uint32 spiRetries; 00857 uint32 spiDataRetries; 00859 uint32 magicRetries; 00860 uint32 mapSizeFail; 00861 uint32 mapRetries; 00863 int32 heartBeat; 00865 int32 activeBoot; 00866 int32 activeDevice; 00867 int32 activeFileFormat; 00869 uint32 autoDetectFailCnt; 00870 uint32 nameDetectFailCnt; 00872 uint32 invalidDataFormatSpec; 00874 uint32 exitAddress; 00876 iblEthBootInfo_t ethParams; 00878 } iblStatus_t; 00879 00880 extern iblStatus_t iblStatus; 00881 00882 00891 typedef struct iblBootMap_s 00892 { 00893 uint16 length; 00894 uint16 chkSum; 00896 uint32 addrLe; 00897 uint32 configLe; 00899 uint32 addrBe; 00900 uint32 configBe; 00902 } iblBootMap_t; 00903 00904 00905 00906 00907 00908 00909 00910 #endif /* IBL_H */