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+<title>IBL Configuration: iblEmif4p0_s Struct Reference</title>
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+ <div id="projectname">IBL Configuration</div>
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+ <li><a href="index.html"><span>Main Page</span></a></li>
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+ <li><a href="classes.html"><span>Data Structure Index</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div>
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">iblEmif4p0_s Struct Reference</div> </div>
+</div>
+<div class="contents">
+<!-- doxytag: class="iblEmif4p0_s" -->
+<p>Emif controller 4.0 configuration.
+ <a href="structibl_emif4p0__s.html#details">More...</a></p>
+
+<p><code>#include <<a class="el" href="ibl_8h_source.html">ibl.h</a>></code></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#afc32bc65ce2cf71dd3c6e30a239af47e">registerMask</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a5faf82fad83d39e53de237a13d512220">sdRamConfig</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a8a03c562a21ec31b59c17c72bcddb4ec">sdRamConfig2</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#afc1d0b4e38a8ce09b240abb20bc60116">sdRamRefreshCtl</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#ae330e2ac1c489536400107dabe14229a">sdRamTiming1</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#ad34082e05339f2632e978dc42389a9e7">sdRamTiming2</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a9bdbcede174de1bd60c4a2d06549d672">sdRamTiming3</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a9f0ea9fb2dde68278b226cf61db7d724">lpDdrNvmTiming</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a8faa1c2c250fd8d50a1821f9f9a4c15f">powerManageCtl</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a6d5eb1a616936e57873af2a648819d2f">iODFTTestLogic</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a779f0a58c5d1cc0e492f24b3f842ddd0">performCountCfg</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#af5754e8493066e1b66dea97161916a14">performCountMstRegSel</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#ae792d7050596145b63d50117d6220de3">readIdleCtl</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#aa6f4e601d939f54af799f78571f24cbc">sysVbusmIntEnSet</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a24b8b8f644cab72d004375d7ef597322">sdRamOutImpdedCalCfg</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#ac27fa6e3bf375487950e5a3b4a429ba7">tempAlterCfg</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a959f7a69fe3191f79cb200263067d3e9">ddrPhyCtl1</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#abc295d552a398f31e636f2dbb9ce180c">ddrPhyCtl2</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#aeee9d593ff0901ec99ca9e7ebb3fa2f6">priClassSvceMap</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a8ed6f7abab17ae59bf2a1cf5169fb3e8">mstId2ClsSvce1Map</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a19116d15b3c25e891b85134f5298af17">mstId2ClsSvce2Map</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a4cc76fb6a01e74434bad174b82485489">eccCtl</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a3416b063ce5e86cf0b99752baed7e978">eccRange1</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a8c9d5f1c8ebd1e746a05915b80e8a0c2">eccRange2</a></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">uint32 </td><td class="memItemRight" valign="bottom"><a class="el" href="structibl_emif4p0__s.html#a512ad045f76a8a93b5bdad6a80cd2454">rdWrtExcThresh</a></td></tr>
+</table>
+<hr/><a name="details" id="details"></a><h2>Detailed Description</h2>
+<div class="textblock"><p>Emif controller 4.0 configuration. </p>
+<p>The parameters are placed directly into the emif controller </p>
+</div><hr/><h2>Field Documentation</h2>
+<a class="anchor" id="a959f7a69fe3191f79cb200263067d3e9"></a><!-- doxytag: member="iblEmif4p0_s::ddrPhyCtl1" ref="a959f7a69fe3191f79cb200263067d3e9" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a959f7a69fe3191f79cb200263067d3e9">ddrPhyCtl1</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>DDR PHY Control 1 Register </p>
+
+</div>
+</div>
+<a class="anchor" id="abc295d552a398f31e636f2dbb9ce180c"></a><!-- doxytag: member="iblEmif4p0_s::ddrPhyCtl2" ref="abc295d552a398f31e636f2dbb9ce180c" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#abc295d552a398f31e636f2dbb9ce180c">ddrPhyCtl2</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>DDR PHY Control 2 Register </p>
+
+</div>
+</div>
+<a class="anchor" id="a4cc76fb6a01e74434bad174b82485489"></a><!-- doxytag: member="iblEmif4p0_s::eccCtl" ref="a4cc76fb6a01e74434bad174b82485489" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a4cc76fb6a01e74434bad174b82485489">eccCtl</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>ECC Control Register </p>
+
+</div>
+</div>
+<a class="anchor" id="a3416b063ce5e86cf0b99752baed7e978"></a><!-- doxytag: member="iblEmif4p0_s::eccRange1" ref="a3416b063ce5e86cf0b99752baed7e978" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a3416b063ce5e86cf0b99752baed7e978">eccRange1</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>ECC Address Range 1 Register </p>
+
+</div>
+</div>
+<a class="anchor" id="a8c9d5f1c8ebd1e746a05915b80e8a0c2"></a><!-- doxytag: member="iblEmif4p0_s::eccRange2" ref="a8c9d5f1c8ebd1e746a05915b80e8a0c2" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a8c9d5f1c8ebd1e746a05915b80e8a0c2">eccRange2</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>ECC Address Range 2 Register </p>
+
+</div>
+</div>
+<a class="anchor" id="a6d5eb1a616936e57873af2a648819d2f"></a><!-- doxytag: member="iblEmif4p0_s::iODFTTestLogic" ref="a6d5eb1a616936e57873af2a648819d2f" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a6d5eb1a616936e57873af2a648819d2f">iODFTTestLogic</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>IODFT Test Logic Global Control Register </p>
+
+</div>
+</div>
+<a class="anchor" id="a9f0ea9fb2dde68278b226cf61db7d724"></a><!-- doxytag: member="iblEmif4p0_s::lpDdrNvmTiming" ref="a9f0ea9fb2dde68278b226cf61db7d724" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a9f0ea9fb2dde68278b226cf61db7d724">lpDdrNvmTiming</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>LPDDR2-NVM Timing Register </p>
+
+</div>
+</div>
+<a class="anchor" id="a8ed6f7abab17ae59bf2a1cf5169fb3e8"></a><!-- doxytag: member="iblEmif4p0_s::mstId2ClsSvce1Map" ref="a8ed6f7abab17ae59bf2a1cf5169fb3e8" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a8ed6f7abab17ae59bf2a1cf5169fb3e8">mstId2ClsSvce1Map</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>Master ID to Class of Service 1 Mapping Register </p>
+
+</div>
+</div>
+<a class="anchor" id="a19116d15b3c25e891b85134f5298af17"></a><!-- doxytag: member="iblEmif4p0_s::mstId2ClsSvce2Map" ref="a19116d15b3c25e891b85134f5298af17" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a19116d15b3c25e891b85134f5298af17">mstId2ClsSvce2Map</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>Master ID to Class of Service 2 Mapping Register </p>
+
+</div>
+</div>
+<a class="anchor" id="a779f0a58c5d1cc0e492f24b3f842ddd0"></a><!-- doxytag: member="iblEmif4p0_s::performCountCfg" ref="a779f0a58c5d1cc0e492f24b3f842ddd0" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a779f0a58c5d1cc0e492f24b3f842ddd0">performCountCfg</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>Performance Counter Config Register </p>
+
+</div>
+</div>
+<a class="anchor" id="af5754e8493066e1b66dea97161916a14"></a><!-- doxytag: member="iblEmif4p0_s::performCountMstRegSel" ref="af5754e8493066e1b66dea97161916a14" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#af5754e8493066e1b66dea97161916a14">performCountMstRegSel</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>Performance Counter Master Region Select Register </p>
+
+</div>
+</div>
+<a class="anchor" id="a8faa1c2c250fd8d50a1821f9f9a4c15f"></a><!-- doxytag: member="iblEmif4p0_s::powerManageCtl" ref="a8faa1c2c250fd8d50a1821f9f9a4c15f" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a8faa1c2c250fd8d50a1821f9f9a4c15f">powerManageCtl</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>Power Management Control Register </p>
+
+</div>
+</div>
+<a class="anchor" id="aeee9d593ff0901ec99ca9e7ebb3fa2f6"></a><!-- doxytag: member="iblEmif4p0_s::priClassSvceMap" ref="aeee9d593ff0901ec99ca9e7ebb3fa2f6" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#aeee9d593ff0901ec99ca9e7ebb3fa2f6">priClassSvceMap</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>DDR Priority to Class of Service Mapping Register </p>
+
+</div>
+</div>
+<a class="anchor" id="a512ad045f76a8a93b5bdad6a80cd2454"></a><!-- doxytag: member="iblEmif4p0_s::rdWrtExcThresh" ref="a512ad045f76a8a93b5bdad6a80cd2454" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a512ad045f76a8a93b5bdad6a80cd2454">rdWrtExcThresh</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>Read Write Execution Threshold Register </p>
+
+</div>
+</div>
+<a class="anchor" id="ae792d7050596145b63d50117d6220de3"></a><!-- doxytag: member="iblEmif4p0_s::readIdleCtl" ref="ae792d7050596145b63d50117d6220de3" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#ae792d7050596145b63d50117d6220de3">readIdleCtl</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>Read Idle Control Register </p>
+
+</div>
+</div>
+<a class="anchor" id="afc32bc65ce2cf71dd3c6e30a239af47e"></a><!-- doxytag: member="iblEmif4p0_s::registerMask" ref="afc32bc65ce2cf71dd3c6e30a239af47e" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#afc32bc65ce2cf71dd3c6e30a239af47e">registerMask</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>Identifies which registers will be configured </p>
+
+</div>
+</div>
+<a class="anchor" id="a5faf82fad83d39e53de237a13d512220"></a><!-- doxytag: member="iblEmif4p0_s::sdRamConfig" ref="a5faf82fad83d39e53de237a13d512220" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a5faf82fad83d39e53de237a13d512220">sdRamConfig</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>SDRAM Config Register </p>
+
+</div>
+</div>
+<a class="anchor" id="a8a03c562a21ec31b59c17c72bcddb4ec"></a><!-- doxytag: member="iblEmif4p0_s::sdRamConfig2" ref="a8a03c562a21ec31b59c17c72bcddb4ec" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a8a03c562a21ec31b59c17c72bcddb4ec">sdRamConfig2</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>SDRAM Config2 Register </p>
+
+</div>
+</div>
+<a class="anchor" id="a24b8b8f644cab72d004375d7ef597322"></a><!-- doxytag: member="iblEmif4p0_s::sdRamOutImpdedCalCfg" ref="a24b8b8f644cab72d004375d7ef597322" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a24b8b8f644cab72d004375d7ef597322">sdRamOutImpdedCalCfg</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>SDRAM Output Impedance Calibratin Config Register </p>
+
+</div>
+</div>
+<a class="anchor" id="afc1d0b4e38a8ce09b240abb20bc60116"></a><!-- doxytag: member="iblEmif4p0_s::sdRamRefreshCtl" ref="afc1d0b4e38a8ce09b240abb20bc60116" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#afc1d0b4e38a8ce09b240abb20bc60116">sdRamRefreshCtl</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>SDRAM Refresh Control Register </p>
+
+</div>
+</div>
+<a class="anchor" id="ae330e2ac1c489536400107dabe14229a"></a><!-- doxytag: member="iblEmif4p0_s::sdRamTiming1" ref="ae330e2ac1c489536400107dabe14229a" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#ae330e2ac1c489536400107dabe14229a">sdRamTiming1</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>SDRAM Timing 1 Register </p>
+
+</div>
+</div>
+<a class="anchor" id="ad34082e05339f2632e978dc42389a9e7"></a><!-- doxytag: member="iblEmif4p0_s::sdRamTiming2" ref="ad34082e05339f2632e978dc42389a9e7" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#ad34082e05339f2632e978dc42389a9e7">sdRamTiming2</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>SDRAM Timing 2 Register </p>
+
+</div>
+</div>
+<a class="anchor" id="a9bdbcede174de1bd60c4a2d06549d672"></a><!-- doxytag: member="iblEmif4p0_s::sdRamTiming3" ref="a9bdbcede174de1bd60c4a2d06549d672" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#a9bdbcede174de1bd60c4a2d06549d672">sdRamTiming3</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>SDRAM Timing 3 Register </p>
+
+</div>
+</div>
+<a class="anchor" id="aa6f4e601d939f54af799f78571f24cbc"></a><!-- doxytag: member="iblEmif4p0_s::sysVbusmIntEnSet" ref="aa6f4e601d939f54af799f78571f24cbc" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#aa6f4e601d939f54af799f78571f24cbc">sysVbusmIntEnSet</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>VBUSM Interrupt Enable Set Register </p>
+
+</div>
+</div>
+<a class="anchor" id="ac27fa6e3bf375487950e5a3b4a429ba7"></a><!-- doxytag: member="iblEmif4p0_s::tempAlterCfg" ref="ac27fa6e3bf375487950e5a3b4a429ba7" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32 <a class="el" href="structibl_emif4p0__s.html#ac27fa6e3bf375487950e5a3b4a429ba7">tempAlterCfg</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>Temperature Alert Config Register </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="ibl_8h_source.html">ibl.h</a></li>
+</ul>
+</div>
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+<hr class="footer"/><address class="footer"><small>Generated on Mon May 2 2011 12:50:34 for IBL Configuration by 
+<a href="http://www.doxygen.org/index.html">
+<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.4 </small></address>
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