diff --git a/src/cfg/c6472/iblcfg.h b/src/cfg/c6472/iblcfg.h
index 4cf552a8e3a110e091e0f5c9cce622c41518167c..672e30e57915c076b60b1b9d8e0f7dcba70cf318 100644 (file)
--- a/src/cfg/c6472/iblcfg.h
+++ b/src/cfg/c6472/iblcfg.h
#define NAND_CLE_GPIO_PIN GPIO_8 // High: Command Cycle occuring
#define NAND_ALE_GPIO_PIN GPIO_9 // High: Address input cycle oddcuring
#define NAND_NWE_GPIO_PIN GPIO_10
+#define NAND_BSY_GPIO_PIN GPIO_11 /* NAND Ready/Busy pin */
#define NAND_NRE_GPIO_PIN GPIO_12
#define NAND_NCE_GPIO_PIN GPIO_13
#define NAND_MODE_GPIO GPIO_14
* The standard NAND delay must be big enough to handle the highest possible
* operating frequency of the device */
#define TARGET_NAND_STD_DELAY 25 // In cpu cycles
+#define NAND_WAIT_PIN_POLL_ST_DLY (10000)