index 464c803910517288fd10d4e6b878603b368b2394..f23e6f5186792c9d65fa57b9ceb6d320cb006ec8 100644 (file)
*/
#define TARGET_PWR_NAND -1
+/**
+ * @brief
+ * The PSC number for GPIO. GPIO is in the always on domain
+ */
+#define TARGET_PWR_GPIO -1
+
/**
* @brief
* Device DDR controller definitions
*/
#define DEVICE_DDR_BASE 0x78000000
+#define targetEmifType() ibl_EMIF_TYPE_31
/**
* @brief
#define GPIO_SET_FAL_TRIG_REG 0x02B0002C
#define GPIO_CLR_FAL_TRIG_REG 0x02B00030
+#define ECC_BLOCK_SIZE 256
+
+/* NAND address pack macro */
+#define PACK_ADDR(col, page, block) \
+ ((col & 0x00000fff) | ((page & 0x0000003f)<<16) | ((block & 0x000003ff) << 22 ))
+
/**
* @brief
- * GPIO pin mapping
+ * The base address of the I2C peripheral, and the module divisor of the cpu clock
*/
-#define NAND_CLE_GPIO_PIN GPIO_8 // High: Command Cycle occuring
-#define NAND_ALE_GPIO_PIN GPIO_9 // High: Address input cycle oddcuring
-#define NAND_NWE_GPIO_PIN GPIO_10
-#define NAND_NRE_GPIO_PIN GPIO_12
-#define NAND_NCE_GPIO_PIN GPIO_13
-#define NAND_MODE_GPIO GPIO_14
+#define DEVICE_I2C_BASE 0x02b04000
+#define DEVICE_I2C_MODULE_DIVISOR 6
+
/**
* @brief
- * The standard NAND delay must be big enough to handle the highest possible
- * operating frequency of the device */
-#define TARGET_NAND_STD_DELAY 25 // In cpu cycles
+ * Register access macros
+ */
+#define DEVICE_REG32_W(x,y) *(volatile unsigned int *)(x)=(y)
+#define DEVICE_REG32_R(x) (*(volatile unsigned int *)(x))
+
+#define BOOTBITMASK(x,y) ( ( ( ((UINT32)1 << (((UINT32)x)-((UINT32)y)+(UINT32)1) ) - (UINT32)1 ) ) << ((UINT32)y) )
+#define BOOT_READ_BITFIELD(z,x,y) (((UINT32)z) & BOOTBITMASK(x,y)) >> (y)
+#define BOOT_SET_BITFIELD(z,f,x,y) (((UINT32)z) & ~BOOTBITMASK(x,y)) | ( (((UINT32)f) << (y)) & BOOTBITMASK(x,y) )
+
/**
* @brief
- * The base address of the I2C peripheral, and the module divisor of the cpu clock
+ * The c6455 supports only booting the ibl from i2c
*/
-#define DEVICE_I2C_BASE 0x02b04000
-#define DEVICE_I2C_MODULE_DIVISOR 6
+#define deviceReadBootDevice() BOOT_DEVICE_I2C
+#define IBL_ENTER_ROM 0
+#define iblEnterRom()
+#define IBL_ENABLE_EDC 0
+#define iblEnableEDC()
+
+